TLC0832AID [TI]

2-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8;
TLC0832AID
元器件型号: TLC0832AID
生产厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述和应用:

2-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8

光电二极管转换器
PDF文件: 总20页 (文件大小:905K)
下载文档:  下载PDF数据表文档文件
型号参数:TLC0832AID参数
是否Rohs认证 不符合
生命周期Obsolete
IHS 制造商TEXAS INSTRUMENTS INC
Reach Compliance Codenot_compliant
ECCN代码EAR99
HTS代码8542.39.00.01
风险等级5.73
最大模拟输入电压5.05 V
最小模拟输入电压-0.05 V
转换器类型ADC, SUCCESSIVE APPROXIMATION
JESD-30 代码R-PDSO-G8
长度4.9 mm
最大线性误差 (EL)1%
模拟输入通道数量2
位数8
功能数量1
端子数量8
最高工作温度85 °C
最低工作温度-40 °C
输出位码BINARY
输出格式SERIAL
封装主体材料PLASTIC/EPOXY
封装代码SOP
封装等效代码SOP8,.25
封装形状RECTANGULAR
封装形式SMALL OUTLINE
峰值回流温度(摄氏度)NOT SPECIFIED
电源5 V
认证状态Not Qualified
座面最大高度1.75 mm
子类别Analog to Digital Converters
最大压摆率5.2 mA
标称供电电压5 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子形式GULL WING
端子节距1.27 mm
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED
宽度3.9 mm
Base Number Matches1
MAX34334CSE前5页PDF页面详情预览
TLC0831C, TLC0831I
TLC0832C, TLC0832I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS107B – JANUARY 1995 – REVISED APRIL 1996
D
D
D
D
D
D
D
D
D
8-Bit Resolution
Easy Microprocessor Interface or
Standalone Operation
Operates Ratiometrically or With 5-V
Reference
Single Channel or Multiplexed Twin
Channels With Single-Ended or Differential
Input Options
Input Range 0 to 5 V With Single 5-V Supply
Inputs and Outputs Are Compatible With
TTL and MOS
Conversion Time of 32
µs
at
f
clock
= 250 kHz
Designed to Be Interchangeable With
National Semiconductor ADC0831 and
ADC0832
Total Unadjusted Error . . .
±
1 LSB
TLC0831 . . . D OR P PACKAGE
(TOP VIEW)
CS
IN+
IN–
GND
1
2
3
4
8
7
6
5
V
CC
CLK
DO
REF
TLC0832 . . . D OR P PACKAGE
(TOP VIEW)
CS
CH0
CH1
GND
1
2
3
4
8
7
6
5
V
CC
/REF
CLK
DO
DI
description
These devices are 8-bit successive-approximation analog-to-digital converters. The TLC0831 has single input
channels; the TLC0832 has multiplexed twin input channels. The serial output is configured to interface with
standard shift registers or microprocessors.
The TLC0832 multiplexer is software configured for single-ended or differential inputs. The differential analog
voltage input allows for common-mode rejection or offset of the analog zero input voltage value. In addition, the
voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of
resolution.
The operation of the TLC0831 and TLC0832 devices is very similar to the more complex TLC0834 and TLC0838
devices. Ratiometric conversion can be attained by setting the REF input equal to the maximum analog input
signal value, which gives the highest possible conversion resolution. Typically, REF is set equal to V
CC
(done
internally on the TLC0832).
The TLC0831C and TLC0832C are characterized for operation from 0°C to 70°C. The TLC0831I and TLC0832I
are characterized for operation from – 40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
TA
0°C to 70°C
– 40°C to 85°C
SMALL OUTLINE
(D)
TLC0831CD
TLC0831ID
TLC0832CD
TLC0832ID
PLASTIC DIP
(P)
TLC0831CP
TLC0831IP
TLC0832CP
TLC0832IP
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
©
1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
1
TLC0831C, TLC0831I
TLC0832C, TLC0832I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS107B – JANUARY 1995 – REVISED APRIL 1996
functional block diagram
CLK
CS
Shift Register
DI
(TLC0832
only)
D
CLK
ODD/EVEN
S
Start
R
CLK
Start
Flip-Flop
To Internal
Circuits
SGL/DIF
CLK
CH0/IN+
CH1/IN –
Analog
MUX
EN
S
Comparator
Time
Delay
R
CS
CS
EN
REF
(TLC0831
only)
Ladder
and
Decoder
Bits 0–7
R
EN
SAR
Logic
and
Latch
MSB
First
One
Shot
CS
CLK
Bits 0–7
Bit 1
LSB
First
R
EOC
CS
CS
R
CLK
D
DO
9-Bit
Shift
Register
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TLC0831C, TLC0831I
TLC0832C, TLC0832I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS107B – JANUARY 1995 – REVISED APRIL 1996
functional description
The TLC0831 and TLC0832 use a sample-data-comparator structure that converts differential analog inputs
by a successive-approximation routine. The input voltage to be converted is applied to an input terminal and
is compared to ground (single ended), or to an adjacent input (differential). The TLC0832 input terminals can
be assigned a positive (+) or negative (–) polarity. The TLC0831 contains only one differential input channel with
fixed polarity assignment; therefore it does not require addressing. The signal can be applied differentially,
between IN+ and IN–, to the TLC0831 or can be applied to IN+ with IN– grounded as a single ended input. When
the signal input applied to the assigned positive terminal is less than the signal on the negative terminal, the
converter output is all zeros.
Channel selection and input configuration are under software control using a serial-data link from the controlling
processor. A serial-communication format allows more functions to be included in a converter package with no
increase in size. In addition, it eliminates the transmission of low-level analog signals by locating the converter
at the analog sensor and communicating serially with the controlling processor. This process returns noise-free
digital data to the processor.
A conversion is initiated by setting CS low, which enables all logic circuits. CS must be held low for the complete
conversion process. A clock input is then received from the processor. An interval of one clock period is
automatically inserted to allow the selected multiplexed channel to settle. DO comes out of the high-impedance
state and provides a leading low for one clock period of multiplexer settling time. The SAR comparator compares
successive outputs from the resistive ladder with the incoming analog signal. The comparator output indicates
whether the analog input is greater than or less than the resistive-ladder output. As the conversion proceeds,
conversion data is simultaneously output from DO, with the most significant bit (MSB) first. After eight clock
periods, the conversion is complete. When CS goes high, all internal registers are cleared. At this time, the
output circuits go to the high-impedance state. If another conversion is desired, CS must make a high-to-low
transition followed by address information.
A TLC0832 input configuration is assigned during the multiplexer-addressing sequence. The multiplexer
address shifts into the converter through the data input (DI) line. The multiplexer address selects the analog
inputs to be enabled and determines whether the input is single ended or differential. When the input is
differential, the polarity of the channel input is assigned. In addition to selecting the differential mode, the polarity
may also be selected. Either channel of the channel pair may be designated as the negative or positive input.
On each low-to-high transition of the clock input, the data on DI is clocked into the multiplexer-address shift
register. The first logic high on the input is the start bit. A 2-bit assignment word follows the start bit on the
TLC0832. On each successive low-to-high transition of the clock input, the start bit and assignment word are
shifted through the shift register. When the start bit is shifted into the start location of the multiplexer register,
the input channel is selected and conversion starts. The TLC0832 DI terminal to the multiplexer shift register
is disabled for the duration of the conversion.
The TLC0832 outputs the least-significant-bit (LSB) first data after the MSB-first data stream. The DI and DO
terminals can be tied together and controlled by a bidirectional processor I/O bit received on a single wire. This
is possible because DI is only examined during the multiplexer-addressing interval and DO is still in the
high-impedance state.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
3
TLC0831C, TLC0831I
TLC0832C, TLC0832I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS107B – JANUARY 1995 – REVISED APRIL 1996
sequence of operation
TLC0831
1
CLK
tsu
tconv
CS
MUX
Settling Time
DO
Hi-Z
MSB
7
6
5
4
3
TLC0832
1
CLK
2
3
4
5
6
10
11
12
13
14
18
19
20
21
2
1
MSB-First Data
2
3
4
5
6
7
8
9
10
LSB
0
Hi-Z
tsu
CS
+Sign Bit
Start
Bit SGL ODD
DI
(TLC0832
only)
tconv
Don’t Care
DIF EVEN
MSB-First Data
MUX
Settling Time
LSB-First Data
Hi-Z
MSB
7
6
2
1
LSB
0
1
2
6
MSB
7
DO
TLC0832 MUX-ADDRESS CONTROL LOGIC TABLE
MUX ADDRESS
SGL/DIF
L
L
H
H
ODD/EVEN
L
H
L
H
CHANNEL NUMBER
CH0
+
+
CH1
+
+
H = high level, L = low level,
– or + = terminal polarity for the selected input channel
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TLC0831C, TLC0831I
TLC0832C, TLC0832I
8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS107B – JANUARY 1995 – REVISED APRIL 1996
absolute maximum ratings over recommended operating free-air temperature range (unless
otherwise noted)
Supply voltage, V
CC
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V
Input voltage range, V
I
: Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to V
CC
+ 0.3 V
Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to V
CC
+ 0.3 V
Input current, I
I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
5 mA
Total input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
20 mA
Operating free-air temperature range, T
A
: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: P package . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential voltages, are with respect to the network ground terminal.
recommended operating conditions
MIN
Supply voltage, VCC
High-level input voltage, VIH
Low-level input voltage, VIL
Clock frequency, fclock
Clock duty cycle (see Note 2)
Pulse duration, CS high, twH(CS)
Setup time, CS low or TLC0832 data valid before CLK↑, tsu
Hold time, TLC0832 data valid after CLK↑, th
Operating free-air temperature, TA
free air temperature
C suffix
I suffix
10
40%
220
350
90
0
– 40
70
85
4.5
2
0.8
600
60%
ns
ns
ns
°C
NOM
5
MAX
5.5
UNIT
V
V
V
kHz
NOTE 2: The clock-duty-cycle range ensures proper operation at all clock frequencies. When a clock frequency is used outside the
recommended duty-cycle range, the minimum pulse duration (high or low) is 1
µs.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
5
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