TL072_V01 [TI]
TL07xx Low-Noise FET-Input Operational Amplifiers;
| 型号： | TL072_V01 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TL07xx Low-Noise FET-Input Operational Amplifiers |
| 文件： | 总80页 (文件大小：4990K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TL071, TL071H, TL071A, TL071B
TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M
SLOS080P – SEPTEMBER 1978 – REVISED NOVEMBER 2020
TL07xx Low-Noise FET-Input Operational Amplifiers
(1.5 kV, HBM), integrated EMI and RF filters, and
operation across the full –40°C to 125°C enable the
1 Features
•
High slew rate: 20 V/μs (TL07xH, typ)
Low offset voltage: 1 mV (TL07xH, typ)
Low offset voltage drift: 2 μV/°C
Low power consumption: 940 μA/ch (TL07xH, typ)
Wide common-mode and differential
voltage ranges
– Common-mode input voltage range
includes VCC+
Low input bias and offset currents
Low noise:
TL07xH devices to be used in the most rugged and
demanding applications.
•
•
•
•
Device Information
PART NUMBER(1)
PACKAGE
BODY SIZE (NOM)
9.59 mm × 6.35 mm
2.00 mm × 1.25 mm
6.20 mm × 5.30 mm
4.90 mm × 3.90 mm
1.60 mm × 1.20 mm
9.59 mm × 6.35 mm
6.20 mm × 5.30 mm
4.90 mm × 3.90 mm
2.90 mm × 1.60 mm
4.40 mm × 3.00 mm
3.00 mm × 3.00 mm
9.59 mm × 6.67 mm
6.12 mm × 3.56 mm
8.89 mm × 8.89 mm
19.30 mm × 6.35 mm
10.30 mm × 5.30 mm
8.65 mm × 3.91 mm
4.20 mm × 2.00 mm
6.20 mm × 5.30 mm
5.00 mm × 4.40 mm
19.56 mm × 6.92 mm
9.21 mm × 6.29 mm
8.89 mm × 8.89 mm
PDIP (8)
SC70 (5)
SO (8)
TL071x
SOIC (8)
•
•
SOT-23 (5)
PDIP (8)
Vn = 18 nV/√ Hz (typ) at f = 1 kHz
Output short-circuit protection
Low total harmonic distortion: 0.003% (typ)
Wide supply voltage:
SO (8)
•
•
•
SOIC (8)
TL072x
TL072M
TL074x
TL074M
SOT-23 (8)
TSSOP (8)
VSSOP (8)
CDIP (8)
±2.25 V to ±20 V, 4.5 V to 40 V
2 Applications
•
•
Solar energy: string and central inverter
Motor drives: AC and servo drive control and
power stage modules
Single phase online UPS
Three phase UPS
CFP (10)
LCCC (20)
PDIP (14)
SO (14)
•
•
•
•
SOIC (14)
SOT-23 (14)
SSOP (14)
TSSOP (14)
CDIP (14)
CFP (14)
LCCC (20)
Pro audio mixers
Battery test equipment
3 Description
The TL07xH (TL071H, TL072H, and TL074H) family
of devices are the next-generation versions of the
industry-standard TL07x (TL071, TL072, and TL074)
devices. These devices provide outstanding value for
cost-sensitive applications, with features including low
offset (1 mV, typical), high slew rate (20 V/μs), and
common-mode input to the positive supply. High ESD
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
TL071
TL072 (each amplifier)
TL074 (each amplifier)
OFFSET N1
IN+
IN−
+
−
IN+
IN−
+
−
OUT
OUT
Copyright © 2017, Texas Instruments Incorporated
OFFSET N2
Logic Symbols
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TL071, TL071H, TL071A, TL071B
TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M
SLOS080P – SEPTEMBER 1978 – REVISED NOVEMBER 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications................................................................ 10
6.1 Absolute Maximum Ratings: TL07xH .......................10
6.2 Absolute Maximum Ratings: All Devices Except
TL07xH........................................................................10
6.3 ESD Ratings: TL07xH ..............................................10
6.4 ESD Ratings: All Devices Except TL07xH................ 11
6.5 Recommended Operating Conditions: TL07xH ....... 11
6.6 Recommended Operating Conditions: All
Devices Except TL07xH.............................................. 11
6.7 Thermal Information for Single Channel: TL071H ....11
6.8 Thermal Information: TL071x....................................12
6.9 Thermal Information for Dual Channel: TL072H ......12
6.10 Thermal Information: TL072x..................................12
6.11 Thermal Information: TL072x (cont.).......................13
6.12 Thermal Information for Quad Channel: TL074H ...13
6.13 Thermal Information: TL074x..................................13
6.14 Thermal Information: TL074x (cont)........................14
6.15 Thermal Information: TL074x (cont)........................14
6.16 Thermal Information................................................14
6.17 Electrical Characteristics: TL07xH .........................15
6.18 Electrical Characteristics: TL071C, TL072C,
6.23 Electrical Characteristics: TL071M, TL072M.......... 22
6.24 Electrical Characteristics: TL074M......................... 23
6.25 Switching Characteristics: TL07xM.........................24
6.26 Switching Characteristics: TL07xC, TL07xAC,
TL07xBC, TL07xI........................................................ 24
6.27 Electrical Characteristics, TL07xM..........................25
6.28 Switching Characteristics........................................25
6.29 Typical Characteristics: TL07xH............................. 26
6.30 Typical Characteristics: All Devices Except
TL07xH........................................................................33
7 Parameter Measurement Information..........................37
8 Detailed Description......................................................38
8.1 Overview...................................................................38
8.2 Functional Block Diagram.........................................38
8.3 Feature Description...................................................39
8.4 Device Functional Modes..........................................39
9 Application and Implementation..................................40
9.1 Application Information............................................. 40
9.2 Typical Application.................................................... 40
9.3 Unity Gain Buffer.......................................................41
9.4 System Examples..................................................... 42
10 Power Supply Recommendations..............................43
11 Layout...........................................................................43
11.1 Layout Guidelines................................................... 43
11.2 Layout Example...................................................... 44
12 Device and Documentation Support..........................45
12.1 Related Links.......................................................... 45
12.2 Receiving Notification of Documentation Updates..45
12.3 Support Resources................................................. 45
12.4 Trademarks.............................................................45
12.5 Electrostatic Discharge Caution..............................45
12.6 Glossary..................................................................45
13 Mechanical, Packaging, and Orderable
TL074C........................................................................17
6.19 Electrical Characteristics: TL071AC, TL072AC,
TL074AC..................................................................... 18
6.20 Electrical Characteristics: TL071BC, TL072BC,
TL074BC..................................................................... 19
6.21 Electrical Characteristics: TL071I, TL072I,
TL074I......................................................................... 20
6.22 Electrical Characteristics, TL07xC, TL07xAC,
Information.................................................................... 45
TL07xBC, TL07xI........................................................ 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision O (October 2020) to Revision P (November 2020)
Page
•
Added SOIC and TSSOP package thermal information in Thermal Information for Quad Channel: TL074H
section ........................................................................................................................................................... 13
•
Added Typical Characteristics:TL07xH section in Specifications section......................................................... 26
Changes from Revision N (July 2017) to Revision O (October 2020)
Page
•
•
•
•
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•
Updated the numbering format for tables, figures, and cross-references throughout the document..................1
Features of TL07xH added to the Features section........................................................................................... 1
Added link to applications in the Applications section........................................................................................ 1
Added TL07xH in the Description section...........................................................................................................1
Added TL07xH device in the Device Information section................................................................................... 1
Added SOT-23 (14), VSSOP (8), SOT-23 (8), SC70 (5), and SOT-23 (5) packages to the Device Information
section................................................................................................................................................................ 1
Added TSSOP, VSSOP and DDF packages to TL072x in Pin Configuration and Functions section................. 4
•
Copyright © 2020 Texas Instruments Incorporated
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SLOS080P – SEPTEMBER 1978 – REVISED NOVEMBER 2020
•
•
•
•
Added DYY package to TL074x in Pin Configuration and Functions section.....................................................4
Removed Table of Graphs from the Typical Characteistics section..................................................................33
Deleted reference to obsolete documentation in Layout Guidelines section....................................................43
Removed Related Documentation section....................................................................................................... 45
Changes from Revision M (February 2014) to Revision N (July 2017)
Page
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Updated data sheet text to latest documentation and translation standards......................................................1
Added TL072M and TL074M devices to data sheet ..........................................................................................1
Rewrote text in Description section ................................................................................................................... 1
Changed TL07x 8-pin PDIP package to 8-pin CDIP package in Device Information table ............................... 1
Deleted 20-pin LCCC package from Device Information table ..........................................................................1
Added 2017 copyright statement to front page schematic..................................................................................1
Deleted TL071x FK (LCCC) pinout drawing and pinout table in Pin Configurations and Functions section ..... 4
Updated pinout diagrams and pinout tables in Pin Configurations and Functions section ................................4
Deleted differential input voltage parameter from Absolute Maximum Ratings table ...................................... 10
Deleted table notes from Absolute Maximum Ratings table ............................................................................10
Added new table note to Absolute Maximum Ratings table ............................................................................ 10
Changed minimum supply voltage value from –18 V to –0.3 V in Absolute Maximum Ratings table...............10
Changed maximum supply voltage from 18 V to 36 V in Absolute Maximum Ratings table............................ 10
Changed minimum input voltage value from –15 V to VCC– – 0.3 V in Absolute Maximum Ratings table....... 10
Changed maximum input voltage from 15 V to VCC– + 36 V in Absolute Maximum Ratings table...................10
Added input clamp current parameter to Absolute Maximum Ratings table ....................................................10
Changed common-mode voltage maximum value from VCC+ – 4 V to VCC+ in the Recommended Operating
Conditions table................................................................................................................................................ 11
Changed devices in Recommended Operating Conditions table from TL07xA and TL07xB to TL07xAC and
TL07xBC ..........................................................................................................................................................11
Added TL07xI operating free-air temperature minimum value of –40°C to Recommended Operating
Conditions table ............................................................................................................................................... 11
Added U (CFP) package thermal values to Thermal Information: TL072x (cont.) table...................................13
Added W (CFP) package thermal values to Thermal Information: TL074x (cont.) table.................................. 14
Added Figure 6-59 to Typical Characteristics section.......................................................................................33
Added second Typical Application section application curves .........................................................................41
Reformatted document references in Layout Guidelines section .................................................................... 43
•
•
•
•
•
•
•
Changes from Revision L (February 2014) to Revision M (February 2014)
Page
•
Added Device Information table, Pin Configuration and Functions section, ESD Ratings table, Feature
Description section, Device Functional Modes, Application and Implementation section, Power Supply
Recommendations section, Layout section........................................................................................................ 1
Changes from Revision K (January 2014) to Revision L (February 2014)
Page
•
Moved Tstg to Handling Ratings table .............................................................................................................. 11
Changes from Revision J (March 2005) to Revision K (January 2014)
Page
•
Updated document to new TI datasheet format - no specification changes.......................................................1
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Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A
TL074B TL072M TL074M
TL071, TL071H, TL071A, TL071B
TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M
SLOS080P – SEPTEMBER 1978 – REVISED NOVEMBER 2020
www.ti.com
5 Pin Configuration and Functions
OFFSET N1
INœ
1
2
3
4
8
7
6
5
NC
VCC+
IN+
OUT
VCCœ
OFFSET N2
Not to scale
NC- no internal connection
Figure 5-1. TL071x D, P, and PS Package
8-Pin SOIC, PDIP, and SO
Top View
Table 5-1. Pin Functions: TL071x
PIN
I/O
DESCRIPTION
NAME
NO.
2
IN–
I
Inverting input
IN+
3
I
Noninverting input
Do not connect
Input offset adjustment
Input offset adjustment
Output
NC
8
—
—
—
O
—
—
OFFSET N1
OFFSET N2
OUT
1
5
6
VCC–
VCC+
4
Power supply
7
Power supply
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TL074B TL072M TL074M
TL071, TL071H, TL071A, TL071B
TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M
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SLOS080P – SEPTEMBER 1978 – REVISED NOVEMBER 2020
1OUT
1INœ
1
2
3
4
8
7
6
5
VCC+
2OUT
2INœ
1IN+
VCCœ
2IN+
Not to scale
Figure 5-2. TL072x D, DDF, DGK, JG, P, PS, and PW Package
8-Pin SOIC, SOT-23 (8), VSSOP, CDIP, PDIP, SO, and TSSOP
Top View
Table 5-2. Pin Functions: TL072x
PIN
I/O
DESCRIPTION
NAME
1IN–
NO.
2
I
I
Inverting input
Noninverting input
Output
1IN+
3
1OUT
2IN–
1
O
I
6
Inverting input
Noninverting input
Output
2IN+
5
I
2OUT
VCC–
VCC+
7
O
—
—
4
Power supply
Power supply
8
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TL074B TL072M TL074M
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TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M
SLOS080P – SEPTEMBER 1978 – REVISED NOVEMBER 2020
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NC
1OUT
1INœ
1
2
3
4
5
10
9
NC
VCC+
2OUT
2INœ
2IN+
8
1IN+
7
VCCœ
6
Not to scale
NC- no internal connection
Figure 5-3. TL072x U Package
10-Pin CFP
Top View
Table 5-3. Pin Functions: TL072x
PIN
I/O
DESCRIPTION
NAME
NO.
1IN–
1IN+
1OUT
2IN–
2IN+
2OUT
NC
3
I
I
Inverting input
Noninverting input
Output
4
2
O
I
7
Inverting input
Noninverting input
Output
6
8
I
O
—
—
—
1, 10
5
Do not connect
Power supply
Power supply
VCC–
VCC+
9
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SLOS080P – SEPTEMBER 1978 – REVISED NOVEMBER 2020
NC
1INœ
NC
4
5
6
7
8
18
17
16
15
14
NC
2OUT
NC
1IN+
NC
2INœ
NC
Not to scale
NC- no internal connection
Figure 5-4. TL072 FK Package
20-Pin LCCC
Top View
Table 5-4. Pin Functions: TL072x
PIN
I/O
DESCRIPTION
NAME
1IN–
NO.
5
I
I
Inverting input
Noninverting input
Output
1IN+
7
1OUT
2IN–
2
O
I
15
12
Inverting input
Noninverting input
Output
2IN+
I
2OUT
17
O
1, 3, 4, 6, 8,
NC
9, 11, 13, 14,
16, 18, 19
—
Do not connect
VCC–
VCC+
10
20
—
—
Power supply
Power supply
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Product Folder Links: TL071 TL071H TL071A TL071B TL072 TL072H TL072A TL072B TL074 TL074H TL074A
TL074B TL072M TL074M
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TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M
SLOS080P – SEPTEMBER 1978 – REVISED NOVEMBER 2020
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1OUT
1INœ
1
2
3
4
5
6
7
14
13
12
11
10
9
4OUT
4INœ
1IN+
4IN+
VCC+
2IN+
VCCœ
3IN+
2INœ
3INœ
2OUT
8
3OUT
Not to scale
Figure 5-5. TL074x D, N, NS, PW, J, DYY, and W Packages
14-Pin SOIC, PDIP, SO, TSSOP, CDIP, SOT-23 (14), and CFP
Top View
Table 5-5. Pin Functions: TL074x
PIN
I/O
DESCRIPTION
NAME
1IN–
NO.
2
I
I
Inverting input
Noninverting input
Output
1IN+
1OUT
2IN–
3
1
O
I
6
Inverting input
Noninverting input
Output
2IN+
2OUT
3IN–
5
I
7
O
I
9
Inverting input
Noninverting input
Output
3IN+
3OUT
4IN–
10
8
I
O
I
13
12
14
11
4
Inverting input
Noninverting input
Output
4IN+
4OUT
VCC–
VCC+
I
O
—
—
Power supply
Power supply
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SLOS080P – SEPTEMBER 1978 – REVISED NOVEMBER 2020
1IN+
NC
4
5
6
7
8
18
17
16
15
14
4IN+
NC
VCC+
NC
VCCœ
NC
2IN+
3IN+
Not to scale
NC- no internal connection
Figure 5-6. TL074 FK Package
20-Pin LCCC
Top View
Table 5-6. Pin Functions: TL074x
PIN
I/O
DESCRIPTION
NAME
1IN–
NO.
3
I
I
Inverting input
Noninverting input
Output
1IN+
4
1OUT
2IN–
2
O
I
9
Inverting input
Noninverting input
Output
2IN+
8
I
2OUT
3IN–
10
13
14
12
19
18
20
O
I
Inverting input
Noninverting input
Output
3IN+
I
3OUT
4IN–
O
I
Inverting input
Noninverting input
Output
4IN+
I
4OUT
O
1, 5, 7, 11, 15,
17
NC
—
Do not connect
VCC–
VCC+
16
6
—
—
Power supply
Power supply
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TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M
SLOS080P – SEPTEMBER 1978 – REVISED NOVEMBER 2020
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6 Specifications
6.1 Absolute Maximum Ratings: TL07xH
over operating ambient temperature range (unless otherwise noted) (1)
MIN
MAX
42
UNIT
V
Supply voltage, VS = (VCC+) – (VCC–
)
0
Common-mode voltage (3)
Differential voltage (3)
Current (3)
(VCC–) – 0.5
(VCC+) + 0.5
VS + 0.2
10
V
Signal input pins
V
–10
–55
–65
mA
Output short-circuit (2)
Continuous
Operating ambient temperature, TA
Junction temperature, TJ
150
150
150
°C
°C
°C
Storage temperature, Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Short-circuit to ground, one amplifier per package.
(3) Input pins are diode-clamped to the power-supply rails. Input signals that may swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
6.2 Absolute Maximum Ratings: All Devices Except TL07xH
over operating free-air temperature range (unless otherwise noted) (1)
MIN
–0.3
MAX
36
UNIT
V
VCC+ - VCC– Supply voltage
VI
Input voltage (3)
VCC– – 0.3
VCC– + 36
–50
V
IIK
Input clamp current
mA
Duration of output short circuit(2)
Operating virtual junction temperature
Case temperature for 60 seconds - FK package
Lead temperature 1.8 mm (1/16 inch) from case for 10 seconds
Storage temperature
Unlimited
TJ
150
260
300
150
°C
°C
°C
°C
Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The output may be shorted to ground or to either supply. Temperature and supply voltages must be limited to ensure that the
dissipation rating is not exceeded.
(3) Differential voltage only limited by input voltage.
6.3 ESD Ratings: TL07xH
VALUE
±1500
±1000
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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SLOS080P – SEPTEMBER 1978 – REVISED NOVEMBER 2020
6.4 ESD Ratings: All Devices Except TL07xH
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.5 Recommended Operating Conditions: TL07xH
over operating ambient temperature range (unless otherwise noted)
MIN
4.5
MAX
UNIT
V
VS
VI
Supply voltage, (VCC+) – (VCC–
)
40
(VCC+) + 0.1
125
Input voltage range
(VCC–) + 2
–40
V
TA
Specified temperature
°C
6.6 Recommended Operating Conditions: All Devices Except TL07xH
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC+
VCC–
VCM
Supply voltage (1)
5
–5
15
–15
VCC+
125
125
85
V
V
V
Supply voltage (1)
Common-mode voltage
VCC– + 4
–55
TL07xM
TL08xQ
–40
TA
Operating free-air temperature
°C
TL07xI
–40
TL07xAC, TL07xBC, TL07xC
0
70
(1) VCC+ and VCC– are not required to be of equal magnitude, provided that the total VCC (VCC+ – VCC–) is between 10 V and 30 V.
6.7 Thermal Information for Single Channel: TL071H
TL071H
D (2)
(SOIC)
DBV (2)
(SOT-23)
THERMAL METRIC (1)
UNIT
8 PINS
TBD
TBD
TBD
TBD
TBD
TBD
5 PINS
TBD
TBD
TBD
TBD
TBD
TBD
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) This package option is preview for TL071H.
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6.8 Thermal Information: TL071x
TL071x
P (PDIP)
THERMAL METRIC(1)
D (SOIC)
8 PINS
97
PS (SO)
8 PINS
95
UNIT
8 PINS
85
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
—
—
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.9 Thermal Information for Dual Channel: TL072H
TL072H
D (2)
(SOIC)
DGK (2)
(VSSOP)
PW (2)
(TSSOP)
THERMAL METRIC (1)
UNIT
8 PINS
8 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
TBD
TBD
TBD
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal
resistance
RθJC(top)
RθJB
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Junction-to-board thermal resistance
Junction-to-top characterization
parameter
ψJT
Junction-to-board characterization
parameter
ψJB
TBD
TBD
TBD
TBD
TBD
TBD
°C/W
°C/W
Junction-to-case (bottom) thermal
resistance
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) This package option is preview for TL072H.
6.10 Thermal Information: TL072x
TL072x
THERMAL METRIC(1)
D (SOIC)
8 PINS
97
JG (CDIP)
8 PINS
—
P (PDIP)
8 PINS
85
PS (SO)
8 PINS
95
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
—
15.05
—
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SLOS080P – SEPTEMBER 1978 – REVISED NOVEMBER 2020
6.11 Thermal Information: TL072x (cont.)
TL072x
U (CFP)
10 PINS
169.8
62.1
THERMAL METRIC(1)
PW (TSSOP)
FK (LCCC)
UNIT
8 PINS
150
—
20 PINS
—
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
5.61
—
—
176.2
48.4
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
—
—
ψJB
—
144.1
5.4
—
RθJC(bot)
—
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.12 Thermal Information for Quad Channel: TL074H
TL074H
D
PW
(TSSOP)
THERMAL METRIC (1)
UNIT
(SOIC)
14 PINS
114.2
70.3
14 PINS
134.4
62.6
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
RθJC(top)
RθJB
°C/W
°C/W
°C/W
°C/W
°C/W
70.2
77.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
28.8
13.0
ψJB
69.8
77.0
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.13 Thermal Information: TL074x
TL074x
THERMAL METRIC(1)
D (SOIC)
14 PINS
86
N (PDIP)
14 PINS
80
NS (SO)
14 PINS
76
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
RθJC(top)
—
—
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.14 Thermal Information: TL074x (cont).
TL074x
THERMAL METRIC(1)
J (CDIP)
PW (TSSOP)
W (CFP)
14 PINS
128.8
56.1
UNIT
14 PINS
—
14 PINS
113
—
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
14.5
—
—
127.6
29
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
—
—
ψJB
—
—
106.1
0.5
RθJC(bot)
—
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.15 Thermal Information: TL074x (cont).
TL074x
THERMAL METRIC(1)
FK (LCCC)
20 PINS
—
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
RθJC(top)
5.61
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.16 Thermal Information
TL071/TL072/TL074
FK
D (SOIC)
J (CDIP)
N (PDIP)
NS (SO)
PW (TSSOP)
THERMAL METRIC(1)
(LCCC)
UNIT
14
PINS
14
PINS
14
PINS
8
14
8 PINS
97
20 PINS 8 PINS
8 PINS
85
8 PINS 14 PINS
PINS PINS
Junction-to-ambient
thermal resistance
RθJA
RθJC(top)
86
—
—
—
80
95
—
76
—
150
—
113
—
°C/W
°C/W
Junction-to-case (top)
thermal resistance
—
—
5.61
15.05
14.5
—
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SLOS080P – SEPTEMBER 1978 – REVISED NOVEMBER 2020
6.17 Electrical Characteristics: TL07xH
For VS = (VCC+) – (VCC–) = 4.5 V to 40 V (±2.25 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VO UT = VS / 2, unless otherwise noted.
PARAMETER
OFFSET VOLTAGE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±1
±4
±5
VOS
Input offset voltage
mV
TA = –40°C to 125°C
dVOS/dT
PSRR
Input offset voltage drift
TA = –40°C to 125°C
TA = –40°C to 125°C
±2
±1
10
µV/℃
μV/V
µV/V
Input offset voltage
versus power supply
VS = 5 V to 40 V, VCM = V
S / 2
±10
Channel separation
f = 0 Hz
INPUT BIAS CURRENT
±1
±120
±5
pA
nA
pA
nA
IB
Input bias current
TA = –40°C to 125°C (1)
TA = –40°C to 125°C (1)
±0.5
±120
±5
IOS
Input offset current
NOISE
EN
9.2
1.4
37
μVPP
Input voltage noise
f = 0.1 Hz to 10 Hz
µVRMS
f = 1 kHz
f = 10 kHz
f = 1 kHz
Input voltage noise
density
eN
iN
nV/√Hz
fA/√Hz
21
Input current noise
80
INPUT VOLTAGE RANGE
Common-mode voltage
range
(VCC–) +
1.5
VCM
(VCC+
)
V
Common-mode
rejection ratio
CMRR
CMRR
CMRR
CMRR
100
95
105
105
dB
dB
dB
dB
VS = 40 V, (VCC–) + 2.5 V
< VCM < (VCC+) – 1.5 V
Common-mode
rejection ratio
TA = –40°C to 125°C
TA = –40°C to 125°C
Common-mode
rejection ratio
90
VS = 40 V, (VCC–) + 2.5 V
< VCM < (VCC+
)
Common-mode
rejection ratio
80
INPUT CAPACITANCE
ZID
Differential
100 || 2
6 || 1
MΩ || pF
TΩ || pF
ZICM
Common-mode
OPEN-LOOP GAIN
VS = 40 V, VCM = VS / 2,
AOL
Open-loop voltage gain (VCC–) + 0.3 V < VO < (V TA = –40°C to 125°C
CC+) – 0.3 V
118
115
125
120
dB
dB
VS = 40 V, VCM = VS / 2,
Open-loop voltage gain RL = 2 kΩ, (VCC–) + 1.2 V TA = –40°C to 125°C
< VO < (VCC+) – 1.2 V
AOL
FREQUENCY RESPONSE
Gain-bandwidth
product
GBW
5.25
20
MHz
V/μs
SR
Slew rate
VS = 40 V, G = +1, CL = 20 pF
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For VS = (VCC+) – (VCC–) = 4.5 V to 40 V (±2.25 V to ±20 V) at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and
VO UT = VS / 2, unless otherwise noted.
PARAMETER
Settling time
Phase margin
TEST CONDITIONS
MIN
TYP
MAX
UNIT
To 0.1%, VS = 40 V, VSTEP = 10 V , G = +1, CL = 20
pF
0.63
To 0.1%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20
pF
0.56
0.91
0.48
tS
μs
To 0.01%, VS = 40 V, VSTEP = 10 V , G = +1, CL =
20 pF
To 0.01%, VS = 40 V, VSTEP = 2 V , G = +1, CL = 20
pF
G = +1, RL = 10kΩ, CL = 20 pF
56
°
Overload recovery time VIN × gain > VS
Total harmonic
300
ns
THD+N
VS = 40 V, VO = 6 VRMS, G = +1, f = 1 kHz
0.00012
53
%
distortion + noise
EMIRR
EMI rejection ratio
f = 1 GHz
dB
OUTPUT
VS = 40 V, RL = 10 kΩ
VS = 40 V, RL = 2 kΩ
VS = 40 V, RL = 10 kΩ
VS = 40 V, RL = 2 kΩ
115
520
105
500
±26
300
210
965
Positive rail headroom
Negative rail headroom
Voltage output swing
from rail
mV
215
1030
ISC
Short-circuit current
Capacitive load drive
mA
pF
CLOAD
Open-loop output
impedance
ZO
f = 1 MHz, IO = 0 A
125
Ω
POWER SUPPLY
937.5
60
1125
1130
Quiescent current per
amplifier
IQ
IO = 0 A
µA
μs
TA = –40°C to 125°C
Turn-On Time
At TA = 25°C, VS = 40 V, VS ramp rate > 0.3 V/µs
(1) Max IB and Ios data is specified based on characterization results.
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SLOS080P – SEPTEMBER 1978 – REVISED NOVEMBER 2020
6.18 Electrical Characteristics: TL071C, TL072C, TL074C
VCC± = ±15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS (1) (2)
TA = 25°C
MIN
TYP
MAX UNIT
3
10
mV
13
VO = 0
RS = 50 Ω
VIO
Input offset voltage
TA = Full range
Temperature coefficient of
input offset voltage
VO = 0
RS = 50 Ω
α
TA = Full range
18
5
µV/°C
TA = 25°C
100
10
pA
nA
pA
nA
IIO
Input offset current
Input bias current (3)
VO = 0
TA = Full range
TA = 25°C
65
200
7
IIB
VO = 0
TA = Full range
Common-mode input voltage
range
VICR
TA = 25°C
±11 –12 to 15
V
RL= 10 kΩ
RL≥ 10 kΩ
RL≥ 2 kΩ
TA = 25°C
±12
±12
±10
25
±13.5
Maximum peak output
voltage swing
VOM
V
TA = Full range
TA = 25°C
200
Large-signal differential
voltage amplification
VO = ±10 V
RL≥ 2 kΩ
AVD
V/mV
TA = Full range
15
B1
rI
Utility-gain bandwidth
Input resistance
TA = 25°C
TA = 25°C
3
MHz
Ω
1012
VIC = VICR(min)
VO = 0
RS = 50 Ω
Common-mode rejection
ratio
CMRR
TA = 25°C
70
70
100
100
dB
dB
VCC = ±9 V to ±15 V
VO = 0
RS = 50 Ω
Supply voltage rejection ratio
kSVR
TA = 25°C
(ΔVCC±/ΔVIO
)
Supply current (each
amplifier)
ICC
VO = 0; no load
AVD = 100
TA = 25°C
TA = 25°C
1.4
2.5
mA
dB
VO1 / VO2 Crosstalk attenuation
120
(1) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified.
(2) Full range is TA = 0°C to 70°C.
(3) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 6-40. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as
possible.
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MAX UNIT
SLOS080P – SEPTEMBER 1978 – REVISED NOVEMBER 2020
6.19 Electrical Characteristics: TL071AC, TL072AC, TL074AC
VCC± = ±15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS (1) (2)
TA = 25°C
MIN
TYP
3
6
mV
7.5
VO = 0
RS = 50 Ω
VIO
Input offset voltage
TA = Full range
Temperature coefficient of
input offset voltage
VO = 0
RS = 50 Ω
α
TA = Full range
18
5
µV/°C
TA = 25°C
100
2
pA
nA
pA
nA
IIO
Input offset current
Input bias current (3)
VO = 0
TA = Full range
TA = 25°C
65
200
7
IIB
VO = 0
TA = Full range
Common-mode input voltage
range
VICR
TA = 25°C
±11 –12 to 15
V
RL= 10 kΩ
RL≥ 10 kΩ
RL≥ 2 kΩ
TA = 25°C
±12
±12
±10
50
±13.5
Maximum peak output
voltage swing
VOM
V
TA = Full range
TA = 25°C
200
Large-signal differential
voltage amplification
VO = ±10 V
RL≥ 2 kΩ
AVD
V/mV
TA = Full range
25
B1
rI
Utility-gain bandwidth
Input resistance
TA = 25°C
3
MHz
Ω
TA = 25°C
1012
VIC = VICR(min)
CMRR
Common-mode rejection ratio VO = 0
RS = 50 Ω
TA = 25°C
75
80
100
100
dB
dB
VCC = ±9 V to ±15 V
VO = 0
Supply-voltage rejection ratio
(ΔVCC± / ΔVIO
kSVR
TA = 25°C
)
RS = 50 Ω
Supply current
(each amplifier)
ICC
VO = 0; no load
AVD = 100
TA = 25°C
TA = 25°C
1.4
2.5
mA
dB
VO1 / VO2 Crosstalk attenuation
120
(1) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified.
(2) Full range is TA = 0°C to 70°C.
(3) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 6-40. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as
possible.
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SLOS080P – SEPTEMBER 1978 – REVISED NOVEMBER 2020
6.20 Electrical Characteristics: TL071BC, TL072BC, TL074BC
VCC± = ±15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS (1) (2)
TA = 25°C
MIN
TYP
MAX UNIT
2
3
VO = 0
RS = 50 Ω
VIO
Input offset voltage
mV
5
TA = Full range
Temperature coefficient of
input offset voltage
VO = 0
RS = 50 Ω
α
TA = Full range
18
5
µV/°C
TA = 25°C
100
2
pA
nA
pA
nA
IIO
Input offset current
Input bias current (3)
VO = 0
TA = Full range
TA = 25°C
65
200
7
IIB
VO = 0
TA = Full range
Common-mode input
voltage range
VICR
TA = 25°C
±11
–12 to 15
±13.5
V
RL= 10 kΩ
RL≥ 10 kΩ
RL≥ 2 kΩ
TA = 25°C
±12
±12
±10
50
Maximum peak output
voltage swing
VOM
V
TA = Full range
TA = 25°C
200
Large-signal differential
voltage amplification
VO = ±10 V
RL ≥ 2 kΩ
AVD
V/mV
TA = Full range
25
B1
rI
Utility-gain bandwidth
Input resistance
TA = 25°C
TA = 25°C
3
MHz
Ω
1012
VIC = VICR(min)
VO = 0
RS = 50 Ω
Common-mode rejection
ratio
CMRR
TA = 25°C
75
80
100
100
dB
dB
VCC = ±9 V to ±15 V
VO = 0
RS = 50 Ω
Supply-voltage rejection
kSVR
TA = 25°C
ratio (ΔVCC±/ΔVIO
)
Supply current (each
amplifier)
ICC
VO = 0; no load
AVD = 100
TA = 25°C
TA = 25°C
1.4
2.5 mA
dB
VO1 / VO2 Crosstalk attenuation
120
(1) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified.
(2) Full range is TA = 0°C to 70°C.
(3) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 6-40. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as
possible.
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MAX UNIT
SLOS080P – SEPTEMBER 1978 – REVISED NOVEMBER 2020
6.21 Electrical Characteristics: TL071I, TL072I, TL074I
VCC± = ±15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS (1) (2)
MIN
TYP
TA = 25°C
3
6
VO = 0
RS = 50 Ω
VIO
Input offset voltage
mV
8
TA = Full range
Temperature coefficient of
input offset voltage
VO = 0
RS = 50 Ω
α
TA = Full range
18
5
µV/°C
TA = 25°C
100
2
pA
nA
pA
nA
IIO
Input offset current
Input bias current (3)
VO = 0
TA = Full range
TA = 25°C
65
200
7
IIB
VO = 0
TA = Full range
Common-mode input voltage
range
VICR
TA = 25°C
±11
–12 to 15
±13.5
V
RL= 10 kΩ
RL ≥ 10 kΩ
RL ≥ 2 kΩ
TA = 25°C
±12
±12
±10
50
Maximum peak output
voltage swing
VOM
V
TA = Full range
TA = 25°C
200
Large-signal differential
voltage amplification
VO = ±10 V
RL ≥ 2 kΩ
AVD
V/mV
TA = Full range
25
B1
rI
Utility-gain bandwidth
Input resistance
TA = 25°C
TA = 25°C
3
MHz
Ω
1012
VIC = VICR(min)
VO = 0
RS = 50 Ω
Common-mode rejection
ratio
CMRR
TA = 25°C
TA = 25°C
75
80
100
100
dB
dB
VCC = ±9 V to ±15 V
VO = 0
RS = 50 Ω
Supply-voltage rejection
kSVR
ratio (ΔVCC±/ΔVIO
)
Supply current (each
amplifier)
ICC
VO = 0; no load
AVD = 100
TA = 25°C
TA = 25°C
1.4
2.5
mA
dB
VO1 / VO2 Crosstalk attenuation
120
(1) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified.
(2) TA = –40°C to 85°C.
(3) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 6-40. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as
possible.
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6.22 Electrical Characteristics, TL07xC, TL07xAC, TL07xBC, TL07xI
VCC± = ±15 V (unless otherwise noted)
TL071C, TL072C,
TL074C
TL071AC, TL072AC,
TL074AC
TL071BC, TL072BC,
TL074BC
TL071I, TL072I, TL074I
TEST CONDITIONS (1)
TA
UNIT
(2)
PARAMETER
MIN
TYP MAX
MIN
TYP MAX
MIN
TYP MAX
MIN
TYP MAX
25°C
3
10
13
3
6
2
3
5
3
6
8
Input offset
voltage
VIO
VO = 0,
VO = 0,
RS = 50 Ω
RS = 50 Ω
mV
Full range
7.5
Temperature
coefficient of
input offset
voltage
αVIO
Full range
18
5
18
5
18
5
18
5
µV/°C
25°C
Full range
25°C
100
10
100
2
100
2
100
2
pA
nA
pA
nA
Input offset
current
IIO
VO = 0
VO = 0
65
200
7
65
200
7
65
200
7
65
200
7
Input bias
current(3)
IIB
Full range
Common-mode
input voltage
range
–12
to
15
–12
to
15
–12
to
15
–12
to
15
VICR
25°C
±11
±11
±11
±11
V
V
RL= 10 kΩ
25°C
Full range
25°C
±12
±12
±10
25
±13.5
±12
±12
±10
50
±13.5
±12
±12
±10
50
±13.5
±12
±12
±10
50
±13.5
Maximum peak
output voltage RL≥ 10 kΩ
swing
VOM
RL≥ 2 kΩ
Large-signal
200
200
200
200
differential
voltage
amplification
VO = ±10
V,
AVD
RL≥ 2 kΩ
V/mV
Full range
15
25
25
25
Utility-gain
bandwidth
B1
rI
25°C
25°C
3
3
3
3
MHz
Ω
Input
resistance
1012
1012
1012
1012
VIC = VICRmin,
Common-mode
rejection ratio
CMRR
kSVR
25°C
25°C
70
70
100
100
75
80
100
100
75
80
100
100
75
80
100
100
dB
dB
VO = 0,
RS = 50 Ω
Supply-voltage VCC = ±9 V to ±15 V,
rejection ratio
VO = 0,
RS = 50 Ω
(ΔVCC±/ΔVIO
)
Supply current
(each amplifier)
ICC
VO = 0,
No load
25°C
25°C
1.4
2.5
1.4
2.5
1.4
2.5
1.4
2.5
mA
dB
Crosstalk
attenuation
VO1 /VO2
AVD = 100
120
120
120
120
(1) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified.
(2) Full range is TA = 0°C to 70°C for TL07_C,TL07_AC, TL07_BC and is TA = –40°C to 85°C for TL07_I.
(3) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 6-40. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as
possible.
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6.23 Electrical Characteristics: TL071M, TL072M
VCC± = ±15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS (1) (2)
MIN
TYP
MAX UNIT
TA = 25°C
3
6
9
VO = 0
RS = 50 Ω
VIO
αVIO
IIO
Input offset voltage
mV
TA = Full range
Temperature coefficient VO = 0
TA = Full range
18
5
μV/°C
of input offset voltage
RS = 50 Ω
TA = 25°C
100
20
pA
nA
pA
nA
Input offset current
VO = 0
TA = Full range
TA = 25°C
65
200
50
IIB
Input bias current
VO = 0
TA = Full range
Common-mode input
voltage range
VICR
TA = 25°C
±11 –12 to 15
V
RL = 10 kΩ
RL ≥ 10 kΩ
RL ≥ 2 kΩ
TA = 25°C
±12
±12
±10
35
±13.5
Maximum peak output
voltage swing
VOM
V
TA = Full range
TA = 25°C
200
Large-signal differential VO = ±10 V
AVD
V/mV
voltage amplification
RL ≥ 2 kΩ
TA = Full range
15
B1
ri
Unity-gain bandwidth
Input resistance
3
MHz
Ω
1012
VIC = VICR(min)
VO = 0
RS = 50 Ω
,
Common-mode rejection
ratio
CMRR
kSVR
TA = 25°C
TA = 25°C
80
80
86
86
dB
dB
VCC = ±9 V to ±15 V
VO = 0
RS = 50 Ω
Supply-voltage rejection
ratio (ΔVCC±/ΔVIO
)
Supply current
(each amplifier)
ICC
VO = 0; no load
AVD = 100
TA = 25°C
TA = 25°C
1.4
2.5
mA
dB
VO1 / VO2
Crosstalk attenuation
120
(1) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 6-40. Pulse techniques that maintain the junction temperature as close to the ambient temperature as possible must
be used.
(2) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range is
TA = –55°C to +125°C.
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6.24 Electrical Characteristics: TL074M
VCC± = ±15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS (1) (2)
MIN
TYP
MAX UNIT
TA = 25°C
3
9
VO = 0
RS = 50 Ω
VIO
αVIO
IIO
Input offset voltage
mV
15
TA = Full range
TA = Full range
Temperature coefficient of
input offset voltage
VO = 0, RS = 50 Ω
VO = 0
18
5
μV/°C
TA = 25°C
100
20
pA
nA
pA
nA
Input offset current
Input bias current
TA = Full range
TA = 25°C
65
200
20
IIB
VO = 0
TA = Full range
Common-mode input
voltage range
VICR
TA = 25°C
±11 –12 to 15
V
RL = 10 kΩ
RL ≥ 10 kΩ
RL ≥ 2 kΩ
TA = 25°C
±12
±12
±10
35
±13.5
Maximum peak output
voltage swing
VOM
V
TA = Full range
TA = 25°C
200
Large-signal differential
voltage amplification
VO = ±10 V
RL ≥ 2 kΩ
AVD
V/mV
TA = Full range
15
B1
ri
Unity-gain bandwidth
Input resistance
3
MHz
Ω
1012
VIC = VICR(min)
VO = 0
RS = 50 Ω
Common-mode rejection
ratio
CMRR
kSVR
TA = 25°C
TA = 25°C
80
80
86
86
dB
dB
VCC = ±9 V to ±15 V
VO = 0
RS = 50 Ω
Supply-voltage rejection
ratio (ΔVCC±/ΔVIO
)
Supply current
(each amplifier)
ICC
VO = 0; no load
AVD = 100
TA = 25°C
TA = 25°C
1.4
2.5
mA
dB
VO1 / VO2
Crosstalk attenuation
120
(1) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 6-40. Pulse techniques that maintain the junction temperature as close to the ambient temperature as possible must
be used .
(2) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range is
TA = –55°C to +125°C.
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6.25 Switching Characteristics: TL07xM
VCC± = ±15 V, TA = 25°C
PARAMETER
TEST CONDITIONS
RL = 2 kΩ
MIN
TYP
MAX UNIT
VI = 10 V
CL = 100 pF
SR
tr
Slew rate at unity gain
5
13
V/μs
μs
See Figure 7-1
0.1
20%
18
VI = 20 V
CL = 100 pF
RL = 2 kΩ
See Figure 7-1
Rise-time overshoot factor
f = 1 kHz
nV/√ Hz
μV
Vn
In
Equivalent input noise voltage RS = 20 Ω
f = 10 Hz to 10 kHz
f = 1 kHz
4
Equivalent input noise current RS = 20 Ω
VIrms = 6 V
0.01
pA/√ Hz
AVD = 1
RS ≤ 1 kΩ
THD
Total harmonic distortion
RL ≥ 2 kΩ
f = 1 kHz
0.003%
6.26 Switching Characteristics: TL07xC, TL07xAC, TL07xBC, TL07xI
VCC± = ±15 V, TA = 25°C
PARAMETER
TEST CONDITIONS
RL = 2 kΩ
MIN
TYP
MAX UNIT
VI = 10 V
CL = 100 pF
SR
tr
Slew rate at unity gain
8
13
V/μs
μs
See Figure 7-1
0.1
20%
18
VI = 20 V
CL = 100 pF
RL = 2 kΩ
See Figure 7-1
Rise-time overshoot factor
f = 1 kHz
nV/√ Hz
μV
Vn
In
Equivalent input noise voltage RS = 20 Ω
f = 10 Hz to 10 kHz
f = 1 kHz
4
Equivalent input noise current RS = 20 Ω
VIrms = 6 V
0.01
pA/√ Hz
AVD = 1
RS ≤ 1 kΩ
THD
Total harmonic distortion
RL ≥ 2 kΩ
f = 1 kHz
0.003%
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6.27 Electrical Characteristics, TL07xM
VCC± = ±15 V (unless otherwise noted)
TL071M, TL072M
MIN TYP MAX
TL074M
TYP
TEST CONDITIONS(1)
TA
UNIT
(2)
PARAMETER
MIN
MAX
25°C
3
6
9
3
9
VIO
αVIO
IIO
Input offset voltage VO = 0, RS = 50 Ω
mV
Full range
15
Temperature
coefficient of input
offset voltage
VO = 0, RS = 50 Ω
Full range
18
5
18
5
μV/°C
25°C
Full range
25°C
100
20
100
20
pA
nA
pA
nA
Input offset current VO = 0
65
200
50
65
200
20
IIB
Input bias current
VO = 0
Common-mode
input voltage range
VICR
25°C
25°C
±11 –12 to 15
±11 –12 to 15
V
RL = 10 kΩ
RL ≥ 10 kΩ
RL ≥ 2 kΩ
±12
±12
±10
35
±13.5
±12
±12
±10
35
±13.5
Maximum peak
output voltage
swing
VOM
V
Full range
25°C
Large-signal
200
200
AVD
differential voltage VO = ±10 V, RL ≥ 2 kΩ
amplification
V/mV
15
15
Unity-gain
bandwidth
B1
3
1012
86
3
1012
86
MHz
Ω
ri
Input resistance
Common-mode
rejection ratio
VIC = VICRmin,
VO = 0, RS = 50 Ω
CMRR
25°C
25°C
80
80
80
80
dB
Supply-voltage
rejection ratio (ΔV
VCC = ±9 V to ±15 V,
VO = 0, RS = 50 Ω
kSVR
86
86
dB
CC±/ΔVIO
)
Supply current
(each amplifier)
ICC
VO = 0, No load
AVD = 100
25°C
25°C
1.4
2.5
1.4
2.5
mA
dB
Crosstalk
attenuation
120
120
VO1/VO2
(1) Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as
shown in Figure 6-40. Pulse techniques must be used that will maintain the junction temperature as close to the ambient temperature
as possible.
(2) All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range is
TA = –55°C to 125°C.
6.28 Switching Characteristics
VCC± = ±15 V, TA= 25°C
TL07xC, TL07xAC,
TL07xM
TL07xBC, TL07xI TL075
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
VI = 10 V,
CL = 100 pF,
RL = 2 kΩ,
See Figure 7-1
SR
tr
Slew rate at unity gain
5
13
8
13
V/μs
μs
0.1
20%
18
0.1
20%
18
Rise-time overshoot
factor
VI = 20 V,
CL = 100 pF,
RL = 2 kΩ,
See Figure 7-1
f = 1 kHz
nV/√ Hz
μV
Equivalent input noise
voltage
Vn
In
RS = 20 Ω
RS = 20 Ω,
f = 10 Hz to 10 kHz
4
4
Equivalent input noise
current
f = 1 kHz
0.01
0.01
pA/√ Hz
VIrms = 6 V,
RL ≥ 2 kΩ,
f = 1 kHz,
Total harmonic
distortion
AVD = 1,
RS ≤ 1 kΩ,
THD
0.003%
0.003%
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6.29 Typical Characteristics: TL07xH
at TA = 25°C, VS = 40 V ( ±20 V), VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 20 pF (unless
otherwise noted)
TA = 25°C
Figure 6-1. Offset Voltage Production Distribution
Figure 6-2. Offset Voltage Drift Distribution
VCM = VS / 2
TA = 25°C
Figure 6-3. Offset Voltage vs Temperature
Figure 6-4. Offset Voltage vs Common-Mode
Voltage
TA = 125°C
TA = –40°C
Figure 6-5. Offset Voltage vs Common-Mode
Voltage
Figure 6-6. Offset Voltage vs Common-Mode
Voltage
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Figure 6-7. Offset Voltage vs Power Supply
Figure 6-8. Open-Loop Gain and Phase vs
Frequency
Figure 6-9. Closed-Loop Gain vs Frequency
Figure 6-10. Input Bias Current vs Common-Mode
Voltage
Figure 6-11. Input Bias Current vs Temperature
Figure 6-12. Output Voltage Swing vs Output
Current (Sourcing)
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Figure 6-14. CMRR and PSRR vs Frequency
Figure 6-13. Output Voltage Swing vs Output
Current (Sinking)
f = 0 Hz
f = 0 Hz
Figure 6-16. PSRR vs Temperature (dB)
Figure 6-15. CMRR vs Temperature (dB)
Figure 6-17. 0.1-Hz to 10-Hz Noise
Figure 6-18. Input Voltage Noise Spectral Density
vs Frequency
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BW = 80 kHz, VOUT = 1 VRMS
BW = 80 kHz, f = 1 kHz
Figure 6-19. THD+N Ratio vs Frequency
Figure 6-20. THD+N vs Output Amplitude
VCM = VS / 2
Figure 6-21. Quiescent Current vs Supply Voltage
Figure 6-22. Quiescent Current vs Temperature
Figure 6-23. Open-Loop Voltage Gain vs
Temperature (dB)
Figure 6-24. Open-Loop Output Impedance vs
Frequency
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G = –1, 25-mV output step
G = 1, 10-mV output step
Figure 6-25. Small-Signal Overshoot vs Capacitive Figure 6-26. Small-Signal Overshoot vs Capacitive
Load
Load
VS = ±10 V, VIN = VOUT
Figure 6-28. No Phase Reversal
Figure 6-27. Phase Margin vs Capacitive Load
G = –10
G = –10
Figure 6-29. Positive Overload Recovery
Figure 6-30. Negative Overload Recovery
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CL = 20 pF, G = 1, 10-mV step response
CL = 20 pF, G = 1, 10-mV step response
Figure 6-31. Small-Signal Step Response, Rising
Figure 6-32. Small-Signal Step Response, Falling
CL = 20 pF, G = 1
CL = 20 pF, G = 1
Figure 6-33. Large-Signal Step Response (Rising) Figure 6-34. Large-Signal Step Response (Falling)
CL = 20 pF, G = 1
Figure 6-35. Large-Signal Step Response
Figure 6-36. Short-Circuit Current vs Temperature
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Figure 6-38. Channel Separation vs Frequency
Figure 6-37. Maximum Output Voltage vs
Frequency
Figure 6-39. EMIRR (Electromagnetic Interference Rejection Ratio) vs Frequency
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6.30 Typical Characteristics: All Devices Except TL07xH
100
15
12.5
10
V
=
15 V
10 V
5 V
R
= 10 kΩ
CC
V
CC
= 15 V
L
T
= 25°C
See Figure 2
A
10
V
=
CC
7.5
5
1
V
=
CC
0.1
2.5
0
0.01
−75 −50 −25
0
25
50
75
100 125
100
1 k
10 k
100 k
1 M
10 M
T
A
− Free-Air Temperature − °C
f − Frequency − Hz
Figure 6-40. Input Bias Current vs Free-Air
Temperature
Figure 6-41. Maximum Peak Output Voltage vs
Frequency
15
R
= 2 kΩ
= 25°C
L
T
A
V
= 15 V
CC
12.5
10
7.5
5
See Figure 2
V
CC
= 10 V
V
CC
=
5 V
2.5
8
0
100
1 k
10 k
100 k
1 M
10 M
f − Frequency − Hz
Figure 6-42. Maximum Peak Output Voltage vs
Frequency
Figure 6-43. Maximum Peak Output Voltage vs
Frequency
15
15
R
L
= 10 kΩ
V
CC
=
15 V
T
= 25°C
See Figure 2
A
12.5
10
7.5
5
12.5
10
7.5
5
R
L
= 2 kΩ
2.5
0
2.5
0
V
= 15 V
8
CC
8
See Figure 2
−75 −50 −25
− Free-Air Temperature − °C
0
25
50
75 100 125
0.1
0.2
0.4 0.7
R − Load Resistance − kΩ
L
1
2
4
7 10
T
A
Figure 6-44. Maximum Peak Output Voltage vs
Free-Air Temperature
Figure 6-45. Maximum Peak Output Voltage vs
Load Resistance
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TL074B TL072M TL074M
TL071, TL071H, TL071A, TL071B
TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M
SLOS080P – SEPTEMBER 1978 – REVISED NOVEMBER 2020
www.ti.com
1000
15
12.5
10
R
T
A
= 10 kΩ
= 25°C
L
400
200
100
40
20
10
7.5
5
4
2
1
V
V
R
=
15 V
10 V
= 2 kΩ
CC
=
2.5
0
O
L
−75 −50 −25
0
25
50
75 100 125
0
2
4
6
8
10
12
14
16
T
A
− Free-Air Temperature − °C
|V
| − Supply Voltage − V
CC
Figure 6-47. Large-Signal Differential Voltage
Amplification vs Free-Air Temperature
Figure 6-46. Maximum Peak Output Voltage vs
Supply Voltage
1.3
1.2
1.1
1
1.03
1.02
Unity-Gain Bandwidth
1.01
1
Phase Shift
0.99
0.98
0.97
0.9
0.8
0.7
V
=
15 V
CC
R = 2 kΩ
f = B for Phase Shift
L
1
−75 −50 −25
0
25
50
75
100 125
T
A
− Free-Air Temperature − °C
Figure 6-49. Normalized Unity-Gain Bandwidth and
Phase Shift vs Free-Air Temperature
Figure 6-48. Large-Signal Differential Voltage
Amplification and Phase Shift vs Frequency
89
2
V
CC
=
15 V
T
A
= 25°C
1.8
1.6
1.4
1.2
1
R
= 10 kΩ
No Signal
No Load
L
88
87
86
85
84
83
0.8
0.6
0.4
0.2
0
−75 −50 −25
0
25
50
75
100 125
0
2
4
6
8
10
12
14
16
|V
| − Supply Voltage − V
T
A
− Free-Air Temperature − °C
CC
Figure 6-50. Common-Mode Rejection Ratio vs
Free-Air Temperature
Figure 6-51. Supply Current Per Amplifier vs
Supply Voltage
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2
1.8
1.6
1.4
1.2
1
250
V
= 15 V
V
= 15 V
CC
CC
225
200
175
150
125
100
75
No Signal
No Load
No Signal
No Load
TL074
0.8
0.6
0.4
0.2
0
TL072
TL071
50
25
0
−75 −50 −25
0
25
50
75 100 125
−75 −50 −25
0
25
50
75
100 125
T
A
− Free-Air Temperature −°C
T
A
− Free-Air Temperature − °C
Figure 6-53. Total Power Dissipation vs Free-Air
Temperature
Figure 6-52. Supply Current Per Amplifier vs Free-
Air Temperature
50
V
CC
=
15 V
A
VD
= 10
Ω
R
T
= 20
= 25°C
S
40
30
20
10
0
A
10
40 100
400 1 k
4 k 10 k 40 k 100 k
f − Frequency − Hz
Figure 6-55. Equivalent Input Noise Voltage vs
Frequency
Figure 6-54. Normalized Slew Rate vs Free-Air
Temperature
1
6
V
CC
= 15 V
V
CC
=
15 V
R
C
T
= 2 kΩ
= 100 pF
= 25°C
A
= 1
L
L
VD
0.4
V
I(RMS)
= 6 V
4
2
T
A
= 25°C
A
Output
0.1
0.04
0
0.01
−2
−4
−6
Input
0.004
0.001
100
400
1 k
4 k 10 k
40 k 100 k
0
0.5
1
1.5
2
2.5
3
3.5
f − Frequency − Hz
t − Time −
µ
s
Figure 6-56. Total Harmonic Distortion vs
Frequency
Figure 6-57. Voltage-Follower Large-Signal Pulse
Response
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10
VCCê = ê15 V
8
6
4
2
0
-2
-4
-6
-8
-10
-13 -11 -9 -7 -5 -3 -1
1
3
5
7
9
11 13 15 17
D003
VCM (V)
Figure 6-59. VIO vs VCM
Figure 6-58. Output Voltage vs Elapsed Time
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SLOS080P – SEPTEMBER 1978 – REVISED NOVEMBER 2020
7 Parameter Measurement Information
−
+
OUT
V
I
C
L
= 100 pF
R
= 2 kΩ
L
Figure 7-1. Unity-Gain Amplifier
10 kΩ
1 kΩ
−
V
I
OUT
= 100 pF
+
C
R
L
L
Figure 7-2. Gain-of-10 Inverting Amplifier
Figure 7-3. Input Offset-Voltage Null Circuit
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TL074B TL072M TL074M
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TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M
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8 Detailed Description
8.1 Overview
The TL07xH (TL071H, TL072H, and TL074H) family of devices are the next-generation versions of the industry-
standard TL07x (TL071, TL072, and TL074) devices. These devices provide outstanding value for cost-sensitive
applications, with features including low offset (1 mV, typ), high slew rate (25 V/μs, typ), and common-mode
input to the positive supply. High ESD (1.5 kV, HBM), integrated EMI and RF filters, and operation across the full
–40°C to 125°C enable the TL07xH devices to be used in the most rugged and demanding applications.
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized for
operation from −40°C to +85°C. The M-suffix devices are characterized for operation over the full military
temperature range of −55°C to +125°C.
8.2 Functional Block Diagram
V
CC+
IN+
IN−
64 Ω
128 Ω
64 Ω
OUT
C1
18 pF
1080 Ω
1080 Ω
V
CC−
OFFSET
N1
OFFSET
N2
TL071 Only
All component values shown are nominal.
†
COMPONENT COUNT
COMPONENT
TYPE
TL071
TL072
TL074
Resistors
11
14
2
22
28
4
44
56
6
Transistors
JFET
Diodes
Capacitors
epi-FET
1
2
4
1
2
4
1
2
4
†
Includes bias and trim circuitry
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TL074B TL072M TL074M
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SLOS080P – SEPTEMBER 1978 – REVISED NOVEMBER 2020
8.3 Feature Description
The TL07xH family of devices improve many specifications as compared to the industry-standard TL07x family.
Several comparisons of key specifications between these families are included below to show the advantages of
the TL07xH family.
8.3.1 Total Harmonic Distortion
Harmonic distortions to an audio signal are created by electronic components in a circuit. Total harmonic
distortion (THD) is a measure of harmonic distortions accumulated by a signal in an audio system. These
devices have a very low THD of 0.003% meaning that the TL07x device adds little harmonic distortion when
used in audio signal applications.
8.3.2 Slew Rate
The slew rate is the rate at which an operational amplifier can change the output when there is a change on the
input. These devices have a 13-V/μs slew rate.
8.4 Device Functional Modes
These devices are powered on when the supply is connected. These devices can be operated as a single-
supply operational amplifier or dual-supply amplifier depending on the application.
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TL074B TL072M TL074M
TL071, TL071H, TL071A, TL071B
TL072, TL072H, TL072A, TL072B, TL074, TL074H, TL074A, TL074B, TL072M, TL074M
SLOS080P – SEPTEMBER 1978 – REVISED NOVEMBER 2020
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
A typical application for an operational amplifier is an inverting amplifier. This amplifier takes a positive voltage
on the input, and makes the voltage a negative voltage. In the same manner, the amplifier makes negative
voltages positive.
9.2 Typical Application
RF
Vsup+
RI
VOUT
+
VIN
Vsup-
Figure 9-1. Inverting Amplifier
9.2.1 Design Requirements
The supply voltage must be selected so the supply voltage is larger than the input voltage range and output
range. For instance, this application scales a signal of ±0.5 V to ±1.8 V. Setting the supply at ±12 V is sufficient
to accommodate this application.
9.2.2 Detailed Design Procedure
1 M Ω
(
)
(
)
Vo = Vi + Vi o
*
1 +
(1)
1 k Ω
Determine the gain required by the inverting amplifier:
VOUT
A
V
=
VIN
1.8
(2)
(3)
A
V
=
= -3.6
-0.5
Once the desired gain is determined, select a value for RI or RF. Selecting a value in the kilohm range is
desirable because the amplifier circuit uses currents in the milliamp range. This ensures the part does not draw
too much current. This example uses 10 kΩ for RI which means 36 kΩ is used for RF. This is determined by
Equation 4.
RF
AV = -
RI
(4)
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SLOS080P – SEPTEMBER 1978 – REVISED NOVEMBER 2020
9.2.3 Application Curve
2
1.5
1
VIN
VOUT
0.5
0
-0.5
-1
-1.5
-2
0
0.5
1
Time (ms)
1.5
2
Figure 9-2. Input and Output Voltages of the Inverting Amplifier
9.3 Unity Gain Buffer
U1 TL072
œ
+
+
VIN
VOUT
10 k
+
12
Copyright © 2017, Texas Instruments Incorporated
Figure 9-3. Single-Supply Unity Gain Amplifier
9.3.1 Design Requirements
•
•
VCC must be within valid range per Section 6.6. This example uses a value of 12 V for VCC.
Input voltage must be within the recommended common-mode range, as shown in Section 6.6. The valid
common-mode range is 4 V to 12 V (VCC– + 4 V to VCC+).
•
Output is limited by output range, which is typically 1.5 V to 10.5 V, or VCC– + 1.5 V to VCC+ – 1.5 V.
9.3.2 Detailed Design Procedure
•
•
Avoid input voltage values below 1 V to prevent phase reversal where output goes high.
Avoid input values below 4 V to prevent degraded VIO that results in an apparent gain greater than 1. This
may cause instability in some second-order filter designs.
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9.3.3 Application Curves
12
10
8
1.5
1
0.5
0
6
-0.5
-1
4
2
-1.5
0
0
2
4
6
VIN (V)
8
10
12
0
2
4
6
VIN (V)
8
10
12
D002
D001
Figure 9-5. Gain vs Input Voltage
Figure 9-4. Output Voltage vs Input Voltage
9.4 System Examples
V
CC+
–
R1
R2
Input
+
Output
V
C3
CC–
R1= R2 = 2R3 = 1.5 MW
R3
C3
C1
C1
C1= C2 =
= 110 pF
= 1kHz
2
1
fo =
2p R1C1
Figure 9-7. High-Q Notch Filter
Figure 9-6. 0.5-Hz Square-Wave Oscillator
Figure 9-8. 100-kHz Quadrature Oscillator
Figure 9-9. AC Amplifier
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SLOS080P – SEPTEMBER 1978 – REVISED NOVEMBER 2020
10 Power Supply Recommendations
CAUTION
Supply voltages larger than 36 V for a single-supply or outside the range of ±18 V for a dual-supply
can permanently damage the device (see Section 6.2).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see Section 11.
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the
operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance
power sources local to the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from VCC+ to ground is applicable for single-
supply applications.
•
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Take care to physically separate digital
and analog grounds, paying attention to the flow of the ground current.
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it
is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed
to in parallel with the noisy trace.
•
•
•
Place the external components as close to the device as possible. Keeping RF and RG close to the inverting
input minimizes parasitic capacitance, as shown in Section 11.2 .
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
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SLOS080P – SEPTEMBER 1978 – REVISED NOVEMBER 2020
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11.2 Layout Example
Place components close to
device and to each other to
reduce parasitic errors
Run the input traces as far
away from the supply lines
as possible
RF
VS+
NC
IN1Þ
IN1+
VCCÞ
NC
VCC+
OUT
NC
Use low-ESR, ceramic
bypass capacitor
RG
GND
VIN
RIN
GND
Only needed for
dual-supply
operation
GND
VS-
(or GND for single supply)
VOUT
Ground (GND) plane on another layer
Figure 11-1. Operational Amplifier Board Layout for Noninverting Configuration
RIN
VIN
+
VOUT
RG
RF
Figure 11-2. Operational Amplifier Schematic for Noninverting Configuration
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SLOS080P – SEPTEMBER 1978 – REVISED NOVEMBER 2020
12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 12-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
TL071
TL071A
TL071B
TL072
Click here
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TL072A
TL072B
TL072M
TL074
TL074A
TL074B
TL074M
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Nov-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
81023052A
8102305HA
ACTIVE
LCCC
CFP
FK
U
20
10
8
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
POST-PLATE
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
81023052A
TL072MFKB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
1
SNPB
SNPB
8102305HA
TL072M
8102305PA
CDIP
LCCC
CDIP
CFP
JG
FK
J
1
8102305PA
TL072M
81023062A
20
14
14
8
1
POST-PLATE
SNPB
81023062A
TL074MFKB
8102306CA
1
8102306CA
TL074MJB
8102306DA
W
1
SNPB
8102306DA
TL074MWB
JM38510/11905BPA
M38510/11905BPA
CDIP
CDIP
JG
JG
1
SNPB
JM38510
/11905BPA
8
1
SNPB
JM38510
/11905BPA
PTL074HIDR
PTL074HIPWR
TL071ACD
ACTIVE
ACTIVE
ACTIVE
SOIC
TSSOP
SOIC
D
PW
D
14
14
8
2500
2000
75
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
0 to 70
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
071AC
TL071ACDG4
TL071ACDR
TL071ACP
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
PDIP
SOIC
SOIC
PDIP
D
D
P
D
D
P
8
8
8
8
8
8
75
2500
50
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
071AC
Green (RoHS
& no Sb/Br)
071AC
Green (RoHS
& no Sb/Br)
TL071ACP
071BC
TL071BCD
TL071BCDR
TL071BCP
75
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
2500
50
Green (RoHS
& no Sb/Br)
071BC
Green (RoHS
& no Sb/Br)
TL071BCP
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Nov-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TL071CD
TL071CDR
TL071CDRE4
TL071CDRG4
TL071CP
ACTIVE
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SO
D
D
D
D
P
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
75
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
-40 to 85
-40 to 85
-40 to 85
-40 to 85
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
TL071C
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
2500
2500
2500
50
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
TL071C
TL071C
TL071C
TL071CP
TL071CP
T071
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TL071CPE4
TL071CPSR
TL071ID
P
50
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
PS
D
D
D
P
2000
75
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
SOIC
SOIC
SOIC
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
Green (RoHS
& no Sb/Br)
TL071I
TL071I
TL071I
TL071IP
072AC
TL071IDR
2500
2500
50
Green (RoHS
& no Sb/Br)
TL071IDRG4
TL071IP
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TL072ACD
TL072ACDE4
TL072ACDR
TL072ACDRE4
TL072ACDRG4
TL072ACP
D
D
D
D
D
P
75
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
75
Green (RoHS
& no Sb/Br)
072AC
2500
2500
2500
50
Green (RoHS
& no Sb/Br)
072AC
Green (RoHS
& no Sb/Br)
072AC
Green (RoHS
& no Sb/Br)
072AC
Pb-Free
(RoHS)
TL072ACP
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
10-Nov-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TL072ACPE4
TL072BCD
ACTIVE
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SO
P
D
D
D
D
D
P
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
50
Pb-Free
(RoHS)
NIPDAU
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
TL072ACP
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
75
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
072BC
TL072BCDE4
TL072BCDG4
TL072BCDR
TL072BCDRG4
TL072BCP
75
Green (RoHS
& no Sb/Br)
072BC
75
Green (RoHS
& no Sb/Br)
072BC
2500
2500
50
Green (RoHS
& no Sb/Br)
072BC
Green (RoHS
& no Sb/Br)
072BC
Pb-Free
(RoHS)
TL072BCP
TL072BCP
TL072C
TL072C
TL072C
TL072C
TL072C
TL072C
TL072CP
TL072CP
T072
TL072BCPE4
TL072CD
P
50
Pb-Free
(RoHS)
N / A for Pkg Type
D
D
D
D
D
D
P
75
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
TL072CDE4
TL072CDG4
TL072CDR
75
Green (RoHS
& no Sb/Br)
75
Green (RoHS
& no Sb/Br)
2500
2500
2500
50
Green (RoHS
& no Sb/Br)
TL072CDRE4
TL072CDRG4
TL072CP
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TL072CPE4
TL072CPS
P
50
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
PS
80
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
10-Nov-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
PS
PS
PS
PW
PW
PW
D
Qty
2000
2000
2000
2000
2000
2000
75
(1)
(2)
(3)
(4/5)
(6)
TL072CPSR
TL072CPSRE4
TL072CPSRG4
TL072CPWR
TL072CPWRE4
TL072CPWRG4
TL072ID
ACTIVE
SO
SO
8
8
8
8
8
8
8
8
8
8
8
8
8
8
20
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
0 to 70
0 to 70
T072
T072
T072
T072
T072
T072
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
POST-PLATE
SO
Green (RoHS
& no Sb/Br)
0 to 70
TSSOP
TSSOP
TSSOP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
LCCC
Green (RoHS
& no Sb/Br)
0 to 70
Green (RoHS
& no Sb/Br)
0 to 70
Green (RoHS
& no Sb/Br)
0 to 70
Green (RoHS
& no Sb/Br)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-55 to 125
TL072I
TL072I
TL072I
TL072I
TL072I
TL072I
TL072IP
TL072IP
TL072IDE4
D
75
Green (RoHS
& no Sb/Br)
TL072IDG4
TL072IDR
D
75
Green (RoHS
& no Sb/Br)
D
2500
2500
2500
50
Green (RoHS
& no Sb/Br)
TL072IDRE4
TL072IDRG4
TL072IP
D
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
P
Pb-Free
(RoHS)
TL072IPE4
P
50
Pb-Free
(RoHS)
N / A for Pkg Type
TL072MFKB
FK
1
TBD
N / A for Pkg Type
81023052A
TL072MFKB
TL072MJG
ACTIVE
ACTIVE
CDIP
CDIP
JG
JG
8
8
1
1
TBD
TBD
SNPB
SNPB
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
TL072MJG
TL072MJGB
8102305PA
TL072M
TL072MUB
ACTIVE
CFP
U
10
1
TBD
SNPB
N / A for Pkg Type
-55 to 125
8102305HA
TL072M
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com
10-Nov-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TL074ACD
TL074ACDE4
TL074ACDR
TL074ACDRE4
TL074ACDRG4
TL074ACN
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SO
D
D
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
50
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
TL074AC
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
50
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
TL074AC
TL074AC
TL074AC
TL074AC
TL074ACN
TL074ACN
TL074A
D
2500
2500
2500
25
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
N
Green (RoHS
& no Sb/Br)
TL074ACNE4
TL074ACNSR
TL074BCD
N
25
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
NS
D
2000
50
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SSOP
Green (RoHS
& no Sb/Br)
TL074BC
TL074BC
TL074BC
TL074BC
TL074BC
TL074BCN
TL074BCN
TL074C
TL074BCDE4
TL074BCDR
TL074BCDRE4
TL074BCDRG4
TL074BCN
D
50
Green (RoHS
& no Sb/Br)
D
2500
2500
2500
25
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
N
Green (RoHS
& no Sb/Br)
TL074BCNE4
TL074CD
N
25
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
D
50
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
TL074CDBR
DB
2000
Green (RoHS
& no Sb/Br)
T074
Addendum-Page 5
PACKAGE OPTION ADDENDUM
www.ti.com
10-Nov-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TL074CDG4
TL074CDR
ACTIVE
SOIC
SOIC
SOIC
PDIP
D
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
50
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
0 to 70
0 to 70
TL074C
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PREVIEW
PREVIEW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
2500
2500
25
Green (RoHS
& no Sb/Br)
NIPDAU | SN
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
TL074C
TL074C
TL074CN
TL074CN
TL074
TL074CDRG4
TL074CN
D
Green (RoHS
& no Sb/Br)
0 to 70
N
Green (RoHS
& no Sb/Br)
0 to 70
TL074CNE4
TL074CNSR
TL074CNSRG4
TL074CPW
TL074CPWR
TL074CPWRE4
TL074CPWRG4
TL074HIDR
TL074HIPWR
TL074ID
PDIP
N
25
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
0 to 70
SO
NS
NS
PW
PW
PW
PW
D
2000
2000
90
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
0 to 70
SO
Green (RoHS
& no Sb/Br)
0 to 70
TL074
TSSOP
TSSOP
TSSOP
TSSOP
SOIC
TSSOP
SOIC
SOIC
SOIC
SOIC
Green (RoHS
& no Sb/Br)
0 to 70
T074
2000
2000
2000
2500
2000
50
Green (RoHS
& no Sb/Br)
0 to 70
T074
Green (RoHS
& no Sb/Br)
0 to 70
T074
Green (RoHS
& no Sb/Br)
0 to 70
T074
Green (RoHS
& no Sb/Br)
-40 to 125
-40 to 125
-40 to 85
-40 to 85
-40 to 85
-40 to 85
TL074HID
TL074PW
TL074I
TL074I
TL074I
TL074I
PW
D
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TL074IDE4
D
50
Green (RoHS
& no Sb/Br)
TL074IDG4
TL074IDR
D
50
Green (RoHS
& no Sb/Br)
D
2500
Green (RoHS
& no Sb/Br)
Addendum-Page 6
PACKAGE OPTION ADDENDUM
www.ti.com
10-Nov-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
2500
2500
25
(1)
(2)
(3)
(4/5)
(6)
TL074IDRE4
TL074IDRG4
TL074IN
ACTIVE
SOIC
SOIC
PDIP
D
D
N
14
14
14
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
-40 to 85
-40 to 85
-40 to 85
TL074I
ACTIVE
ACTIVE
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
TL074I
Green (RoHS
& no Sb/Br)
TL074IN
TL074MFK
TL074MFK
ACTIVE
ACTIVE
LCCC
LCCC
FK
FK
20
20
1
1
TBD
POST-PLATE
POST-PLATE
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
TL074MFKB
TBD
81023062A
TL074MFKB
TL074MJ
ACTIVE
ACTIVE
CDIP
CDIP
J
J
14
14
1
1
TBD
TBD
SNPB
SNPB
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
TL074MJ
TL074MJB
8102306CA
TL074MJB
TL074MWB
ACTIVE
CFP
W
14
1
TBD
SNPB
N / A for Pkg Type
-55 to 125
8102306DA
TL074MWB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 7
PACKAGE OPTION ADDENDUM
www.ti.com
10-Nov-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TL072, TL072M, TL074, TL074M :
Catalog: TL072, TL074
•
Enhanced Product: TL072-EP, TL072-EP, TL074-EP, TL074-EP
•
Military: TL072M, TL074M
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 8
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Nov-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TL071ACDR
TL071BCDR
TL071CDR
TL071CDR
TL071IDR
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
TSSOP
SOIC
SOIC
SOIC
SO
D
D
8
8
2500
2500
2500
2500
2500
2500
2500
2500
2500
2000
2500
2500
2500
2000
2500
2500
2500
2000
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
16.4
16.4
16.4
16.4
16.4
12.4
6.4
6.4
6.4
6.4
6.4
6.4
6.4
6.4
6.4
7.0
6.4
6.4
6.5
8.2
6.5
6.5
6.5
6.9
5.2
5.2
5.2
5.2
5.2
5.2
5.2
5.2
5.2
3.6
5.2
5.2
9.0
10.5
9.0
9.0
9.0
5.6
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
2.1
1.6
2.1
2.1
2.1
2.5
2.1
2.1
2.1
1.6
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
D
8
D
8
D
8
TL072ACDR
TL072BCDR
TL072CDR
TL072CDR
TL072CPWR
TL072IDR
D
8
D
8
D
8
D
8
PW
D
8
8
TL072IDR
D
8
TL074ACDR
TL074ACNSR
TL074BCDR
TL074CDR
TL074CDRG4
TL074CPWR
D
14
14
14
14
14
14
NS
D
SOIC
SOIC
SOIC
TSSOP
D
D
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Nov-2020
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TL074IDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TL071ACDR
TL071BCDR
TL071CDR
TL071CDR
TL071IDR
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
TSSOP
SOIC
SOIC
SOIC
SO
D
D
8
8
2500
2500
2500
2500
2500
2500
2500
2500
2500
2000
2500
2500
2500
2000
2500
2500
340.5
340.5
853.0
340.5
340.5
340.5
340.5
853.0
340.5
853.0
340.5
853.0
333.2
367.0
333.2
333.2
338.1
338.1
449.0
338.1
338.1
338.1
338.1
449.0
338.1
449.0
338.1
449.0
345.9
367.0
345.9
345.9
20.6
20.6
35.0
20.6
20.6
20.6
20.6
35.0
20.6
35.0
20.6
35.0
28.6
38.0
28.6
28.6
D
8
D
8
D
8
TL072ACDR
TL072BCDR
TL072CDR
TL072CDR
TL072CPWR
TL072IDR
D
8
D
8
D
8
D
8
PW
D
8
8
TL072IDR
D
8
TL074ACDR
TL074ACNSR
TL074BCDR
TL074CDR
D
14
14
14
14
NS
D
SOIC
SOIC
D
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Nov-2020
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TL074CDRG4
TL074CPWR
TL074IDR
SOIC
TSSOP
SOIC
D
PW
D
14
14
14
2500
2000
2500
333.2
853.0
333.2
345.9
449.0
345.9
28.6
35.0
28.6
Pack Materials-Page 3
PACKAGE OUTLINE
U0010A
CFP - 2.03 mm max height
S
C
A
L
E
1
.
4
0
0
CERAMIC FLATPACK
.27 MAX
GLASS
.005 MIN
TYP
.010 .002
1
PIN 1 ID
.045 MAX
TYP
10
8X .050 .005
.27 MAX
GLASS
5
6
10X .017 .002
+.019
.241
5X .32 .01
5X .32 .01
-.003
.005 .001
+.013
.067
-.012
.045
.026
4225582/A 01/2020
NOTES:
1. All linear dimensions are in inches. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
PACKAGE OUTLINE
J0014A
CDIP - 5.08 mm max height
S
C
A
L
E
0
.
9
0
0
CERAMIC DUAL IN LINE PACKAGE
4X .005 MIN
[0.13]
PIN 1 ID
(OPTIONAL)
A
.015-.060 TYP
[0.38-1.52]
1
14
12X .100
[2.54]
14X .014-.026
[0.36-0.66]
14X .045-.065
[1.15-1.65]
.010 [0.25] C A B
.754-.785
[19.15-19.94]
8
7
B
.245-.283
[6.22-7.19]
.2 MAX TYP
[5.08]
.13 MIN TYP
[3.3]
SEATING PLANE
C
.308-.314
[7.83-7.97]
AT GAGE PLANE
.015 GAGE PLANE
[0.38]
0 -15
TYP
14X .008-.014
[0.2-0.36]
4214771/A 05/2017
NOTES:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.
www.ti.com
EXAMPLE BOARD LAYOUT
J0014A
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE
(.300 ) TYP
[7.62]
SEE DETAIL B
14
SEE DETAIL A
1
12X (.100 )
[2.54]
SYMM
14X ( .039)
[1]
8
7
SYMM
LAND PATTERN EXAMPLE
NON-SOLDER MASK DEFINED
SCALE: 5X
.002 MAX
[0.05]
ALL AROUND
(.063)
[1.6]
METAL
(
.063)
[1.6]
SOLDER MASK
OPENING
METAL
.002 MAX
[0.05]
ALL AROUND
SOLDER MASK
OPENING
(R.002 ) TYP
[0.05]
DETAIL A
DETAIL B
SCALE: 15X
13X, SCALE: 15X
4214771/A 05/2017
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.063 (1,60)
0.015 (0,38)
0.020 (0,51) MIN
0.200 (5,08) MAX
0.130 (3,30) MIN
Seating Plane
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
8
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
SEATING PLANE
TYP
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
5
1
3.1
2.9
NOTE 3
2X
1.95
4
0.30
0.19
8X
4.5
4.3
1.2 MAX
B
0.1
C A
B
NOTE 4
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
0 - 8
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
8X (0.45)
(R0.05)
1
4
TYP
8
SYMM
6X (0.65)
5
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
(R0.05) TYP
8X (0.45)
1
4
8
SYMM
6X (0.65)
5
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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