TIOS1015DMWR [TI]
具有集成浪涌保护功能和 5V LDO 输出的数字传感器输出驱动器 | DMW | 10 | -40 to 125;
| 型号： | TIOS1015DMWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成浪涌保护功能和 5V LDO 输出的数字传感器输出驱动器 | DMW | 10 | -40 to 125 驱动 传感器 驱动器 |
| 文件： | 总31页 (文件大小：2086K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TIOS101, TIOS1013, TIOS1015
ZHCSGF5C – JULY 2017 – REVISED FEBRUARY 2021
具有集成浪涌保护功能的 TIOS101、TIOS101x 数字传感器输出驱动器
1 特性
2 应用
•
提供功能安全
•
•
•
接近开关
电容式和电感式传感器
数字输出
– 可帮助进行功能安全系统设计的文档：
TIOS101、TIOS1013、TIOS1015
• 7V 至 36V 电源电压
• PNP、NPN 或推挽可配置输出
3 说明
TIOS101(x) 器件可配置为高侧、低侧或推挽驱动器。
•
在 250mA 条件下，残余电压低，为 1.75V
• 50mA 至 350mA 可配置电流限制
耐受 ±65V 瞬态电压（时间低于 100µs）
这 些 器 件 能 够 承 受 高 达 1.2kV (500Ω)
61000-4-5 浪涌，并具有集成反向极性保护。
的
IEC
•
• VCC、OUT 和 GND 上高达 60V 的反极性保护
• VCC 和 OUT 上有集成式 EMC 保护
– ±16kV IEC 61000-4-2 ESD 接触放电
– ±4kV IEC 61000-4-4 电气快速瞬变
– ±1.2kV/500Ω IEC 61000-4-5 浪涌
只需通过一个简单的引脚可编程接口，便可轻松连接到
控制器电路。输出电流限制可使用外部电阻器进行配
置。
此外，它们提供了故障报告和内部保护功能，可应对欠
压、过流和过热条件。
•
高达 1.5H 电感负载的
器件信息
封装(1)
快速消磁功能
大电容负载驱动能力
封装尺寸（标称值）
器件型号
TIOS101
•
• < 2.2mA 静态电源电流
TIOS1013
TIOS1015
VSON (10)
2.50mm x 3.00mm
•
集成式 LDO 选项可支持高达 20mA 的电流
– TIOS101：无 LDO
– TIOS1013：3.3V LDO
– TIOS1015：5V LDO
过热警告和热保护
故障指示灯
工作环境温度：-40°C 至 125°C
(1) 如需了解所有可订购器件，请参阅数据表末尾的可订购产品附
录。
•
•
•
• 2.5mm x 3mm 10 引脚 VSON 封装
TIOS101(x)
VCC
VCC_OUT
VOLTAGE
REGULATOR
0.1 µF
100 V
1 µF
10 V
10 kΩ
IN
OUT
Sensor
Front-End
EN
DIAGNOSTICS
and
CONTROL
NFAULT
CUR_OK
TMP_OK
PWR_OK
GND
ILIM_ADJ
RSET
典型应用图
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSEV6
TIOS101, TIOS1013, TIOS1015
ZHCSGF5C – JULY 2017 – REVISED FEBRUARY 2021
www.ti.com.cn
Table of Contents
8.2 Functional Block Diagrams......................................... 9
8.3 Feature Description...................................................10
8.4 Device Functional Modes..........................................15
9 Application Information Disclaimer.............................17
9.1 Application Information............................................. 17
9.2 Typical Application.................................................... 17
10 Power Supply Recommendations..............................21
11 Layout...........................................................................22
11.1 Layout Guidelines................................................... 22
11.2 Layout Example...................................................... 22
12 Device and Documentation Support..........................23
12.1 接收文档更新通知................................................... 23
12.2 支持资源..................................................................23
12.3 Trademarks.............................................................23
12.4 静电放电警告.......................................................... 23
12.5 术语表..................................................................... 23
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics............................................6
6.7 Typical Characteristics................................................7
7 Parameter Measurement Information............................8
8 Detailed Description........................................................9
8.1 Overview.....................................................................9
4 Revision History
Changes from Revision B (June 2019) to Revision C (February 2021)
Page
•
向特性 列表添加了“功能安全”........................................................................................................................ 1
Changes from Revision A (August 2018) to Revision B (June 2019)
Page
•
•
•
向数据表添加了器件编号 TIOS1013 和 TIOS1015.............................................................................................1
将所有 TIOS101-3 更改为 TIOS1013 并将 TIOS101-5 更改为 TIOS1015......................................................... 1
将特性 从“VCC 上高达 55V 的反极性保护”更改为“VCC 上高达 60V 的反极性保护”................................ 1
• Changed the Supply voltage values From: MIN = –55 V, MAX = 50 V To: MIN = –60 V, MAX = 60 V in the
Absolute Maximum Ratings ...............................................................................................................................4
• Changed the Voltage difference Max value From: 55 V To: 60 V in the Absolute Maximum Ratings ............... 4
• Changed |55 V| To: |60 V| in the Leakage current Test Conditions in the Electrical Characteristics.................. 5
• Changed text From: "not exceed 55 V DC at any time." To: "not exceed 60 V DC at any time." in the Reverse
Polarity Protection section................................................................................................................................ 13
Changes from Revision * (July 2017) to Revision A (August 2018)
Page
• Changed the Thermal Information table values..................................................................................................5
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5 Pin Configuration and Functions
VCC_IN/OUT
1
2
3
4
5
10
9
NC
NFAULT
NC
VCC
Thermal
Pad
8
OUT
IN
7
GND
EN
6
ILIM_ADJ
Not to scale
图 5-1. DMW Package, 10-Pin (VSON), Top View
表 5-1. Pin Functions
DESCRIPTION
PIN
I/O
NAME
OUT
NO.
8
O
Switch output
VCC
9
POWER
POWER
Supply voltage (24 V nominal)
Device ground
GND
7
Driver enable input signal from the local controller. Logic low sets the OUT output at Hi-Z. Weak internal pull-
down.
EN
IN
5
4
I
I
Transmit data input from the local controller. No effect if EN is low. Logic high sets low-side switch. Logic low
sets high-side switch. Weak internal pull-up.
VCC_IN/OUT
ILIM_ADJ
1
6
POWER
I
3.3-V or 5-V linear regulator output; external 3.3-V or 5-V logic supply input for option without LDO.
Input for current limit adjustment. Connect resistor RSET between ILIM_ADJ and GND.
Fault indicator output signal to the microcontroller. A low level indicates either an over- current, an
undervoltage in supply or an overtemperature condition. Connect this pin via pull-up resistor to VCC_IN/OUT.
NFAULT
2
OPEN-DRAIN
NC
3, 10
No internal connection.
—
—
Thermal Pad
Connect to GND plane for optimal thermal and electrical performance
—
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
–60
–65
MAX
60
65
60
6
UNIT
V
Steady state voltage for VCC and OUT
Supply voltage
Transient pulse width < 100 µs for VCC and OUT
V
Voltage difference
V
|V(VCC) – V(OUT)
|
Logic supply voltage (TIOS101)
Input logic voltage
VCC_IN
V
–0.3
–0.3
–5
IN, EN, ILIM_ADJ
NFAULT
6
V
Output current
5
mA
°C
Storage temperature, Tstg
-55
170
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltages are with reference to the GND pin, unless otherwise specified.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
All pins
±4000
Contact discharge, per IEC 61000-4-2(2) (3)
Electrical fast transient, per IEC 61000-4-4(2)
±16000
±4000
V(ESD)
Electrostatic discharge
V
Pins VCC, OUT
and GND
Surge protection with 500 Ω, per IEC 61000-4-5;
1.2/50 μs (2)
±1200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) Minimum 100-nF capacitor is required between VCC and GND. Minimum 1-µF capacitor is required between VCC_IN/OUT and GND.
(3) Passing level is ±4500 V if the device is powered and EN=IN=HIGH.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
7
NOM
24
MAX
36
UNIT
V
V(VCC)
Supply voltage
3.3 V configuration
5 V configuration
3
3.3
5
3.6
V
V(VCC_IN)
Logic level input voltage (TIOS101 only)
4.5
0
5.5
V
RSET
1/tBIT
I(VCC_OUT)
TA
External resistor for OUT current limit
Signaling rate (push-pull mode)
100
250
20
kΩ
kbps
mA
°C
LDO output current (TIOS1013 and TIOS1015 only)
Operating ambient temperature
125
150
–40
TJ
Junction temperature
°C
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6.4 Thermal Information
TIOS101(x)
UNIT
DMW (10 Pins)
THERMAL METRIC(1)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
68.1
60.1
40.6
13.4
40.7
25.2
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJT
ψJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (VCC)
EN = LOW, no load
EN = HIGH, no load
1.5
2
2.2
2.7
mA
mA
I(VCC)
Quiescent supply current
LOGIC-LEVEL INPUTS (EN, IN)
VIL
Input logic low voltage
Input logic high voltage
Pull-down (EN) resistance
Pull-up (IN) resistance
0.8
V
V
VIH
2
RPD
RPU
100
200
kΩ
kΩ
CONTROL OUTPUT (NFAULT)
VOL
IOZ
Output logic low voltage
IO = 4 mA
0.5
1
V
Output high impedance leakage
Output in Hi-Z, VO = 0 V or VCC_IN/OUT
µA
–1
DRIVER OUTPUT (OUT)
I = 250 mA
1.75
1.5
1.1
1.75
1.5
1.1
80
V
V
High-side driver residual voltage
I = 200 mA
I = 100 mA
V
VDS(ON)
I = 250 mA
V
Low-side driver residual voltage
OUT pull-up/down current
Driver output current limit
I = 200 mA
V
I = 100 mA
V
EN = LOW, IN = LOW, pull-down current
EN = LOW, IN = HIGH, pull-up current
RSET = 100 kΩ
40
40
50
50
µA
µA
mA
mA
mA
IP
80
35
50
70
IO(LIM)
300
300
350
350
400
400
RSET = 0 kΩ
RSET = OPEN(1)
PROTECTION CIRCUITS
VCC falling; NFAULT = Hi-Z
VCC rising; NFAULT = LOW
6
V
V
V(UVLO)
VCC under voltage lockout
6.5
V(UVLO,HYS
VCC under voltage hysteresis
Rising to falling threshold
100
mV
)
VCC_IN falling; NFAULT = Hi-Z
VCC_IN rising; NFAULT = LOW
2.4
2.5
V
V
VCC_IN under voltage lockout (No
LDO option)
V(UVLO_IN)
V(UVLO,HYS VCC_IN under voltage hysteresis
Rising to falling threshold
100
mV
(No LDO option)
)
T(WRN)
T(SDN)
T(HYS)
Thermal warning
125
150
°C
°C
°C
Thermal shutdown
Die temperature TJ
160
10
Thermal hysteresis for shutdown
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6.5 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V(OUT) < V(VCC) or
V(OUT) > V(VCC)
up to |36 V|
50
µA
V(OUT) < V(OUT) or
V(OUT) > V(VCC)
up to |60 V|
IREV
Leakage current in reverse polarity
80
µA
EN = HIGH, IN = LOW; V(OUT to VCC) = 3 V
EN = HIGH, IN = HIGH; V(OUT to GND) = -3 V
550
10
µA
µA
LINEAR REGULATOR (LDO)
TIOS1015
TIOS1013
4.75
3.13
5
5.25
3.46
1.9
V
V
V
V
V(VCC_OUT) Voltage regulator output
3.3
TIOS1015
TIOS1013
Voltage regulator drop-out voltage
(V(VCC) – V(VCC_OUT)
V(DROP)
REG
ICC = 20 mA load current
I(VCC_OUT) = 1 mA
)
2.3
Line regulation (dV(VCC_OUT)
dV(VCC)
/
1.7
1%
mV/V
Load regulation (dV(VCC_OUT)
/
LREG
V(VCC) = 24 V, I(VCC_OUT) = 100 µA to 20 mA
100 kHz, I(VCC_OUT) = 20 mA
V(VCC_OUT)
)
PSSR
Power Supply Rejection Ratio
40
dB
(1) Current fault indication will be active. Current fault auto recovery will be de-activated.
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH, tPHL
tP(skew)
Driver propagation delay
600
800
ns
ns
Driver propagation delay skew. |tPLH
-
See 图 7-1
100
tPHL
|
See 图 7-2
See 图 7-3
RL = 2 kΩ
CL = 5 nF
tPZH, tPZL
tPHZ, tPLZ
tr, tf
Driver enable delay
4
4
µs
µs
ns
ns
µs
µs
ms
Driver disable delay
R(SET) = 0 Ω
Driver output rise, fall time
Difference in rise and fall time
Current fault blanking time
Current fault indication delay
150
50
|tr – tf|
tSC
175
10
200
tpSC
260
50
tSCEN
Current fault driver re-enable wait time
OUT re-enable delay after UVLO (1)
15
30
V(UVLO) rising threshold crossing
time to OUT enable time
t(UVLO)
ms
(1) OUT output remains Hi-Z for this time
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6.7 Typical Characteristics
3
2.5
2
1.8
1.6
1.4
1.2
1
1.5
1
0.8
0.6
0.4
0.2
0
-40èC
25èC
125èC
0.5
0
EN = High
EN = Low
0
5
10
15
Supply Voltage (V)
20
25
30
35
40
0
50
100 150
Load Current (mA)
200
250
D001
D002
图 6-2. Residual Voltage vs Load Current: High Side
No load
IN = OPEN
25°C
图 6-1. Supply Current vs Supply Voltage
1.6
1.4
1.2
1
400
Low Side
High Side
350
300
250
200
150
100
50
0.8
0.6
0.4
-40èC
0.2
25èC
125èC
0
0
0
50
100 150
Load Current (mA)
200
250
0
20
40
RSET (kW)
60
80
100
D003
D004
图 6-3. Residual Voltage vs Load Current: Low Side
图 6-4. Current Limit vs RSET
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7 Parameter Measurement Information
VCC
R
L
IN
OUT
R
C
L
L
EN
图 7-1. Test Circuit for Driver Switching
V
V
OH
OH
80%
80%
50%
IN
OUT
OUT
t
t
PHL
PHL
VOH
50%
20%
20%
OUT
V
V
OL
OL
VOL
t
r
t
f
图 7-2. Waveforms for Driver Output Switching Measurements
IN = Low
IN = High
50%
50%
EN
t
EN
t
t
PLZ
t
PLZ
PZH
PHZ
VVCC/2
VOH
80%
50%
50%
OUT
20%
OUT
VOL
VVCC/2
图 7-3. Waveforms for Driver Enable or Disable Time Measurements
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8 Detailed Description
8.1 Overview
图 8-1 shows that the device driver output (OUT) can be used in a push-pull, high-side, or low-side configuration
using the enable (EN) and transmit data (IN) input pins. OUT can drive resistive, large capacitive or large
inductive loads.
TIOS101 and TIOS101x devices have integrated IEC 61000-4-4/5 EFT and surge protection. In addition,
tolerance to ±65-V transients enables flexibility to choose from a wider range of TVS diodes if an application
requires higher levels of protection. These integrated robustness features will simplify the system-level design by
reducing the external protection circuitry.
These devices implement protection features for over-current, over-voltage and over-temperature conditions.
The devices also provide a current-limit setting of the driver output current using an external resistor.
The TIOS101x devices derive the low voltage supply from the typical 24 V industrial supply via an internal linear
regulator to provide power to the local controller and sensor circuitry.
8.2 Functional Block Diagrams
VCC
VCC_IN
IN
OUT
EN
Diagnostics
& Control
NFAULT
CUR_OK
TMP_OK
PWR_OK
GND
ILIM_ADJ
图 8-1. Block Diagram, TIOS101
Voltage
Regulator
VCC
VCC_OUT
IN
OUT
EN
Diagnostics
& Control
NFAULT
CUR_OK
TMP_OK
PWR_OK
GND
ILIM_ADJ
图 8-2. Block Diagram, TIOS101x
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8.3 Feature Description
8.3.1 Current Limit Configuration
The output current can be configured with an internal resistor on ILIM_ADJ pin. The maximum settable current
limit is 300 mA. This maximum setting specifies a minimum of 300 mA over temperature and voltage.
Output disable due to current fault and current fault auto recovery features can be disabled by floating ILIM_ADJ
pin. However, the current fault indication is still active in this configuration. This feature is useful when driving
large capacitances.
表 8-1. Current Limitation
Output Disable and Auto
ILIM_ADJ Pin Condition
OUT Current Limit
NFAULT Indication During Fault
Recovery
RSET resistor to GND
Connected to GND
OPEN
Variable
300 mA
300 mA
Yes
Yes
Yes
Yes
Yes
No
8.3.2 Current Fault Detection, Indication and Auto Recovery
If the output current at OUT exceeds the internally set current limit IO(LIM) for a duration longer than tSC, the
NFAULT pin is driven logic low to indicate a fault condition. The output is turned off, but the LDO continues to
function. The output periodically retries to check if the output is still in the over current condition. In this mode,
the output is switched on for tSC in tSCEN intervals. Current fault auto recovery mode can be disabled by setting
ILIM_ADJ = OPEN. See 表 8-3.Toggling EN will clear NFAULT.
8.3.3 Thermal Warning, Thermal Shutdown
If the die temperature exceeds T(WRN), the NFAULT flag is held low indicating a potential over temperature
problem. When the TJ exceeds T(SDN), The output is disabled but the LDO remains operational. As soon as the
temperature drops below the temperature threshold (and after T(HYS)), the internal circuit re-enables the driver,
subject to the state of the EN and IN pins.
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8.3.4 Fault Reporting (NFAULT)
NFAULT is driven low if either a current fault condition is detected, die temperature has exceeded T(WRN) or
supply has dropped below the UVLO threshold. NFAULT returns to high-impedance as soon as all three fault
conditions clear.
Normal
Operation
CUR_OK = Z
Driver = ON
LDO = ON
Output at Hi-Z
EN*
CUR_OK=Z
Driver = OFF
LDO = ON
N
R
W
T
>
T
E
N
N
*
E
N&
R
W
T
<
Thermal
Warning
CUR_OK = Z
Current
Fault
T
T >T
WRN
CUR_OK = L
Driver = OFF
LDO= ON
TMP_OK = L
Driver= EN/EN*
LDO= ON
Out at I
T < T
WRN
O(LIM) and
Current
Fault Recovery
Thermal
Shutdown
CUR_OK = Z
TMP_OK = L
CUR_OK = L
Driver = ON for t
sc
LDO= ON
Driver = OFF
LDO = ON
NFAULT = [CUR_OK && PWR_OK && TMP_OK]
图 8-3. Device State Diagram
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8.3.5 Device Function Tables
表 8-2. Driver Function
EN
IN
OUT
COMMENT
L / Open
X
L
Hi-Z
H
Device is in ready-to-receive state
H
H
OUT is sourcing current (high-side drive)
OUT is sinking current (low-side drive)
H / Open
L
表 8-3. Current Limit Indicator Function (t > tSC
)
EN
IN
OUT CURRENT
| I(OUT) | > IO(LIM)
| I(OUT) | < IO(LIM)
| I(OUT) | > IO(LIM)
| I(OUT) | < IO(LIM)
X
NFAULT
COMMENT
L
Z
L
Z
Z
OUT current exceeds the set limit for over tSC
Normal operation
H
H / Open
OUT current exceeds the set limit for over tSC
Normal operation
H
L
L / Open
X
Driver is disabled, current limit indicator is inactive
8.3.6 The Integrated Voltage Regulator (LDO)
The TIOS1013 and TIOS1015 each have an integrated linear voltage regulator (LDO) which can supply power to
external components. The voltage regulator is specified for VCC voltages in the range of 7 V to 36 V with respect
to GND. The LDO is capable of delivering up to 20 mA. The LDO output is current limited to 35-mA to limit the
inrush current onto VCC_OUT decoupling capacitors during initial power up.
The LDO is designed to be stable with standard ceramic capacitors with values of 1 μF or larger at the output.
X5R- and X7R-type capacitors are best because they have minimal variation in value and ESR over
temperature. Maximum ESR should be less than 1 Ω. With tolerance and dc bias effects, the minimum
capacitance to ensure stability is 1 μF.
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8.3.7 Reverse Polarity Protection
Reverse polarity protection circuitry protects the devices against accidental reverse polarity connections to the
VCC, OUT and GND pins. The maximum voltage between any of the pins may not exceed 60 V DC at any time.
图 8-4 and 图 8-5 shows all the possible connection combinations.
VCC
OUT
GND
VCC
OUT
GND
DC
RL
DC
RL
TIOS101(x)
TIOS101(x)
Correct
Configuration
Reverse Polarity Protected
Fault Conditions
VCC
OUT
GND
VCC
OUT
GND
DC
DC
RL
TIOS101(x)
TIOS101(x)
RL
Reverse Polarity Protected
Fault Conditions
Reverse Polarity Protected
Fault Conditions
VCC
VCC
OUT
GND
DC
OUT
GND
DC
RL
TIOS101(x)
TIOS101(x)
RL
Reverse Polarity Protected
Fault Conditions
Reverse Polarity Protected
Fault Conditions
图 8-4. High-Side Driver Configuration
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VCC
OUT
GND
VCC
DC
DC
OUT
TIOS101(x)
TIOS101(x)
RL
RL
GND
Reverse Polarity Protected
Fault Conditions
Correct
Configuration
VCC
OUT
GND
VCC
DC
DC
OUT
TIOS101(x)
TIOS101(x)
RL
RL
GND
Reverse Polarity Protected
Fault Conditions
Reverse Polarity Protected
Fault Conditions
VCC
OUT
GND
VCC
OUT
DC
DC
TIOS101(x)
TIOS101(x)
RL
RL
GND
Reverse Polarity Protected
Fault Conditions
Reverse Polarity Protected
Fault Conditions
图 8-5. Low-Side Driver Configuration
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8.3.8 Integrated Surge Protection and Transient Waveform Tolerance
The VCC and OUT pins of the device are capable of withstanding up to 1.2 kV of 1.2/50 – 8/20 μs IEC
61000-4-5 surge with a source impedance of 500 Ω. The surge testing should be performed with a minimum 100
nF supply decoupling capacitor between VCC and GND, and 1 µF between VCC_IN/OUT and GND.
External TVS diodes may be required for higher transient protection levels. The system designer should ensure
that the maximum clamping voltage of the external diodes should be < 65 V at the desired current level. The
device is capable of withstanding up to ±65-V transient pulses < 100 µs.
R
Combination
Wave
Generator
EUT
VCC
OUT
GND
Decoupling
Network
>100nF
1.2/50 - 80/20 µs CWG
R = 500 Ω
图 8-6. Surge Test Setup
8.3.9 Power Up Sequence
VCC_IN and VCC domains can be powered up in any sequence. In the event of VCC is powered and VCC_IN is
not, the OUT pin remains in high impedance.
8.3.10 Undervoltage Lock-Out (UVLO)
The device enters UVLO if the VCC voltage falls below V(UVLO). (For the device without the integrated LDO, the
device monitors VCC_IN in addition to VCC. UVLO happens if either supply falls below the threshold.)
As soon as the supply falls below V(UVLO), NFAULT is pulled low, the LDO is turned off and the OUT output is
disabled (Hi-Z). Receiver performance is not specified in this mode.
When the supply rises above V(UVLO), NFAULT returns to Hi-Z (given no other fault conditions present) and the
LDO will be enabled immediately. The OUT output will be turned on after T(UVLO) delay.
8.4 Device Functional Modes
These devices can operate in three different modes.
8.4.1 NPN Configuration (N-Switch Mode)
Set IN pin high (or open) and use EN pin as control for realizing the function of an N-switch (low-side
configuration) on OUT.
8.4.2 PNP Configuration (P-Switch Mode)
Set IN pin low and use EN pin as control for realizing the function of a P-switch (high-side configuration) on OUT.
8.4.3 Push-Pull Mode
Set EN pin high and toggle IN as control for realizing the function of a push-pull output on OUT. 表 8-4, 表 8-5,
and 表 8-6 summarize the pin configurations to accomplish the functional modes.
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表 8-4. NPN Mode
EN
L / Open
H
IN
OUT
Hi-Z
H / Open
H / Open
N-Switch
表 8-5. PNP Mode
EN
L / Open
H
IN
OUT
Hi-Z
L
L
P-Switch
表 8-6. Push-Pull Mode
EN
IN
OUT
Hi-Z
L / Open
X
H / Open
L
H
H
N-Switch
P-Switch
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9 Application Information Disclaimer
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
TIOS101 and TIOS101x are robust 24-V digital drivers for industrial sensors.
9.2 Typical Application
TIOS101(x)
VCC_OUT
VCC
VOLTAGE
REGULATOR
0.1 µF
100 V
1 µF
10 V
10 kΩ
IN
OUT
Sensor
Front-End
EN
DIAGNOSTICS
and
CONTROL
NFAULT
CUR_OK
TMP_OK
PWR_OK
GND
ILIM_ADJ
RSET
图 9-1. Typical Application Schematic
9.2.1 Design Requirements
表 9-1 shows recommended components for a typical system design.
表 9-1. Design Parameters
PARAMETERS
VALUE
Input voltage range (VCC)
24 V, 30 V (max)
200 mA
Output current (OUT)
Output voltage (VCC_OUT), Pick TIOS1015
5 V
Maximum LDO output current (IVCC(OUT)
Pull-up resistors for NFAULT
VCC decoupling capacitor
)
5 mA
10 kΩ
0.1 µF / 100 V
1 µF / 10 V
10 kΩ
LDO output capacitor
ILIM_ADJ resistor (RSET
)
Maximum Ambient Temperature, TA
105°C
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9.2.2 Detailed Design Procedure
9.2.2.1 Maximum Junction Temperature Check
For a 200 mA current limit:
• The maximum driver output current limit, IO(LIM) = 250 mA (allowed for current limit tolerance).
• The maximum voltage drop across the high-side switch is given with VDS(ON) = 1.75 V.
This causes a power consumption of:
2&12 = 8&5(10) T +1(.+/) = 1.758 T 250 I# = 437.5 I9
(1)
For a 5 mA LDO current output,
:
;
2&.&1 = k8.+ F 88%%_176 o x +8%%_176 = 30 F 5 V x 5 mA = 125 mW
(2)
(3)
Total power dissipation,
2& = 2&12 + 2&.&1 = 437.5 I9 + 125 I9 = 562.5 I9
Multiply this value with the Junction-to-ambient thermal resistance of θJA = 68.1°C/W (taken from the 节 6.4
table) to receive the difference between junction temperature, TJ, and ambient temperature, TA:
¿6 = 6 F 6 = 2& x E,# = 562.5 I9 T 68.1°%/9 = 38.3°%
#
,
(4)
Add this value to the maximum ambient temperature of TA = 105°C to receive the final junction temperature:
6
,FI=T
= 6
+ ¿6 = 105°% + 38.3°% = 143.3°%
#FI=T
(5)
As long as TJ-max is below the recommended maximum value of 150°C, no thermal shutdown will occur.
However, thermal warning may occur as the junction temperature is greater than TWRN
.
Note that the modeling of the complete system may be necessary to predict junction temperature in smaller
PCBs and/or enclosures without air flow.
9.2.2.2 Driving Capacitive Loads
These devices are capable of driving capacitive loads on the OUT output. Assuming a pure capacitive load
without series/parallel resistance, the maximum capacitance that can be charged without triggering current fault
can be calculated as:
[I
x t
]
SC
O LIM
(
)
C
=
LOAD
V
VCC
(6)
Higher capacitive loads can be driven if a series resistor is connected between the OUT and the load. Capacitive
loads can be connected to VCC and GND.
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9.2.2.3 Driving Inductive Loads
The TIOS101(x) family is capable of magnetizing and demagnetizing inductive loads up to 1.5 H. These devices
contain internal circuitry that enables fast demagnetization when configured as either P-switch or N-switch mode.
In P-switch configuration, the load inductor L is magnetized when the OUT pin is driven high. When the PNP is
turned off, there is a significant amount of negative inductive kick back at the OUT pin. This voltage is clamped
internally at about -75 V.
Similarly in N-switch configuration, the load inductor L is magnetized when the OUT pin is driven low. When the
NPN is turned off, there is a significant amount of positive inductive kick back at the OUT pin. This voltage is
clamped internally at about 75 V.
The equivalent protection circuits are shown in 图 9-2 and 图 9-3. The minimum value of the resistive load R can
be calculated as:
V
VCC
(
)
R =
I
O(LIM)
(7)
spacer
VCC
OUT
VCC
OUT
R
L
L
R
TIOS101(x)
TIOS101(x)
图 9-3. NPN Mode
图 9-2. PNP Mode
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9.2.3 Application Curves
Time 10 ms/div
Time 1 ms/div
图 9-5. OUT Power Up Delay, Low Side Mode
125 kHz
图 9-4. OUT in Push-Pull Mode
Time 50 ms/div
Time 10 ms/div
图 9-7. OUT In Current Fault, Low Side Mode
图 9-6. OUT Power Up Delay, High Side Mode
Time 50 ms/div
Time 10 ms/div
图 9-9. OUT In Current Fault Auto Recovery, Low
图 9-8. OUT In Current Fault, High Side Mode
Side Mode
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Time 10 ms/div
Time 10 ms/div
1.5-H With = RSET
=
图 9-10. OUT In Current Fault Auto Recovery, High
Inductor OPEN
100 Ω
Side Mode
图 9-11. OUT Driving, Low Side Mode
Time 10 ms/div
1.5-H Inductor
RSET = OPEN
With = 100 Ω
图 9-12. OUT Driving, High Side Mode
10 Power Supply Recommendations
The TIOS101 and TIOS101x are designed to operate from a 24-V nominal supply at VCC, which can vary by
+12 V and -17 V from the nominal value to remain within the device's recommended supply voltage range of 7 V
to 36 V. This supply should be buffered with at least a 100-nF/100-V capacitor.
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11 Layout
11.1 Layout Guidelines
• Use of a 4-layer board is recommended for good heat conduction. Use layer 1 (top layer) for control signals,
layer 2 as GND, layer 3 for the 24-V supply plane (VCC), and layer 4 for the regulated output supply
(VCC_IN/OUT).
• Connect the thermal pad to GND with maximum amount of thermal vias for best thermal performance.
• Use entire planes for VCC, VCC_IN/OUT and GND to assure minimum inductance.
• The VCC terminal must be decoupled to ground with a low-ESR ceramic decoupling capacitor with a
minimum value of 100 nF. The capacitor must have a voltage rating of 50 V minimum (100 V depending on
max sensor supply fault rating) and an X5R or X7R dielectric.
•
• The optimum placement of the capacitor is closest to the VCC and GND terminals to reduce supply drops
during large supply current loads. See 图 11-1 for a PCB layout example.
• Connect all open-drain control outputs via 10 kΩ pull-up resistors to the VCC_IN/OUT plane to provide a
defined voltage potential to the system controller inputs when the outputs are high-impedance.
• Connect the RSET resistor between ILIM_ADJ and GND.
• Decouple the regulated output voltage at VCC_IN/OUT to ground with a low-ESR, 1 μF, ceramic decoupling
capacitor. The capacitor should have a voltage rating of 10 V minimum and an X5R or X7R dielectric.
11.2 Layout Example
VIA to Layer 2: Power Ground Plane (VCC)
VIA to Layer 3: 24V Supply Plane (GND)
VIA to Layer 4: Regulated Supply Plane (VCC_IN/OUT)
1uF/10V
V
100nF/
50V
C
C
_
I
N
/
O
U
NC
T
VCC
NFAULT
VCC
NC
OUT
GND
OUT
GND
IN
EN
Use Multiple Vias for
VCC and GND
Exposed Thermal
Pad Area
RSET
图 11-1. Layout Example
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12 Device and Documentation Support
12.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.4 静电放电警告
静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TIOS1013DMWR
TIOS1013DMWT
TIOS1015DMWR
TIOS1015DMWT
TIOS101DMWR
TIOS101DMWT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSON
VSON
VSON
VSON
VSON
VSON
DMW
DMW
DMW
DMW
DMW
DMW
10
10
10
10
10
10
1500 RoHS & Green
250 RoHS & Green
1500 RoHS & Green
250 RoHS & Green
1500 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
TS1013
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
TS1013
TS1015
TS1015
TS101
TS101
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
2-Feb-2021
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TIOS1013DMWR
TIOS1013DMWT
TIOS1015DMWR
TIOS1015DMWT
TIOS101DMWR
VSON
VSON
VSON
VSON
VSON
DMW
DMW
DMW
DMW
DMW
10
10
10
10
10
1500
250
178.0
178.0
178.0
178.0
178.0
13.5
13.5
13.5
13.5
13.5
2.75
2.75
2.75
2.75
2.75
3.35
3.35
3.35
3.35
3.35
1.05
1.05
1.05
1.05
1.05
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
Q2
1500
250
1500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TIOS1013DMWR
TIOS1013DMWT
TIOS1015DMWR
TIOS1015DMWT
TIOS101DMWR
VSON
VSON
VSON
VSON
VSON
DMW
DMW
DMW
DMW
DMW
10
10
10
10
10
1500
250
189.0
189.0
189.0
189.0
189.0
185.0
185.0
185.0
185.0
185.0
36.0
36.0
36.0
36.0
36.0
1500
250
1500
Pack Materials-Page 2
PACKAGE OUTLINE
DMW0010A
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
2.6
2.4
C
1 MAX
SEATING PLANE
0.08 C
1.65 0.1
SYMM
(0.2) TYP
0.05
0.00
EXPOSED
THERMAL PAD
5
6
2X
2
SYMM
11
1.95 0.1
1
10
8X 0.5
0.475
0.275
0.29
0.19
10X
10X
PIN 1 ID
(OPTIONAL)
0.1
C A B
C
0.05
4223225/A 08/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DMW0010A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
10X (0.575)
(0.575)
1
10
10X (0.24)
(0.725)
SYMM
11
(1.95)
8X (0.5)
(R0.05) TYP
5
6
(
0.2) VIA
TYP
SYMM
(2.825)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223225/A 08/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DMW0010A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
10X (0.575)
METAL
TYP
SYMM
1
11
10
10X (0.24)
(0.535)
SYMM
8X (0.5)
(0.87)
(R0.05) TYP
5
6
2X (1.5)
(2.825)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11
81% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4223225/A 08/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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