TIBPLS506ACFK [TI]
OT PLD, 20ns, CQCC28;
| 型号： | TIBPLS506ACFK |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OT PLD, 20ns, CQCC28 时钟 输入元件 可编程逻辑 |
| 文件： | 总16页 (文件大小：322K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TIBPLS506AC
13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
SRPS003C – D3090, DECEMBER 1987 – REVISED NOVEMBER 1995
JT OR NT PACKAGE
(TOP VIEW)
•
•
•
•
•
58-MHz Max Clock Rate
Two Transition Complement Array Terms
16-Bit Internal State Registers
8-Bit Output Registers
CLK
I0
V
CC
I6
1
24
23
22
21
20
19
18
17
16
15
14
13
2
I1
I7
3
I2
I8
4
Outputs Programmable for Registered or
Combinational Operation
I3
I9
5
I4
I5
I10
I11
I12/OE
Q7
Q6
Q5
Q4
6
7
•
Ideal for Waveform Generation and
High-Performance State Machine
Applications
Q0
Q1
Q2
Q3
GND
8
9
10
11
12
•
•
Programmable Output Enable
Programmable Clock Polarity
FK OR FN PACKAGE
(TOP VIEW)
description
The TIBPLS506AC is a TTL field-programmable
state machine of the Mealy type. This state
machine (logic sequencer) contains 97 product
terms (AND terms) and 48 sum terms (OR terms).
The product and sum terms are used to control the
16-bit internal state registers and the 8-bit output
registers.
4
3
2
1
28 27 26
25
5
I2
I3
I4
NC
I5
Q0
Q1
I8
I9
I10
6
24
23
7
8
22 NC
21 I11
20 I12/OE
19 Q7
9
The outputs of the internal state registers
(P0–P15) are fed back and combined with the
inputs (I0–I12) to form the AND array. In addition,
two sum terms are complemented and fed back to
the AND array, which allows any product m to
be summed, complemented, and used as inut to
the AND array.
10
11
12 13 14 15 16 17 18
NC – No internal connection
The eight output cells can be individually
programmed for registered or combinational
operation. Nonregistered operation is selected by
blowing the output multiplexer fuse. Registered
output operation is selected by leaving the output
multiplexer fuse intact.
Pin 17 can be programmeunction as an input and/or an output enable. Blowing the output enable fuse lets
pin 17 function as an output enable but does not disconnect pin 17 from the input array. When the output enable
fuse is intact, pin 17 functions only as an input with the outputs being permanently enabled.
The state and output registers are synchronously clocked by the fuse programmable clock input. The clock
polarity fuse selects either postive- or negative-edge triggering. Negative-edge triggering is selected by blowing
the clock polarity e. Leaving this fuse intact selects positive-edge triggering. After power-up, the device must
be initialized to the desired state. When the output multiplexer fuse is left intact, registered operation is selected.
The TIBPLS506AC is characterized for operation from 0°C to 75°C.
PRODUCTION DATA information is current as of publication date.
Copyright 1995, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
logic diagram (positive logic)
1
CLK
DETAIL:
10670
1S
C1
2
0
I0
3
I1
4
1R
I2
5
5
I3
6
Each S-R Flip-Flop
I4
7
10
15
20
25
I5
23
I6
MUX
1
22
I7
21
I8
20
I9
19
I10
G1
18
17
I11
PRE/OE
Each Multiplexer
P0
26
30
36
41
46
51
10671
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
C0
P15
59
60
C
5
1S
1
1S
C1
1R
64
68
72
P14
P0
P1
P2
P3
P4
1S
C1
1R
1S
C1
1R
1S
C1
1R
1S
C1
1R
1S
C1
1R
1S
C1
1R
76
80
84
88
92
P5
1S
C1
1R
P6
1S
C1
1R
P7
1S
C1
1R
P8
1S
C1
1R
P9
1S
C1
1R
P10
P11
P12
P13
1S
C1
1R
1S
C1
1R
1S
C1
1R
MUX
1
8
9
1S
C1
1R
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
G1
10672
10673
10674
10675
10676
10677
10678
10679
MUX
1
1S
C1
1R
96
100
104
G1
MUX
1
10
11
13
14
15
16
1S
C1
1R
G1
MUX
1
1S
C1
1R
G1
MUX
1
1S
C1
1R
1
MUX
1
1S
C1
1R
G1
MUX
1
1S
C1
1R
G1
MUX
1
1S
C1
1R
108
109
G1
All inputs to AND gates, exclusive-OR gates, and multiplexers with a blown link assume the logic-1 state.
All OR gate inputs with a blown link assume the logic-0 state.
TIBPLS506AC
13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
SRPS003C – D3090, DECEMBER 1987 – REVISED NOVEMBER 1995
S-R FUNCTION TABLE (see Note 1)
CLK POLARITY FUSE CLK
S
L
R
L
STATE REGISTER
INTACT
INTACT
INTACT
INTACT
BLOWN
BLOWN
BLOWN
BLOWN
↑
↑
↑
↑
↓
↓
↓
↓
Q
0
L
H
L
L
H
H
L
H
H
L
INDETERMINATE
Q
0
L
H
L
L
H
H
H
H
INDETENATE
NOTE 1: Q is the state of the S-R registers before the active clck edge.
0
functional block diagram (positive logic)
CLK
16
2
≥1
97 x 50
C1
16 x
&
16
16
16
8
1S
60 x 97
1R
8 x MUX
2
2
2 x
1
1
16
16 x
16
C1
8 x
97
16
8
Q0 – Q7
8
8
8
1S
12
1
13
13
13 x
I0 – I11
I12/OE
G1
EN
1R
denotes fused inputs
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4
TIBPLS506AC
13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
SRPS003C – D3090, DECEMBER 1987 – REVISED NOVEMBER 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to disabled output (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
NOTE 2: These ratings apply except when programming pins during a programming cycle or during diagnostic testing.
recommended operating conditions
MIN NOM
MAX
5.25
5.5
UNIT
V
V
V
V
Supply voltage
4.75
2
5
CC
IH
High-level input voltage, V
= 5.25 V
= 4.75 V
V
CC
CC
Low-level input voltage, V
High-level output current
Low-level output current
0.8
V
IL
I
I
–3.2
16
mA
mA
OH
OL
Clock high
6
6
t
w
ns
Pulse duration
Clock low
Input or feedback to S/R↑ inputs
Input or feedback to S/R↓ inputs
Input or feedback to S/R inputs
Input or feedback to S/R input
12
20
25
0
Without C-array
With C-array
Setup time before CLK
active transition
‡
t
ns
su
†
t
h
Hold time after CLK
Operating free-air temperature
ns
T
0
25
75
°C
A
†
‡
The active edge of CLK is determined by the programmed state of CLK polarity fuse.
See the OR term loading section and Figure 3.
electrical characteristics over recommendoperating free-air temperature range (unless
otherwise noted)
§
PARAMETER
TECONDITIONS
I 8 mA
MIN TYP
MAX
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= 4.75 V,
= 4.75 V,
= 4.75 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5
= 5.25 V,
–1.2
IK
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
I
I
I
= –3.2 mA
= 16 mA
= 2.7 V
2.4
3
V
OH
OL
OZH
OZL
I
OH
OL
0.37
0.5
20
V
I
I
I
I
I
I
I
V
µA
µA
mA
µA
mA
mA
mA
pF
pF
pF
O
O
V
= 0.4 V
–20
0.1
V = 5.5 V
I
V = 2.7 V
I
20
IH
V = 0.4 V
I
–0.25
–130
210
IL
¶
V
O
= 0.5 V
–30
O
See Note 3,
V = 2 V
Outputs open
156
7
CC
C
C
C
f = 1 MHz,
f = 1 MHz,
f = 1 MHz,
i
I
V = 2 V
O
11
14
o
V = 2 V
CLK
clk
§
¶
All typical values are at V
= 5 V, T = 25°C.
A
OS
C
This parameter approximates I . The condition V = 0.5 V takes tester noise into account. Not more than one output should be shorted at a
time and duration of the short circuit should not exceed one second.
O
NOTE 3: When the clock is programmed for negitive edge, then V = 4.75 V. When the clock is programmed for positive edge, then V = 0.
I
I
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
TIBPLS506AC
13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
SRPS003C – D3090, DECEMBER 1987 – REVISED NOVEMBER 1995
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
TEST CONDITION
MIN TYP
MAX
UNIT
MHz
ns
Without C-array
With C-array
58
33
45
28.5
6
65
45
60
40
‡
f
max
External feedback without C-array
External feedback with C-array
R1 = 300 Ω,
R2 = 390 Ω,
See Figure 5
Q (nonregistered)
25
10
20
10
10
CLK
t
pd
Q (registered)
3
I or Feedback
OE↓
Q (nonregistered)
6
ns
ns
ns
t
t
Q
Q
1
1
6
6
en
OE↑
dis
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
calculations section.
See the f
max
f
calculations
max
The following is a brief description of how the different operating frequencies can be achieved when using the
TIBPLS506A.
1
f
without C-(complementary) array =
where setup time t before CLK at the S/R
su
max
t
t
LK to Q
su
register inputs = 12 ns and propagation delay time t CLK to Q for the internal S/R registers = 5ns (difference
pd
in t from CLK and feedback, 25 to 20).
pd
1
1
Thus: f
for this condition
58 MHz.
max
(12 + 5) ns
17 ns
1
f
with the C-array =
where t setup time before CLK at the S/R register
su
max
t
t
LK to Q
su
pd
inputs = 25 ns and propagation delay time t CLK to Q for the internal S/R registers = 5 ns (difference in t
from CLK and feedback, 25 to 20)
pd
pd
1
1
Thus: f
for this condition
33 MHz.
where setup time t before CLK at the
max
(25 + 5) ns
30 ns
1
f
external feedback without the C-array =
max
su
t
t
CLK to Q
su
pd
S/R register inputs = 12 ns and propagation delay time t CLK to Q for the internal S/R registers = 10 ns
pd
1
1
Thus: f
for this con
45 MHz.
max
(12 + 10) ns
22 ns
1
f
external feedback with the C-array =
where setup time t before CLK at the S/R
max
su
t
t
CLK to Q
su
register inputs = 25 ns and propagation delay time t CLK to Q for the internal S/R registers = 10 ns.
pd
pd
1
1
Thus: f
for this condition
28.5 MHz.
max
(25 + 10) ns
35 ns
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6
TIBPLS506AC
13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
SRPS003C – D3090, DECEMBER 1987 – REVISED NOVEMBER 1995
Dedicated Inputs
a, b
t
Min Clock Period for This Path
Internal SRs
min(2)
c
a
C Array
b, c
SR
SR
Feedback Lines
t
I to Internal S or R,
su(a)
Data Through C Array
CLK
SR
SR
t
Min Clock Period
min(3)
for This Path
t
I to Internal S or R
su(2)
CLK Internal
Output SRs
CLK
SR
t
Min Clock Period
min(1)
for This Path
t
CLK Internal to Output Response
pd(3)
SR
SR
t
or t
min(c)
su(b)
t
t
or t
pd(c)
pd(b)
pd(2)
CLK to Q Pin
t
I to Output S or R
su(1)
t
I to Output Pin
pd(1)
Dedicated Inputs
Output Pin
Figure 1. Timing Model
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
TIBPLS506AC
13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
SRPS003C – D3090, DECEMBER 1987 – REVISED NOVEMBER 1995
glossary — timing model
t
t
t
t
—
—
—
Maximum time interval from the time a signal edge is received at any input pin to the time any logically
affected combinational output pin delivers a response.
pd(1)
pd(2)
pd(3)
Maximum time interval from a positive edge on the clock input pin to data delivery on the output pin
corresponding to any output SR register.
Maximum time interval from the positive edge on the clock input pin to the response on any logically
affected combinational configured output (at the pin), where data origin is any internal SR register.
) — Maximum time interval from the time a signal edge is received at any input pin to the time any logically
affected combinational output pin delivers a response, where data passes through a C-array once
before reaching the affected output.
pd(b
t
—
Maximum time interval from the positive edge on the clock input pin to the response on any logically
affected combinational configured output (at the pin), where data origin is any internal SR register
and data passes once through a C-array before reaching an affected output.
pd(c)
t
t
t
—
—
—
Minimum time interval that must be allowed between the data edge on any dedicated input and the
active clock edge on the clock input pin when data affects the S or R line of any output SR register.
su(1)
su(2)
su(a)
Minimum time interval that must be allowed between the data edge on any dedicated input and the
active clock edge on the clock input pin when ta affects the S or R line of any internal SR register.
Minimum time interval that must be allowed between the data edge on any dedicated input and the
active clock edge on the clock input pin whata passes once through a C-array before reaching
an affected S or R line on any internal SR register.
t
—
Minimum time interval that must be allowed between the data edge on any dedicated input and the
active clock edge on the clock input n when data passes once through a C-array before reaching
an affected S or R line on any outpuregister.
su(b)
t
t
t
— Minimum clock period (or 1/[maximum frequency]) that the device will accommodate when using
feedback from any internal SR rister or counter bit to feed the S or R line of any output SR register.
min(1)
min(2)
min(3)
— Minimum clock period (or 1/[maxmum frequency]) that the device will accommodate when using
feedback from any internal SR register to feed the S or R line of any internal SR register.
— Minimum clock period (or 1/[maximum frequency]) that the device will accommodate when using
feedback from any internal SR register to feed the S or R line of any internal SR register and data
passes once through a C-array before reaching an affected S or R line on any internal SR register.
t
— Minimum clock period (or 1/[maximum frequency]) that the device will accommodate when using
feedback from any internal SR register to feed the S or R line of any output SR register and data
passes once through a C-array before reaching an affected S or R line on any output SR register.
min(c)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8
TIBPLS506AC
13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
SRPS003C – D3090, DECEMBER 1987 – REVISED NOVEMBER 1995
PARAMETER VALUES FOR TIMING MODEL
†
†
t
t
t
= 20 ns
= 10 ns
= 25 ns
t
t
t
t
= 12 ns
= 12 ns
= 25 ns
= 25 ns
t
t
t
t
= 20 ns
= 20 ns
= 25 ns
= 25 ns
pd(1)
pd(2)
pd(3)
su(1)
su(2)
su(a)
su(b)
min(1)
min(2)
min(3)
min(c)
INTERNAL NODE NUMBERS
RESET 25-32 P0-P15
Q0-Q7
SET 33-48
C0
C1
65
66
RESET 49-64
†
Use tsu = 20 ns for applications where the setup time for S/R↓ inputs are required.
diagnostics
A diagnostic mode is provided with these devices that allows the user to inspect the contents of the state
registers. The step-by-step procedures required to use the diagnostics follow.
Step 1.
Step 2.
Step 3.
Disable all outputs by taking pin 17 (OE) high (see Note 4).
Take pin 8 (Q0) to V to enable the diagnostics test sequence.
Apply appropriate levels of voltage to pins 11 (Q3), 13 (Q4), and 14 (Q5) to select the desired
state register (see Table 1).
IHH
The voltage level monitored on pin 9 will indicate the of the selected state register.
NOTE 4: If pin 17 is being used as an input to the array, then pin 7 (I5) must be taken to V
before pin 17 is taken high.
IHH
†
V
IHH
I5
Pin 7
V
IH
OE
Pin 17
100 ns
V
V
OHH
OH
Q0
Pin 8
V
V
OL
100 ns
OHH
V
OH
Q3, Q4, Q5
Pins 11, 13, 14
V
V
OL
100 ns
OH
Q1
Pin 9
V
OL
†
V
IHH
= 10.25 V min, 10.5 V nom, 10.75 V max
Figure 2. Diagnostics Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
TIBPLS506AC
13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
SRPS003C – D3090, DECEMBER 1987 – REVISED NOVEMBER 1995
Table 1. Addressing State Registers
†
During Diagnostics
REGISTER BINARY ADDRESS
BURIED REGISTER
PIN 11
PIN13
L
PIN 14
L
SELECTED
C1
L
L
L
H
P15
C0
L
L
HH
L
L
H
P14
P0
L
H
H
L
H
HH
L
P1
L
HH
HH
HH
L
P2
L
H
P3
L
HH
L
P4
H
H
H
H
H
H
H
H
H
P5
L
H
P6
L
HH
L
P7
H
P8
H
H
P9
H
HH
L
P10
P11
P12
P13
HH
HH
HH
H
HH
†
V
IHH
= 10.25 V min, 10.5 V nom, 10.75 V max
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers that are capable of programming Texas
Instruments programmable logic is also available, upon request, from the nearest TI sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 997-5666.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10
TIBPLS506AC
13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
SRPS003C – D3090, DECEMBER 1987 – REVISED NOVEMBER 1995
OR term loading
As shown in Figure 3 and by the f
calculations, f
is calculated as:
is affected by the number of terms connected to each
max
max
OR array line. Theoretically, f
max
1
f
=
max
t
t
CLK to Q
su
pd
Since the setup time (input or feedback to S/R↓) varies with the number of terms connected to each OR array
line, (due to capacitance loading) f will also vary. Figure 3 illustrates the relationship between the number of
max
terms connected per OR line and the setup time.
Use Figure 3 to determine the worst-case setup time for a particular appation. Identify the OR array line with
the maximum number of terms connected. Count the number of terms ane the graph to determine the setup
time.
WORST-CASE SETUP TIME
(input or feedback to SR↓)
vs
”OR” TERM LOAD
20
V
T
= 4.75 V
CC
= 75°C
A
19
18
17
16
15
14
13
12
11
10
0
20
40
60
80
100
Maximum Number of OR Terms Connected
Figure 3
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11
TIBPLS506AC
13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
SRPS003C – D3090, DECEMBER 1987 – REVISED NOVEMBER 1995
f
with external feedback
max
The configuration shown is a typical state-machine design with feedback signals sent off-chip. This external
feedback could go back to the device inputs or to a second device in a multi-chip state machine. The slowest
path defining the clock period is the sum of the clock-to-output delay time and the setup time for the input or
feedback signals (t + t CLK to Q).
su
pd
1
Thus: f
with external feedback =
max
t
t
CLK to Q
su
pd
Internal
SR
Registers
CLK
Logic
Array
Input
Output
SR
Registers
Next Device
t
pd
t
su
CLK to Q
Figure 4
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12
TIBPLS506AC
13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
SRPS003C – D3090, DECEMBER 1987 – REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
5 V
S1
R1
From Output
Under Test
Test
Point
C
R2
L
(see Note A)
LOAD CIRCUIT FOR
3-STATE OUTPUTS
3.5 V
0.3 V
High-Level
Pulse
3.5 V
0.3 V
1.5 V 1.5 V
Timing
Input
1.5 V
t
w
t
h
t
su
3.5 V
0.3 V
3.5 V
0.3 V
Data
Input
Lw-Level
Pulse
1.5 V
1.5 V 1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
0.3 V
Output
Control
(low–level
3.5 V
0.3 V
1.5 V
1.5 V
1.5 V
1.5 V
Input
enabling)
t
en
t
pd
t
t
t
dis
pd
V
OH
In-Phase
Output
≈ 3.3 V
1.5 V
1.5 V
1.5 V
Waveform 1
S1 Closed
(see Note B)
1.5 V
V
+0.5 V
OL
V
OL
V
OL
t
pd
pd
t
dis
V
OH
t
en
Out-of-Phase
Output
(see Note D)
1.5 V
V
OH
Waveform 2
S1 Open
(see Note B)
V
OL
1.5 V
V
–0.5 V
OH
≈ 0 V
VOLTAGE WAVEFORMS
PROPAGATION DELMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. C includes probe and jig capacitance and is 50 pF for t and t , 5 pF for t
pd en dis
.
L
B. Waveform1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output wh internal conditions such that the output is high except when disabled by the output control.
C. All input pulses ve the following characteristics: PRR ≤ 1 MHz, t = t ≤ 2 ns, duty cycle = 50%.
r
f
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
Figure 5. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
13
TIBPLS506AC
13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
SRPS003C – D3090, DECEMBER 1987 – REVISED NOVEMBER 1995
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
200
175
150
125
V
CC
= 5.25 V
V
CC
= 5 V
100
75
V
CC
= 4.75 V
50
25
0
0
25
50
75
T
A
– Free-Air Temperature – °C
Figure 6
POWER DISSIPATION
vs
REQUENCY
1000
950
900
800
750
700
T
= 0°C
A
T
= 25°C
A
T
= 50°C
A
1
2
4
7
10
20
40
70 100
f – Frequency – MHz
Figure 7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
14
TIBPLS506AC
13 × 97 × 8 FIELD-PROGRAMMABLE LOGIC SEQUENCER
SRPS003C – D3090, DECEMBER 1987 – REVISED NOVEMBER 1995
TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME
PROPAGATION DELAY TIME
vs
vs
SUPPLY VOLTAGE
LOAD CAPACITANCE
30
25
20
15
10
5
20
18
16
14
12
10
8
V
= 5 V
CC
R1 = 300 Ω
R2 = 390 Ω
T
A
t
(I or Feedback to Q)
= 25°C
PHL
t
(I or Feedback to Q)
PLH
t
t
t
t
(I or Feedback to Q)
(I or Feedback to Q)
(CLK to Q)
t
(CLK to Q)
PHL
PLH
PLH
PHL
PLH
6
t
(CLK to Q)
PHL
(CLK to Q)
4
2
0
R1 = 300 Ω
R2 = 390 Ω
C
= 50 pF
= 25°C
L
T
A
0
0
100
200
300
400
500
600
4.75
5
5.25
C
– Load Capacitance – pF
V
CC
– Supply Voltage – V
L
Figure 9
Figure 8
PROPAGATION DELAY TIME
vs
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
NUMBER OF OUTPUTS SWITCHING
20
18
16
14
12
10
8
20
18
16
14
12
10
8
t
(I or Feedback to Q)
PHL
t
(I or Feedback to Q)
PHL
t
(I or Feedback to Q)
PLH
t
(I or Feedback to Q)
PLH
t
t
(CLK to Q)
(CLK to Q)
PLH
PHL
t
(CLK to Q)
PLH
6
6
t
(CLK to Q)
PHL
V
= 5 V
CC
4
2
0
4
2
0
V
= 5 V
R1 = 300 Ω
R2 = 390 Ω
R1 = 300 Ω
R2 = 390 Ω
CC
C
T
= 50 pF
L
C
= 50 pF
= 25°C
L
A
0
25
50
75
0
1
2
3
4
5
6
7
8
– Free-Air Temperature – °C
Number of Outputs Switching
Figure 10
Figure 11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
15
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