TIBPAL22V10AMFKB [TI]
High-Performance Impact Programmable Array Logic Circuits 28-LCCC -55 to 125;
| 型号： | TIBPAL22V10AMFKB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High-Performance Impact Programmable Array Logic Circuits 28-LCCC -55 to 125 时钟 输入元件 可编程逻辑 |
| 文件： | 总22页 (文件大小：564K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TIBPAL22V10AM is Not Recommended For New Designs
TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM
HIGH-PERFORMANCE IMPACTꢀ™ PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024A − OCTOBER 1986 − REVISED APRIL 2010
C SUFFIX . . . NT PACKAGE
M SUFFIX . . . JT OR W PACKAGE
• Second-Generation PLD Architecture
(TOP VIEW)
• Choice of Operating Speeds
TIBPAL22V10AC . . . 25 ns Max
TIBPAL22V10AM . . . 30 ns Max
TIBPAL22V10C . . . 35 ns Max
CLK/I
VCC
1
24
23
22
21
20
19
18
17
16
15
14
13
I
I
I
I
I
I
I
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
2
3
• Increased Logic Power − Up to 22 Inputs
4
and 10 Outputs
5
6
• Increased Product Terms − Average of 12
7
Per Output
8
• Variable Product Term Distribution
Allows More Complex Functions to Be
Implemented
9
I
I
10
11
12
GND
• Each Output Is User Programmable for
Registered or Combinational Operation,
Polarity, and Output Enable Control
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
• TTL-Level Preload for Improved Testability
(TOP VIEW)
• Extra Terms Provide Logical Synchronous
Set and Asynchronous Reset Capability
• Fast Programming, High Programming
Yield, and Unsurpassed Reliability Ensured
Using Ti-W Fuses
4
3
2
1
28 27 26
25
5
6
7
8
9
I
I
I
I/O/Q
I/O/Q
I/O/Q
24
23
• AC and DC Testing Done at the Factory
NC
22 NC
Utilizing Special Designed-In Test Features
I
I
I
21 I/O/Q
20 I/O/Q
19 I/O/Q
10
11
• Dependable Texas Instruments Quality and
Reliability
12 13 14 15 16 17 18
• Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
NC − No internal connection
Pin assignments in operating mode
• Functionally Equivalent to AMDs
AMPAL22V10 and AMPAL22V10A
description
The TIBPAL22V10 and TIBPAL22V10A are programmable array logic devices featuring high speed and
functional equivalency when compared to presently available devices. They are implemented with the familiar
sum-of-products (AND-OR) logic structure featuring the new concept “Programmable Output Logic Macrocell”.
These IMPACT™ circuits combine the latest Advanced Low-Power Schottky technology with proven
titanium-tungsten fuses to provide reliable, high-performance substitutes for conventional TTL logic.
These devices contain up to 22 inputs and 10 outputs. They incorporate the unique capability of defining and
programming the architecture of each output on an individual basis. Outputs may be registered or nonregistered
and inverting or noninverting as shown in the output logic macrocell diagram. The ten potential outputs are
enabled through the use of individual product terms.
These devices are covered by U.S. Patent 4,410,987.
IMPACT is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Copyright © 2010, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
TIBPAL22V10AM is Not Recommended For New Designs
TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM
HIGH-PERFORMANCE IMPACTꢀ™ PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024A − OCTOBER 1986 − REVISED APRIL 2010
description (continued)
Further advantages can be seen in the introduction of variable product term distribution. This technique
allocates from 8 to 16 logical product terms to each output for an average of 12 product terms per output. This
variable allocation of terms allows far more complex functions to be implemented than in previously available
devices.
Circuit design is enhanced by the addition of a synchronous set and an asynchronous reset product term. These
functions are common to all registers. When the synchronous set product term is a logic 1, the output registers
are loaded with a logic 1 on the next low-to-high clock transition. When the asynchronous reset product term
is a logic 1, the output registers are loaded with a logic 0. The output logic level after set or reset depends on
the polarity selected during programming. Output registers can be preloaded to any desired state during testing.
Preloading permits full logical verification during product testing.
With features such as programmable output logic macrocells and variable product term distribution, the
TIBPAL22V10 and TIBPAL22V10A offer quick design and development of custom LSI functions with
complexities of 500 to 800 equivalent gates. Since each of the ten output pins may be individually configured
as inputs on either a temporary or permanent basis, functions requiring up to 21 inputs and a single output or
down to 12 inputs and 10 outputs are possible.
A power-up clear function is supplied that forces all registered outputs to a predetermined state after power is
applied to the device. Registered outputs selected as active-low power up with their outputs high. Registered
outputs selected as active-high power up with their outputs low.
A single security fuse is provided on each device to discourage unauthorized copying of fuse patterns. Once
blown, the verification circuitry is disabled and all other fuses will appear to be open.
The TIBPAL22V10C and TIBPAL22V10AC are characterized for operation from 0°C to 75°C. The
TIBPAL22V10AM is characterized for operation over the full military temperature range of −55°C to125°C.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2
TIBPAL22V10AM is Not Recommended For New Designs
TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM
HIGH-PERFORMANCE IMPACTꢀ™ PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024A − OCTOBER 1986 − REVISED APRIL 2010
functional block diagram (positive logic)
C1
1S
Set
&
Reset
44 x 132
R
8
1
Output
Logic
Macrocell
I/O/Q
EN
10
12
14
16
16
14
12
10
8
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
22
EN
EN
EN
EN
EN
EN
EN
EN
EN
CLK/I
11
10
22
I
10
10
10
denotes fused inputs
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
TIBPAL22V10AM is Not Recommended For New Designs
TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM
HIGH-PERFORMANCE IMPACTꢀ™ PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024A − OCTOBER 1986 − REVISED APRIL 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4
TIBPAL22V10AM is Not Recommended For New Designs
TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM
HIGH-PERFORMANCE IMPACTꢀ™ PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024A − OCTOBER 1986 − REVISED APRIL 2010
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
TIBPAL22V10AM is Not Recommended For New Designs
TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM
HIGH-PERFORMANCE IMPACTꢀ™ PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024A − OCTOBER 1986 − REVISED APRIL 2010
output logic macrocell diagram
Output Logic Macrocell
MUX
2
3
I = 0
AR
SS
R
1D
0
1
1
0
C1
1S
0
3
G
From Clock Buffer
S0
MUX
1
1
G1
S1
AR = asynchronous reset
SS = synchronous set
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6
TIBPAL22V10AM is Not Recommended For New Designs
TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM
HIGH-PERFORMANCE IMPACTꢀ™ PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024A − OCTOBER 1986 − REVISED APRIL 2010
R
R
1D
1D
C1
1S
C1
1S
S1 = 0
S0 = 0
S1 = 0
S0 = 1
REGISTER FEEDBACK, REGISTERED, ACTIVE-LOW OUTPUT
REGISTER FEEDBACK, REGISTERED, ACTIVE-HIGH OUTPUT
S1 = 1
S0 = 0
S1 = 1
S0 = 1
I/O FEEDBACK, COMBINATIONAL, ACTIVE-LOW OUTPUT
I/O FEEDBACK, COMBINATIONAL, ACTIVE-HIGH OUTPUT
MACROCELL FEEDBACK AND OUTPUT FUNCTION TABLE
FUSE SELECT
FEEDBACK AND OUTPUT CONFIGURATION
S1
0
S0
0
Register feedback
Register feedback
I/O feedback
Registered
Registered
Active low
Active high
0
1
1
0
Combinational Active low
Combinational Active high
1
1
I/O feedback
0 = unblown fuse, 1 = blown fuse
S1 and S0 are select-function fuses as shown in the output logic macrocell
diagram.
Figure 1. Resultant Macrocell Feedback and Output Logic After Programming
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
TIBPAL22V10AM is Not Recommended For New Designs
TIBPAL22V10C, TIBPAL22V10AC
HIGH-PERFORMANCE IMPACTꢀ™ PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024A − OCTOBER 1986 − REVISED APRIL 2010
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −5.5 V
Voltage range applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.
recommended operating conditions
TIBPAL22V10C
MIN NOM MAX
TIBPAL22V10AC
MIN NOM MAX
UNIT
V
V
V
Supply voltage
4.75
2
5
5.25
5.5
0.8
−3.2
16
4.75
2
5
5.25
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
0.8
V
I
I
f
−3.2
16
mA
mA
MHz
OH
OL
†
Clock frequency
18
28.5
clock
Clock high or low
25
35
30
30
30
35
0
15
25
20
20
25
25
0
t
Pulse duration
ns
w
Asynchronous reset high or low
Input
Feedback
t
su
Setup time before clock↑
ns
Synchronous set
Asynchronous reset low (inactive)
t
Hold time, input, set, or feedback after clock↑
ns
h
T
A
Operating free-air temperature
0
75
0
75
°C
1
†
1
f
(with feedback) =
, f
clock
(without feedback) =
clock
t
) t (CLK to Q)
t (low) ) t (high)
su
pd
w
w
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8
TIBPAL22V10AM is Not Recommended For New Designs
TIBPAL22V10C, TIBPAL22V10AC
HIGH-PERFORMANCE IMPACTꢀ™ PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024A − OCTOBER 1986 − REVISED APRIL 2010
electrical characteristics over recommended operating free-air temperature range
TIBPAL22V10C
TIBPAL22V10AC
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
V
V
= 4.75 V, I = −18 mA
−1.2
−1.2
V
V
V
IK
CC
CC
CC
I
= 4.75 V,
= 4.75 V,
I
I
= −3.2 mA
= 16 mA
2.4
3.5
0.35
2.4
3.5
0.35
OH
OL
OH
OL
0.5
0.1
0.5
0.1
I
V
CC
= 5.25 V,
V = 2.7 V
O
mA
OZH
Any output
Any I/O
−100
−100
V
= 5.25 V,
V = 0.4 V
I
I
μA
CC
I
IL
−250
1
−250
1
V
= 5.25 V, V = 5.5 V
mA
I
CC
I
I
I
V
V
= 5.25 V, V = 2.7 V
25
25
μA
mA
IH
CC
I
= 5.25 V, V = 0.4 V
−0.25
−0.25
IL
CC
I
‡
I
I
V
V
= 5.25 V,
V = 0.5 V
O
−30
−90
180
−30
−90
180
mA
mA
OS
CC
= 5.25 V, V = GND,
Outputs open
120
120
CC
CC
I
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
FROM
TO
TIBPAL22V10C
TIBPAL22V10AC
UNIT
PARAMETER
TEST CONDITIONS
†
†
(INPUT)
(OUTPUT)
MIN TYP
MAX
MIN TYP
MAX
¶
f
t
t
t
t
t
With feedback
18
28.5
MHz
ns
max
I, I/O
I, I/O (reset)
CLK
I/O
Q
R1 = 300 Ω,
R2 = 390 Ω,
See Figure 4
15
35
40
25
35
35
15
25
30
15
25
25
pd
15
10
15
15
15
10
15
15
ns
pd
Q
ns
pd
I, I/O
I/O, Q
I/O, Q
ns
en
I, I/O
ns
dis
†
‡
All typical values are at V = 5 V, T = 25°C.
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. V is set at 0.5 V to
CC
A
O
avoid test problems caused by test equipment ground degradation.
1
¶
1
f
(with feedback) =
, f
max
(without feedback) =
max
t
) t (CLK to Q)
t (low) ) t (high)
su
pd
w
w
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
TIBPAL22V10AM is Not Recommended For New Designs
TIBPAL22V10AM
HIGH-PERFORMANCE IMPACTꢀ™ PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024A − OCTOBER 1986 − REVISED APRIL 2010
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −5.5 V
Voltage range applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.
recommended operating conditions
MIN NOM
MAX
5.5
5.5
0.8
−2
UNIT
V
V
V
V
Supply voltage
4.5
2
5
CC
IH
IL
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
V
V
I
I
mA
mA
OH
12
OL
†
f
t
Clock frequency
22
MHz
ns
clock
Clock high or low
20
30
25
25
25
30
0
Pulse duration
w
Asynchronous reset high or low
Input
Feedback
t
su
Setup time before clock↑
ns
Synchronous set
Asynchronous reset low (inactive)
t
h
Hold time, input, set, or feedback after clock↑
ns
T
A
Operating free-air temperature
−55
125
°C
1
†
1
f
(with feedback) =
, f
clock
(without feedback) =
clock
t
) t (CLK to Q)
t (low) ) t (high)
su
pd
w
w
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10
TIBPAL22V10AM is Not Recommended For New Designs
TIBPAL22V10AM
HIGH-PERFORMANCE IMPACTꢀ™ PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024A − OCTOBER 1986 − REVISED APRIL 2010
electrical characteristics over recommended operating free-air temperature range
†
PARAMETER
TEST CONDITIONS
I = −18 mA
MIN TYP
MAX
UNIT
V
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 4.5 V,
−1.2
V
V
V
IK
CC
CC
CC
I
I
I
= −2 mA
= 12 mA
2.4
3.5
0.25
OH
OL
OH
OL
0.5
0.1
I
V
CC
= 5.5 V,
V
O
V
O
= 2.7 V
= 0.4 V
mA
OZH
I
I
V
V
= 5.5 V,
= 5.5 V,
−100
1
μA
mA
OZL
CC
V = 5.5 V
I
I
CC
I
I
V
V
= 5.5 V,
= 5.5 V,
V = 2.7 V
25
μA
mA
IH
CC
I
V = 0.4 V
I
−0.25
IL
CC
‡
I
I
V
V
= 5.5 V,
= 5.5 V,
V = 0.5 V
O
−30
−90
180
mA
mA
OS
CC
V = GND,
I
Outputs open
120
CC
CC
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
¶
f
t
t
t
t
t
With feedback
22
MHz
ns
max
I, I/O
I, I/O (reset)
CLK
I/O
Q
R1 = 390 Ω,
R2 = 750 Ω,
See Figure 4
15
15
10
15
15
30
35
20
30
30
pd
ns
pd
Q
ns
pd
I, I/O
I/O, Q
I/O, Q
ns
en
I, I/O
ns
dis
†
‡
All typical values are at V = 5 V, T = 25°C.
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. V is set at 0.5 V to
CC
A
O
avoid test problems caused by test equipment ground degradation.
1
¶
1
f
(with feedback) =
, f
max
(without feedback) =
max
t
) t (CLK to Q)
t (low) ) t (high)
su
pd
w
w
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
TIBPAL22V10AM is Not Recommended For New Designs
TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM
HIGH-PERFORMANCE IMPACTꢀ™ PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024A − OCTOBER 1986 − REVISED APRIL 2010
preload procedure for registered outputs (see Notes 2 and 3)
The output registers can be preloaded to any desired state during device testing. This permits any state to be
tested without having to step through the entire state-machine sequence. Each register is preloaded individually
by following the steps given below:
Step 1. With V at 5 V and pin 1 at V , raise pin 13 to V .
IHH
CC
IL
Step 2. Apply either V or V to the output corresponding to the register to be preloaded.
IL
IH
Step 3. Pulse pin 1, clocking in preload data.
Step 4. Remove output voltage, then lower pin 13 to V . Preload can be verified by observing the voltage level
IL
at the output pin.
V
V
IHH
Pin 13
IL
t
t
d
su
t
t
w
d
V
V
V
V
IH
Pin 1
IL
V
V
IH
OH
OL
Registered I/O
Input
Output
IL
Figure 2. Preload Waveforms
NOTES: 2. Pin numbers shown are for JT and NT packages only. If chip-carrier socket adapter is not used, pin numbers must be changed
accordingly.
3. td = tsu = tw = 100 ns to 1000 ns. VIHH = 10.25 V to 10.75 V.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
12
TIBPAL22V10AM is Not Recommended For New Designs
TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM
HIGH-PERFORMANCE IMPACTꢀ™ PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024A − OCTOBER 1986 − REVISED APRIL 2010
power-up reset
Following power up, all registers are reset to zero. The output level depends on the polarity selected during
programming. This feature provides extra flexibility to the system designer and is especially valuable in
simplifying state-machine initialization. To ensure a valid power-up reset, it is important that the rise of V
be
CC
monotonic. Following power-up reset, a low-to-high clock transition must not occur until all applicable input and
feedback setup times are met.
V
CC
5 V
4 V
†
t
pd
(600 ns typ, 1000 ns MAX)
V
OH
Active High
State Unknown
1.5 V
1.5 V
Registered Output
V
V
OL
OH
Active Low
Registered Output
State Unknown
V
OL
‡
t
su
V
V
IH
CLK
1.5 V
1.5 V
IL
t
w
†
‡
This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.
This is the setup time for input or feedback.
Figure 3. Power-Up Reset Waveforms
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas Instruments
programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI
distributor, or by calling Texas Instruments at (214) 997-5666.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
13
TIBPAL22V10AM is Not Recommended For New Designs
TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM
HIGH-PERFORMANCE IMPACTꢀ™ PROGRAMMABLE ARRAY LOGIC CIRCUITS
SRPS024A − OCTOBER 1986 − REVISED APRIL 2010
PARAMETER MEASUREMENT INFORMATION
5 V
S1
R1
From Output
Under Test
Test
Point
C
R2
L
(see Note A)
LOAD CIRCUIT FOR
3-STATE OUTPUTS
(3.5 V) [3 V]
(0.3 V) [0]
High-Level
Pulse
(3.5 V) [3 V]
(0.3 V) [0]
1.5 V 1.5 V
Timing
Input
1.5 V
t
w
t
h
t
su
(3.5 V) [3 V]
(0.3 V) [0]
(3.5 V) [3 V]
(0.3 V) [0]
Data
Input
Low-Level
Pulse
1.5 V
1.5 V 1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
(3.5 V) [3 V]
(0.3 V) [0]
Output
Control
(3.5 V) [3 V]
(0.3 V) [0]
1.5 V
1.5 V
(low−level
1.5 V
1.5 V
Input
enabling)
t
en
t
pd
t
t
t
dis
pd
pd
V
OH
In-Phase
Output
≈ 3.3 V
+0.5 V
1.5 V
1.5 V
1.5 V
Waveform 1
S1 Closed
(see Note B)
1.5 V
V
OL
V
OL
V
OL
t
pd
t
dis
V
OH
t
en
Out-of-Phase
Output
(see Note D)
1.5 V
V
OH
Waveform 2
S1 Open
(see Note B)
V
OL
1.5 V
V
−0.5 V
OH
≈ 0 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. C includes probe and jig capacitance and is 50 pF for t and t , 5 pF for t
.
dis
L
pd
en
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: For C suffix, use the voltage levels indicated in parentheses ( ). PRR ≤ 1 MHz,
t = t ≤ 2 ns, duty cycle = 50%. For M suffix, use the voltage levels indicated in brackets [ ]. PRR ≤ 10 MHz, t and t ≤ 2 ns,
r
f
r
f
duty cycle = 50%.
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
Figure 4. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
14
PACKAGE OPTION ADDENDUM
www.ti.com
16-Jul-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
5962-86053013A
NRND
LCCC
FK
28
1
TBD
Call TI
Call TI
-55 to 125
5962-
86053013A
TIBPAL22
V10AMFKB
5962-8605301KA
5962-8605301LA
NRND
NRND
CFP
W
24
24
1
1
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-55 to 125
-55 to 125
5962-8605301KA
TIBPAL22V10AMW
B
CDIP
JT
5962-8605301LA
TIBPAL22V10AMJ
TB
TIBPAL22V10ACFN
TIBPAL22V10ACNT
ACTIVE
ACTIVE
PLCC
PDIP
FN
NT
28
24
37
15
CU
Level-1-220C-UNLIM
N / A for Pkg Type
0 to 75
0 to 75
22V10ACFN
Pb-Free
(RoHS)
CU NIPDAU
TIBPAL22V10ACN
T
TIBPAL22V10AMFKB
NRND
LCCC
FK
28
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
5962-
86053013A
TIBPAL22
V10AMFKB
TIBPAL22V10AMJT
TIBPAL22V10AMJTB
NRND
NRND
CDIP
CDIP
JT
JT
24
24
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
TIBPAL22V10AMJ
T
5962-8605301LA
TIBPAL22V10AMJ
TB
TIBPAL22V10AMWB
NRND
CFP
W
24
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8605301KA
TIBPAL22V10AMW
B
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Jul-2013
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MCER004A – JANUARY 1995 – REVISED JANUARY 1997
JT (R-GDIP-T**)
CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
PINS **
A
24
28
DIM
13
24
1.280
(32,51) (37,08)
1.460
A MAX
1.240
(31,50) (36,58)
1.440
B
A MIN
B MAX
B MIN
0.300
(7,62)
0.291
(7,39)
1
12
0.070 (1,78)
0.030 (0,76)
0.245
(6,22)
0.285
(7,24)
0.320 (8,13)
0.290 (7,37)
0.015 (0,38) MIN
0.100 (2,54) MAX
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.014 (0,36)
0.008 (0,20)
0.100 (2,54)
4040110/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MCFP007 – OCTOBER 1994
W (R-GDFP-F24)
CERAMIC DUAL FLATPACK
0.375 (9,53)
0.340 (8,64)
Base and Seating Plane
0.006 (0,15)
0.004 (0,10)
0.045 (1,14)
0.026 (0,66)
0.090 (2,29)
0.045 (1,14)
0.395 (10,03)
0.360 (9,14)
0.360 (9,14)
0.240 (6,10)
0.360 (9,14)
0.240 (6,10)
0.019 (0,48)
0.015 (0,38)
1
24
0.050 (1,27)
0.640 (16,26)
0.490 (12,45)
0.030 (0,76)
0.015 (0,38)
12
13
30° TYP
1.115 (28,32)
0.840 (21,34)
4040180-5/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD
E. Index point is provided on cap for terminal identification only.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPLC004A – OCTOBER 1994
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
D
0.090 (2,29)
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
18
D2/E2
D2/E2
E
E1
8
14
0.021 (0,53)
0.013 (0,33)
0.050 (1,27)
9
13
0.007 (0,18)
M
0.008 (0,20) NOM
D/E
D1/E1
D2/E2
NO. OF
PINS
**
MIN
0.385 (9,78)
MAX
MIN
MAX
MIN
MAX
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.191 (4,85)
0.291 (7,39)
0.341 (8,66)
0.169 (4,29)
0.219 (5,56)
0.319 (8,10)
0.369 (9,37)
20
28
44
52
68
84
0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)
0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)
0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)
0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)
1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)
4040005/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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