THS6302 [TI]
双端口 G.Fast 和 G.mgFast DSL 线路驱动器;
| 型号： | THS6302 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双端口 G.Fast 和 G.mgFast DSL 线路驱动器 驱动 驱动器 |
| 文件： | 总29页 (文件大小：1691K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THS6302
ZHCSNF4A – JUNE 2016 – REVISED FEBRUARY 2021
THS6302 双端口、G.Fast 和 G.mgFast DSL 线路驱动器
1 特性
3 说明
•
•
•
•
专为 G.Fast 106MHz、212MHz DSL 模式而设计
兼容 G.mgFast 424MHz
支持传统 VDSL 和 ADSL2+ 应用
适用于 G.Fast 和传统应用的出色 MTPR（线路功
率 = 8dBm）：
THS6302 是一款采用电流反馈架构的双端口差分线路
驱动器，专为 G.Fast 和各种数字用户线路 (DSL) 系统
而设计。该器件适用于 G.Fast 数字用户线路系统，这
些系统支持本地离散多音调制 (DMT) 信号并支持带宽
高达 212MHz 的 8dBm 线路功率，具有出色的线性特
性。
– ADSL2+ = 75dB
– VDSL-17a = 74dB
– VDSL-30a = 70dB
该器件的独特架构可实现超小的静态电流，同时仍然实
现超高线性度。对于并不需要该放大器全部性能的线路
驱动模式，该器件的内在偏置设置可提供更高的节能效
果。为了进一步提高灵活性并节省更多电力，可以通过
连接到一个器件引脚的外部偏置电阻器来调节两个端口
的总静态电流。该器件还具有两种线路端接模式，以便
在非常低的功耗下保持阻抗匹配。
– G.Fast 106MHz = 60dB
– G.Fast 212MHz = 48dB
多种电源模式可适应不同外形
可通过外部电阻器调节偏置电流
差分增益：11V/V
•
•
•
•
•
•
线性输出电流：80mA（最小值）
低功率线路端接模式：<7mA
掉电模式
THS6302 是适用于 DSL 系统中 CO（局端）应用的双
端口器件，类似于适用于 CPE（客户驻地设备）DSL
应用的单端口 THS6301 器件。
• 12V 技术支持高功率输出
– 12.6V 最大工作电压
THS6302 器件采用 4mm x 5mm 28 引脚 VQFN 封
装。
2 应用
器件信息(1)
• G.Fast 和传统 DSL 线路驱动器
•
•
封装尺寸（标称值）
器件型号
THS6302
封装
VQFN (28)
兼容 G.mgFast 的线路驱动器
通用宽带线路驱动器
4.00mm × 5.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
-40
-45
-50
-55
-60
-65
-70
Channel A
Channel B
1M 25M 50M 75M 100M 125M 150M 175M 200M 225M
Frequency (Hz)
D001
多音功率比 (MTPR) 模式（G.Fast，212MHz，8dBm）
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS746
THS6302
www.ti.com.cn
ZHCSNF4A – JUNE 2016 – REVISED FEBRUARY 2021
Table of Contents
7.4 Device Functional Modes..........................................15
7.5 Programming............................................................ 16
8 Application and Implementation..................................17
8.1 Application Information............................................. 17
8.2 Typical Application.................................................... 17
9 Power Supply Recommendations................................19
10 Layout...........................................................................20
10.1 Layout Guidelines................................................... 20
10.2 Layout Example...................................................... 20
11 Device and Documentation Support..........................21
11.1 接收文档更新通知................................................... 21
11.2 支持资源..................................................................21
11.3 Trademarks............................................................. 21
11.4 静电放电警告...........................................................21
11.5 术语表..................................................................... 21
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics............................................7
6.7 Typical Characteristics................................................8
7 Detailed Description......................................................14
7.1 Overview...................................................................14
7.2 Functional Block Diagram.........................................14
7.3 Feature Description...................................................15
Information.................................................................... 21
4 Revision History
Changes from Revision * (June 2016) to Revision A (February 2021)
Page
•
首次公开发布量产数据表.................................................................................................................................... 1
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ZHCSNF4A – JUNE 2016 – REVISED FEBRUARY 2021
5 Pin Configuration and Functions
IREF
INA+
INAœ
GND
GND
INBœ
INB+
NC
1
2
3
4
5
6
7
8
22
21
20
19
18
17
16
15
NC
GND
VS
VS
Thermal
Pad
VS
GND
VS
NC
Not to scale
图 5-1. RHF Package 28-Pin VQFN Top View
表 5-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
IREF
NO.
1
Bias current reference pin
Positive input for channel A
Negative input for channel A
Positive input for channel B
Negative input for channel B
Positive output for channel A
Negative output for channel A
Positive output for channel B
Negative output for channel B
Most significant bit (MSB) of channel A
Least significant bit (LSB) of channel A
MSB of channel B
—
INA+
2
I
3
I
I
INA–
INB+
7
6
I
INB–
OUTA+
OUTA–
OUTB+
OUTB–
M11
27
25
10
12
28
26
9
O
O
O
O
I
M12
I
M21
I
M22
11
I
LSB of channel B
VS
16, 18, 19, 20
4, 5, 17, 21
Positive supply voltage connection
Ground
—
—
GND
8, 13, 14, 15,
22, 23, 24
NC
Not connected
—
—
Thermal pad
Device thermal pad, connected to ground
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
.
MIN
MAX
13.2
5.5
UNIT
Supply voltage
VS pin to GND (all modes)
M11, M12, M21, M22
V
V
V
Digital inputs to GND
Analog inputs to GND
Continuous power dissipation
Storage temperature, Tstg
–0.3
–0.3
12
VINA+, VINA–, VINB+, VINB–
See 节 6.4
150
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted).
MIN
11.4
–40
–40
NOM
MAX
UNIT
Power-supply voltage range
Operating junction temperature
Operating ambient temperature
12
12.6
125
85
V
TJ
°C
°C
TA
6.4 Thermal Information
THS6302
THERMAL METRIC(1)
RHF (VQFN)
UNIT
28 PINS
35
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
27
6.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJT
6.6
ψJB
RθJC(bot)
2.4
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
At TA = 25°C, VS pin = 12 V, GND = 0 V, gain = 11 V/V, 100-Ω load, RSERIES = 47.5 Ω, RIREF = 75 kΩ, CIREF = 100 pF,
G.Fast 106-MHz bias mode, PAR = 15 dB, and output power measured at input of transformer (1:1) with no assumed
transformer insertion losses (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
VOUT = 15 VPP, ADSL2+ bias mode
140
180
VOUT = 15 VPP, VDSL 17a bias mode
LSBW
Large-signal bandwidth
MHz
VOUT = 15 VPP, G.Fast 106-MHz bias mode
VOUT = 15 VPP, G.Fast 212-MHz bias mode
ADSL2+ bias mode, 4 kHz to 2.208 MHz
VDSL2-17a bias mode, 4 kHz to 17.6 MHz
VDSL2-30a bias mode, 4 kHz to 30 MHz
G.Fast 106-MHz bias mode, 4 kHz to 106 MHz
G.Fast 212-MHz bias mode, 4 kHz to 212 MHz
ADSL2+ bias mode, 10%-90% 15-VPP pulse
VDSL2-17a bias mode, 10%-90% 15-VPP pulse
VDSL2-30a bias mode, 10%-90% 15-VPP pulse
220
320
±0.001
±0.02
±0.02
±0.02
±0.2
Gain flatness referenced to
1 MHz
dB
5100
6600
6600
SR
Slew rate
V/µs
G.Fast 106-MHz bias mode,
10%-90% 15-VPP pulse
7400
G.Fast 212-MHz bias mode,
10%-90% 15-VPP pulse
10600
f > 100 kHz, ADSL2+ bias mode
4.3
3.9
3.9
3.7
3.5
f > 100 kHz, VDSL2-17a bias mode
f > 100 kHz, VDSL2-30a bias mode
f > 100 kHz, G.Fast 106-MHz bias mode
f > 100 kHz, G.Fast 212-MHz bias mode
en
Input-referred voltage noise
nV/√ Hz
Noise floor
(line-termination mode)
Output-referred, bias 00 and bias Z0
dBm/ Hz
dB
–152.5
66
66
66
72
72
70
67
58
50
127
92
82
85
75
Line power = 8 dBm, f ≤ 552 kHz
Line power = 8 dBm, f ≤ 1.104 MHz
Line power = 8 dBm, f ≤ 2.208 MHz
Line power = 8 dBm, f ≤ 14 MHz
Line power = 8 dBm, f ≤ 17.6 MHz
Line power = 8 dBm, f ≤ 30 MHz
Line power = 4 dBm, f ≤ 106 MHz
Line power = 8 dBm, f ≤ 106 MHz
Line power = 8 dBm, f ≤ 212 MHz, bias 10
ADSL2+ bias mode
ADSL2+ MTPR
VDSL2-17a MTPR
dB
dB
dB
dB
VDSL2-30a MTPR
G.Fast 106-MHz MTPR
G.Fast 212-MHz MTPR
VDSL2-17a bias mode
Crosstalk
VDSL2-30a bias mode
dB
G.Fast 106-MHz bias mode
G.Fast 212-MHz bias mode
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6.5 Electrical Characteristics (continued)
At TA = 25°C, VS pin = 12 V, GND = 0 V, gain = 11 V/V, 100-Ω load, RSERIES = 47.5 Ω, RIREF = 75 kΩ, CIREF = 100 pF,
G.Fast 106-MHz bias mode, PAR = 15 dB, and output power measured at input of transformer (1:1) with no assumed
transformer insertion losses (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC PERFORMANCE
AV
Differential gain
At dc, no load, all modes
10.5
–100
18
11
11.5
100
V/V
mV
VPP
Differential output offset
Maximum output swing
G.Fast 106-MHz bias mode
Differential, at dc, 200-Ω load at amplifier output
ADSL2+ bias mode, sourcing,
output offset < 20-mV deviation
40
40
80
80
ADSL2+ bias mode, sinking,
output offset < 20-mV deviation
Linear output current
mA
G.Fast 212-MHz bias mode, sourcing,
output offset < 20-mV deviation
G.Fast 212-MHz bias mode, sinking,
output offset < 20-mV deviation
COMMON MODE
Input CM bias voltage
Output CM bias voltage
POWER SUPPLY
5.9
5.9
6.0
6.0
6.1
6.1
V
V
Maximum supply voltage
All modes
12.6
V
PSRR
Power-supply rejection ratio
f = dc
60
dB
ADSL2+ bias mode
14.5
19.5
28.0
23.0
17.8
39.0
9.5
16.5
22.0
32.0
25.5
20.0
44.5
10.5
7.0
VDSL2 bias mode
VDSL2 high-power bias mode
G.Fast 106-MHz bias mode
G.Fast 106-MHz low-power bias mode
G.Fast 212-MHz bias mode
Line-termination high-power mode
Line-termination low-power mode
Power-down bias mode
IQ
Quiescent current per channel
mA
6.3
1.35
219
298
340
525
525
115
77
1.7
ADSL2+ bias mode, line power = 8 dBm
VDSL2 bias mode, bias Z1
G.Fast 106-MHz bias mode, line power = 8 dBm
G.Fast 212-MHz bias mode, line power = 8 dBm
G.Fast 212-MHz bias mode, line power = 7 dBm
Line-termination high-power mode
Line-termination low-power mode
Power-down bias mode
Dynamic power consumption
mW
19
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6.6 Switching Characteristics
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
VIH
VIL
Minimum logic high level
Maximum logic low level
Logic mid range
All digital pins, high
2.3
All digital pins, low
0.6
1.6
V
VMID
VFloat
IIH
All digital pins, driven externally
1.2
1.3
V
Logic self-bias voltage
Logic high-level leakage current
Logic low-level leakage current
All digital pins, floating
1.4
110
–75
64
1.5
V
All digital pins, logic level = 3.6 V
135
µA
µA
IIL
All digital pins, logic level = ground
–95
Line-termination mode (bias 00) to G.Fast 212-MHz mode (bias 10)
Line-termination mode (bias Z0) to G.Fast 212-MHz mode (bias 10)
Power-down mode (bias ZZ) to G.Fast 212-MHz mode (bias 10)
G.Fast 212-MHz mode (bias 10) to line-termination mode (bias 00)
G.Fast 212-MHz mode (bias 10) to line-termination mode (bias Z0)
G.Fast 212-MHz mode (bias 10) to power-down mode (bias ZZ)
Turn-on switching time
Turn-off switching time
50
ns
ns
60
76
400
380
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6.7 Typical Characteristics
At TA = 25 °C, VS pin = 12 V, GND = 0 V, gain = 11 V/V, 100 Ω Load, RSERIES = 47.5 Ω, PAR = 15 dB, and output power
measured at input of transformer (1:1) with no assumed transformer insertion losses (unless otherwise noted).
-40
-45
-50
-55
-60
-65
-70
-45
-50
-55
-60
-65
-70
-75
Channel A
Channel B
Bias10 Ch. A
Bias10 Ch. B
Bias11 Ch. A
Bias11 Ch. B
1M 25M 50M 75M 100M 125M 150M 175M 200M 225M
Frequency (Hz)
1M
20M
40M
60M
Frequency (Hz)
80M
100M
120M
D001
D002
Line power = 8 dBm
Line power = 8 dBm
图 6-2. MTPR G.Fast 106-MHz Mode
图 6-1. MTPR G.Fast 212-MHz Mode
-40
-45
-50
-55
-60
-65
-70
-75
-80
-70
-72
-74
-76
-78
-80
Bias01 Ch. A
Bias01 Ch. B
Bias10 Ch. A
Bias10 Ch. B
Bias11 Ch. A
Bias11 Ch. B
BiasZ1 Ch. A
BiasZ1 Ch. B
Bias1Z Ch. A
Bias1Z Ch. B
1M
20M
40M
60M
Frequency (Hz)
80M
100M
120M
1M
5M
10M
15M 20M
Frequency (Hz)
25M
30M
35M
D003
D004
Line power = 4 dBm
Line power = 8 dBm
图 6-4. MTPR VDSL-30a Mode
图 6-3. MTPR G.Fast 106-MHz Mode
-60
-65
-70
-75
-80
-55
-60
-65
-70
-75
BiasZ1 Ch. A
BiasZ1 Ch. B
Bias1Z Ch. A
Bias1Z Ch. B
Bias0Z Ch. A
Bias0Z Ch. B
Bias01 Ch. A
Bias01 Ch. B
1M
5M
10M
Frequency (Hz)
15M
20M
0.1M
0.5M
1M 1.5M
Frequency (Hz)
2M
2.5M
D005
D006
Line power = 8 dBm
图 6-5. MTPR VDSL-17a Mode
Line power = 8 dBm
图 6-6. MTPR ADSL2+ Mode
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6.7 Typical Characteristics (continued)
At TA = 25 °C, VS pin = 12 V, GND = 0 V, gain = 11 V/V, 100 Ω Load, RSERIES = 47.5 Ω, PAR = 15 dB, and output power
measured at input of transformer (1:1) with no assumed transformer insertion losses (unless otherwise noted).
600
550
500
450
400
350
300
250
200
500
450
400
350
300
250
200
150
106 MHz Bias01
106 MHz Bias11
106 MHz Bias10
212 MHz Bias10
ADSL2 Bias0Z
ADSL2 Bias01
VDSL17a BiasZ1
VDSL17a Bias1Z
VDSL30a BiasZ1
VDSL30a Bias1Z
-10
-8
-6
-4
-2
Tx Power (dBm)
0
2
4
6
8
-10
-8
-6
-4
-2
Tx Power (dBm)
0
2
4
6
8
D007
D008
图 6-7. G.Fast Modes Power Consumption
图 6-8. xDSL Modes Power Consumption
-60
-65
-70
-75
-80
-85
-90
-95
-100
-60
-65
-70
-75
-80
-85
-90
-95
-100
Ch. A-to-B
Ch. B-to-A
Ch. A-to-B
Ch. B-to-A
1M
10M
Frequency (Hz)
100M
1M
10M
Frequency (Hz)
100M
D009
D010
图 6-9. Crosstalk G.Fast 212-MHz Mode
图 6-10. Crosstalk G.Fast 106-MHz Mode
-60
-62
-64
-66
-68
-70
-72
-74
-60
-62
-64
-66
-68
-70
-72
-74
-40° C
0° C
25° C
50° C
85° C
-40° C
0° C
25° C
50° C
85° C
1M
20M
40M
60M
Frequency (Hz)
80M
100M
120M
1M
20M
40M
60M
Frequency (Hz)
80M
100M
120M
D011
D012
G.Fast 106-MHz channel A, line power = 8 dBm
G.Fast 106-MHz channel B, line power = 8 dBm
图 6-11. MTPR vs Temperature
图 6-12. MTPR vs Temperature
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6.7 Typical Characteristics (continued)
At TA = 25 °C, VS pin = 12 V, GND = 0 V, gain = 11 V/V, 100 Ω Load, RSERIES = 47.5 Ω, PAR = 15 dB, and output power
measured at input of transformer (1:1) with no assumed transformer insertion losses (unless otherwise noted).
20
0
20
0
-20
-40
-60
-80
-20
-40
-60
-80
Bias10
Bias0Z
Bias1Z
Bias01
BiasZ1
Bias11
Bias10
Bias0Z
Bias1Z
Bias01
BiasZ1
Bias11
1M
10M
100M
1G
1M
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
D013
D014
图 6-13. Normalized Small-Signal Frequency Response
VOUT = 13 VPP
图 6-14. Normalized Large-Signal Frequency Response
150
-145
Bias00
BiasZ0
125
Bias00 AB
BiasZ0 AB
Bias00 CD
BiasZ0 CD
-146
-147
-148
100
75
50
25
0
-149
-150
-151
-152
-153
-154
-155
10k
100k
1M 10M
Frequency (Hz)
100M
1G
0
50M
100M
150M
Frequency (Hz)
200M
250M
300M
D015
D016
图 6-15. Terminal Modes Output Impedance
图 6-16. Terminal Modes Noise Floor
11.5
11.25
11
2
8.8
8.6
8.4
8.2
8
4.4
4.2
4
Bias10
Bias0Z
Bais1Z
Bias01
BiasZ1
Bias11
Bias10
Bias0Z
Bias1Z
Bias01
BiasZ1
Bias11
1.75
1.5
1.25
1
Sourcing
Sourcing
10.75
10.5
10.25
10
3.8
3.6
3.4
Sinking
Sinking
0.75
0.5
7.8
0
10
20
30
40
50
Current (mA)
60
70
80
90 100
0
10
20
30
40
50
Current (mA)
60
70
80
90 100
D017
D018
Full-scale input
图 6-17. Output Voltage vs Current
Mid-scale input
图 6-18. Output Voltage vs Current
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6.7 Typical Characteristics (continued)
At TA = 25 °C, VS pin = 12 V, GND = 0 V, gain = 11 V/V, 100 Ω Load, RSERIES = 47.5 Ω, PAR = 15 dB, and output power
measured at input of transformer (1:1) with no assumed transformer insertion losses (unless otherwise noted).
6.6
6.4
6.2
6
6.6
6.4
6.2
6
Bias10
Bias0Z
Bias1Z
Bias01
BiasZ1
Bias11
Bias00 Ch. A
Bias00 Ch. B
BiasZ0 Ch. A
BiasZ0 Ch. B
Channel A
5.8
5.6
5.4
5.2
5.8
5.6
5.4
Channel B
-100 -80 -60 -40 -20
0
20
Output Current (mA)
40
60
80 100
-100 -80 -60 -40 -20
0
20
Output Current (mA)
40
60
80 100
D019
D020
Zero input
Terminal modes
图 6-20. Output Voltage vs Current
图 6-19. Output Voltage vs Current
3.5
3
2
3.5
2
Bias Level Signal
Differential Output
Bias Level Signal
Differential Output
1.5
1
3
2.5
2
1.5
1
2.5
2
0.5
0
0.5
0
1.5
1
1.5
1
-0.5
-1
-0.5
-1
0.5
0
0.5
0
-1.5
-1.5
0
20
40
60
80 100 120 140 160 180 200
Time (ns)
0
80 160 240 320 400 480 560 640 720 800
Time (ns)
D021
D022
Bias mode 00 to mode 10
Bias mode Z0 to mode 10
图 6-21. Mode Switching Time
图 6-22. Mode Switching Time
3.5
3
2
44
43
42
41
40
39
38
37
36
35
34
Bias Level Signal
Differential Output
1.5
1
2.5
2
0.5
0
1.5
1
-0.5
-1
0.5
0
-1.5
0
80 160 240 320 400 480 560 640 720 800
Time (ns)
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
Temperature (èC)
D023
D024
Bias mode ZZ to mode 10
10 devices, channels A and B, G.Fast 212-MHz bias (mode
10)
图 6-23. Mode Switching Time
图 6-24. Quiescent Current vs Temperature
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6.7 Typical Characteristics (continued)
At TA = 25 °C, VS pin = 12 V, GND = 0 V, gain = 11 V/V, 100 Ω Load, RSERIES = 47.5 Ω, PAR = 15 dB, and output power
measured at input of transformer (1:1) with no assumed transformer insertion losses (unless otherwise noted).
28
27
26
25
24
23
22
21
20
19
18
24
23
22
21
20
19
18
17
16
15
14
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
Temperature (èC)
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
Temperature (èC)
D025
D026
10 devices, channels A and B, G.Fast 106-MHz bias (mode
11)
10 devices, channels A and B, VDSL bias (mode Z1)
图 6-26. Quiescent Current vs Temperature
图 6-25. Quiescent Current vs Temperature
20
19
18
17
16
15
14
13
12
11
10
14
13
12
11
10
9
8
7
6
5
4
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
Temperature (èC)
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
Temperature (èC)
D027
D028
10 devices, channels A and B, ADSL bias (mode 0Z)
10 devices, channels A and B, line-termination high-power
bias (mode 00)
图 6-27. Quiescent Current vs Temperature
图 6-28. Quiescent Current vs Temperature
10
9
8
7
6
5
4
3
2
1
0
3
2.5
2
1.5
1
0.5
0
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
Temperature (èC)
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
Temperature (èC)
D029
D030
10 devices, channels A and B, line-termination low-power bias
(mode Z0)
10 devices, channels A and B, power-down (mode ZZ)
图 6-30. Quiescent Current vs Temperature
图 6-29. Quiescent Current vs Temperature
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6.7 Typical Characteristics (continued)
At TA = 25 °C, VS pin = 12 V, GND = 0 V, gain = 11 V/V, 100 Ω Load, RSERIES = 47.5 Ω, PAR = 15 dB, and output power
measured at input of transformer (1:1) with no assumed transformer insertion losses (unless otherwise noted).
1250
1000
750
500
250
0
0
10
20
30
40
50
60
D032
Differential Output Offset (mV)
图 6-31. Output Offset Voltage
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7 Detailed Description
7.1 Overview
The THS6302 is a dual-port, current-feedback architecture, differential line driver designed for G.Fast and xDSL
systems. The device is targeted for use in G.Fast digital subscriber line (DSL) systems that enable native
discrete multitone modulation (DMT) signals and supports an 8-dBm line power up to 212 MHz with good
linearity.
The device consists of a unique architecture consisting of two amplifiers per channel in a noninverting
configuration with an internally-fixed gain of 11 V/V. The THS6302 is designed to drive the high-performance
G.Fast 212-MHz DSL profile, but is also backwards-comparable to drive lower frequency profiles. The device
features selectable bias modes for the G.Fast 106-MHz profile, VDSL profiles, and ADSL profiles. These modes
reduce the quiescent current of the device based on the frequency requirements of the various DSL profiles to
maximize power efficiency. Along with adjustable bias modes, the device features two line-termination modes
that maintain an output impedance match with low power consumption. The line-termination modes allow for the
device to be in a low-power state without causing distortion on a shared signal line.
For further flexibility, the THS6302 features an IREF pin that is used to further adjust the quiescent current of the
device. A resistor connected to this pin can be changed to increase or decrease the device current to meet
performance requirements and uses the lowest amount of power possible.
7.2 Functional Block Diagram
THS6302
VINA+
VOUTA+
Channel A
VOUTA-
VINA-
M11, M12
IREF
M21, M22
Bias, Control
VINB+
VOUTB+
Channel B
VOUTB-
VINB-
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7.3 Feature Description
The THS6302 is a dual-channel line driver that has a high current drive and a differential input and output
amplifier in each channel. 图 7-1 shows an example circuit for channel A of the THS6302 configured to drive the
G.Fast 212-MHz DSL profile. The bias control pins (M12 and M11) are set to ground and 3.3 V, respectively, to
put the device in the G.Fast 212-MHz bias mode. This bias optimizes the internal power consumption of the
device to meet performance specifications of the G.Fast 212-MHz profile and can be changed to meet several
different DSL profiles and other modes listed in 表 7-1. The IREF pin is biased with a 75-kΩ (RIREF) resistor that
adjusts the device quiescent current to a nominal state. RIREF can be increased to lower the quiescent current or
deceased to raise the quiescent current of the device for fine-tuning. CIREF provides decoupling for the IREF pin
and is typically 100 pF.
The THS6302 has a 10-kΩ, internally-set differential input impedance and low output impedance. In 图 7-1 the
input impedance is matched to 100 Ω by using a 100-Ω resistor connected differentially across the inputs. This
value can easily be changed by using a different resistor to create the desired impedance at the input.
Remember that the impedance in the device is actually the parallel combination of 10 kΩ and the external input
resistor. For low impedances, this effect is minimal, but must be considered if the matched input impedance is
increased. The output impedance of the THS6302 in 图 7-1 is set by the two RSERIES resistors to match 100 Ω.
The internal output resistance is very low (< 2 Ω per output), so the output impedance is primarily set by the
RSERIES resistors. These resistors can be adjusted to match various output impedance values.
12 V
3.3 V
0.1 mF
½ THS6302
Rseries
47.5 ꢀ
VINA+
VOUTA+
1:1
100-ꢀ
Differential 100 ꢀ
Input
100-ꢀ
Differential
to Line
Channel A
Rseries
47.5 ꢀ
VINA-
IREF
VOUTA-
GND
CIREF
100
pF
(Thermal
Pad)
RIREF
75 kꢀ
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图 7-1. G.Fast 212-MHz Driving Mode Example Circuit
7.4 Device Functional Modes
The THS6302 features nine different device operational modes to accommodate the G.Fast, xDSL, line
termination, and power-down scenarios, as listed in 表 7-1. Each channel of the device is controlled by a 2-pin
parallel interface that uses three-level logic to control the device state. The G.Fast and xDSL modes change the
quiescent current of the device to meet signal performance requirements and maintain the lowest power
possible, which allows for legacy DSL compatibility with maximum power efficiency. The two line-termination
modes maintain a low impedance at the output when placing the device in a low-power state. The line-
termination modes allow for the muxing of multiple devices to one output line by putting the non-driving devices
in a state that does not add distortion to the line. A power-down mode is also included to digitally shut down the
device for the highest level of power savings. 表 7-1 lists the device power modes and the typical quiescent
currents for each mode.
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7.5 Programming
The THS6302 programming is controlled by two pins for each channel. These pins use three-level logic to create
nine different combinations for each pair of pins. The pins have a high state (1) when the pin voltage is greater
than 2.3 V, a low state (0) when the pin voltage is less than 0.6 V, and an open state (Z) where the pin floats at
approximately 1.4 V or can be driven between 1.2 V and 1.6 V. The pins are labeled Mxy where x is the channel
number that the pin is associated with and y is the pin number. 表 7-1 shows the logic combinations for the two
pins and the corresponding power modes.
表 7-1. Bias Modes Truth Table
BIAS CONTROL PINS
BIAS MODE DESCRIPTION
TYPICAL QUIESCENT CURRENT
Mx1
0
Mx2
0
Line termination, high power
Line termination, low power
G.Fast 212 MHz
9.5 mA
6.3 mA
Z
0
1
0
39 mA
0
Z
ADSL2+
14.5 mA
1.35 mA
28.0 mA
17.8 mA
19.5 mA
23.0 mA
Z
Z
Power down
1
Z
Alternate VDSL (high power)
Alternate G.Fast 106 MHz (low power)
VDSL
0
1
Z
1
1
1
G.Fast 106 MHz
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
THS6302 is a dual-port, very-high-bit-rate linear xDSL, G.Fast, and G.mgFast differential line driver where the
device drives a twisted pair cable. The signal is typically generated by a DAC in the DSL ASIC at low signal
swings that is amplified by the G.Fast line driver.
The G.Fast system is ac-coupled when transmitting information above the audio band. On the input of the line
driver, this ac-coupling translates into the series capacitors to isolate the dc voltage coming from the DAC output
common-mode voltage. On the output, a transformer is used to help isolate the 48 V present between the tip and
ring of the telephone line.
The transformer can be set to any useful ratio. In practice, the transformer-turn ratio is set between 1:1 and 1:1.4
for the device. Synthetic impedance at the output of the line driver is common in many xDSL applications.
However, to support high AC performance needed for typical G.Fast and G.mgFast applications, THS6302 is an
internally fixed-gain device and often synthetic impedance configuration is not recommeded to maintain the AC
performance.
Note: the resulting load detected by the amplifier may affect the amplifier linearity or output voltage swing
capabilities.
8.2 Typical Application
图 8-1 shows a typical application circuit for THS6302. Only one channel circuit of THS6302 is shown; the other
channel is often a duplicate of this channel in most applications.
12 V
Digital
Interface
0.1 mF
½ THS6302
Rseries
47.5 ꢀ
VINA+
VOUTA+
1:n
Passive
matching &
filter network
AWG or
DSL ASIC
Secondary
Protection
To Line
Load
100 ꢀ
Channel A
Rseries
47.5 ꢀ
VINA-
IREF
VOUTA-
GND
(Thermal
Pad)
RIREF
75 kꢀ
CIREF
100 pF
图 8-1. Typical G.Fast Line Driver Configuration
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8.2.1 Design Requirements
表 8-1 provides design requirements for a G.Fast line driver, which is met by the THS6302 device.
表 8-1. Design Requirements
PARAMETER
G.Fast, 212-MHz and 106-MHz transmit profile
CONDITION
MTPR information using bias control for line power = 8 dBm and
PAR = 15 dB
Legacy DSL profile support
Supply voltage
Yes
12 V
Input interface
AC coupled
1:1
Output transformer ratio
Surge protection
External as needed
8.2.2 Detailed Design Procedure
The G.Fast signal input to the THS6302 comes from a high-speed DAC in the DSL ASIC whose interleaving
spurs are filtered out using either a 3rd- or 5th-order filter. Digital pre-emphasis can be employed in the DAC
output such that the differential line driver compensates for the transmission line cable losses at long distance
and high frequency. The THS6302 is operated on a 12-V single supply. Resulting from the single-supply
operation, the device input is AC-coupled using a capacitor that blocks any DC current flowing out of the inputs
to the adjacent circuitry. The AC-coupling capacitor forms a high-pass filter with the device input impedance.
This pole must be set at a frequency low enough to not interfere with the desired xDSL or G.Fast signal.
The THS6302 differential outputs usually drive a 1:n output transformer with a transformer turns ratio that can be
changed depending upon the application. The output transformer selected must have low insertion loss in the
desired frequency band in order to maintain good multi-tone power rejection (MTPR) for a given line power. The
load is expected to be a transmission line with 100-Ω characteristic impedance on the primary side (line load
side) of the transformer. Referred to the transformer secondary, the load seen by the amplifier is 1/n2 with 1:n
being the transformer turn ratio. Practical limitations force the transformer-turn ratio to be between 1:1 and 1:1.6.
At the lighter load seen by the amplifier (1:1), the voltage swing is limited by the class AB output stage and the
maximum achievable swing of the amplifier. At the heaviest load (1:1.6), the voltage swing is limited by the
current drive capability of the amplifier.
For surge protection, consider adding a gas discharge tube (GDT) on the primary side of the output transformer.
The gas discharge tube is required to shunt the large current that could flow through the cables during lightning
surge, and protect the device outputs. The secondary protection is also normally added after the series
resistance on the secondary transformer side. The secondary protection could be in the form of back to back
switching diodes, which also help limit the residual surge current flowing into the device outputs.
For the power-supply bypass, consider using X7R or X5R because of the better stability of these materials over
temperature.
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8.2.3 Application Performance Plots
图 8-2 and 图 8-3 show the MTPR results for 212-MHz and 106-MHz G.Fast profiles, respectivley.
-40
-45
-50
-55
-60
-65
-70
-45
-50
-55
-60
-65
-70
-75
Channel A
Channel B
Bias10 Ch. A
Bias10 Ch. B
Bias11 Ch. A
Bias11 Ch. B
1M 25M 50M 75M 100M 125M 150M 175M 200M 225M
Frequency (Hz)
1M
20M
40M
60M
Frequency (Hz)
80M
100M
120M
D001
D002
1-in-64 missing tones
1-in-64 missing tones
图 8-2. MTPR G.Fast 212-MHz
图 8-3. MTPR G.Fast 106-MHz
9 Power Supply Recommendations
The THS6302 is recommended to operate using a total supply voltage of 12 V. If a lower or higher supply
voltage is required, select one that is between 11.4 V and 12.6 V for optimal performance. Use supply
decoupling capacitors on the power-supply pins to minimize distortion caused by parasitic signals on the power
supply. This usage is especially important in applications where many devices share a single power-supply bus.
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10 Layout
10.1 Layout Guidelines
Achieving optimum performance with a high-frequency amplifier such as the THS6302 requires careful attention
to board layout parasitics and external component types. Recommendations that optimize performance include:
1. Minimize parasitic capacitance to any ac ground for all signal I/O pins. Excessive parasitic capacitance on
the input pin can cause instability. In the line driver application, the parasitic capacitance forms a pole with
the load detected by the amplifier and can reduce the effective bandwidth of the application circuit, thus
leading to degraded performance. To reduce unwanted capacitance, open a window around the signal I/O
pins in all ground and power planes around those pins. Otherwise, make sure that ground and power planes
are unbroken elsewhere on the board.
2. Minimize the distance (< 0.25 in.) from the power-supply pins to high-frequency 0.1-µF decoupling
capacitors. At the device pins, make sure that the ground and power-plane layout are not in close proximity
to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and
decoupling capacitors. Always decouple the power-supply connections with these capacitors.
3. Careful selection and placement of external components preserves the high-frequency performance of the
device. Use very-low reactance-type resistors. Surface-mount resistors function best and allow a tighter
overall layout. Metal-film or carbon composition, axially-leaded resistors also provide good high-frequency
performance. Again, keep the leads and printed circuit board traces as short as possible. Never use wire-
wound type resistors in a high-frequency application.
4. Connections to other wideband devices on the board can be made with short, direct traces or through
onboard transmission lines. For short connections, consider the trace and the input to the next device as a
lumped capacitive load. Use relatively wide traces (50 mils to 100 mils), preferably with ground and power
planes opened up around them.
5. Do not socket a high-speed part such as the THS6302. The additional lead length and pin-to-pin capacitance
introduced by the socket can create an extremely troublesome parasitic network that makes achieving a
smooth, stable frequency response almost impossible. Best results are obtained by soldering the device
onto the board.
10.2 Layout Example
Channel A
Outputs
Thermal
Pad
Differential
Inputs
Decoupling
Capacitors
Channel B
Outputs
图 10-1. Example Layout
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11 Device and Documentation Support
11.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.4 静电放电警告
静电放电 (ESD) 会损坏这个集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
THS6302IRHFR
ACTIVE
VQFN
RHF
28
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
THS6302
IRHF
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
THS6302IRHFR
VQFN
RHF
28
3000
330.0
12.4
4.3
5.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VQFN RHF 28
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 33.0
THS6302IRHFR
3000
Pack Materials-Page 2
PACKAGE OUTLINE
RHF0028A
VQFN - 1.0 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
B
A
PIN 1 INDEX AREA
0.5
0.3
5.1
4.9
0.30
0.18
DETAIL
OPTIONAL TERMINAL
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2.55 0.1
2X 2.5
(0.2) TYP
9
EXPOSED
14
THERMAL PAD
24X 0.5
15
8
3.55 0.1
2X
29
SYMM
3.5
SEE TERMINAL
DETAIL
1
22
0.30
0.18
28X
0.1
C A B
PIN 1 ID
(OPTIONAL)
28
23
SYMM
0.05
0.5
0.3
28X
4220383/A 11/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RHF0028A
VQFN - 1.0 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.55)
SYMM
28
23
28X (0.6)
22
1
28X (0.24)
(3.55)
(1.525)
24X (0.5)
29
SYMM
(4.8)
(
0.2) TYP
VIA
8
15
(R0.05)
TYP
9
14
(1.025)
(3.8)
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4220383/A 11/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RHF0028A
VQFN - 1.0 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X (1.13)
(0.665) TYP
23
28
28X (0.6)
1
22
28X (0.24)
(0.865)
TYP
24X (0.5)
SYMM
(4.8)
29
4X (1.53)
(R0.05) TYP
8
15
METAL
TYP
14
9
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 29
76% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4220383/A 11/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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