THS3125IDG4 [TI]
2 CHANNEL, VIDEO AMPLIFIER, PDSO14, GREEN, PLASTIC, SOIC-14;
| 型号： | THS3125IDG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2 CHANNEL, VIDEO AMPLIFIER, PDSO14, GREEN, PLASTIC, SOIC-14 放大器 光电二极管 商用集成电路 |
| 文件： | 总34页 (文件大小：1320K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THS3122
THS3125
www.ti.com
SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
LOW-NOISE, HIGH-SPEED, 450-mA CURRENT FEEDBACK AMPLIFIERS
Check for Samples: THS3122, THS3125
1
FEATURES
APPLICATIONS
•
•
•
•
•
Video Distribution
Instrumentation
Line Drivers
Motor Drivers
Piezo Drivers
23
•
Low Noise:
–
–
–
–
–
2.9-pA/√Hz Noninverting Current Noise
10.8-pA/√Hz Inverting Current Noise
2.2-nV/√Hz Voltage Noise
128-MHz , –3-dB BW (RL = 50 Ω, RF = 470 Ω)
1550-V/µs Slew Rate (G = 2, RL= 50Ω )
DESCRIPTION
•
High Output Current: 450 mA
High Speed:
The THS3122/5 are low-noise, high-speed current
feedback amplifiers, with high output current drive.
This makes them ideal for any application that
requires low distortion over a wide frequency with
heavy loads. The THS3122/5 can drive four
serially-terminated video lines while maintaining a
differential gain error less than 0.03%.
•
–
–
–
–
128-MHz , –3-dB BW (RL = 50 Ω, RF = 470 Ω)
1550-V/µs Slew Rate (G = 2, RL= 50Ω )
26-VPP Output Voltage, RL= 50 Ω
–80 dBc (1 MHz, 2 VPP, G = 2)
•
•
Wide Output Swing:
The high output drive capability of the THS3122/5
enables the devices to drive 50-Ω loads with low
distortion over a wide range of output voltages:
–
–
–
26-VPP Output Voltage, RL= 50 Ω
–80 dBc (1 MHz, 2 VPP, G = 2)
370-µA Shutdown Supply Current
•
•
–80-dBc THD at 2 VPP
-75-dBc THD at 8 VPP
Low Distortion:
The THS3122/5 can operate from ±5-V to ±15-V
supply voltages while drawing as little as 7.2 mA of
supply current per channel. The THS3125 offers a
low-power shutdown mode, reducing the supply
current to only 370 µA. The THS3122/5 are packaged
in a standard SOIC, SOIC PowerPAD™, and TSSOP
PowerPAD packages.
–
–
–80 dBc (1 MHz, 2 VPP, G = 2)
370-µA Shutdown Supply Current
•
•
Low-Power Shutdown Mode (THS3125)
370-µA Shutdown Supply Current
–
Standard SOIC, SOIC PowerPAD™, and
TSSOP PowerPAD Packages
VOLTAGE NOISE AND CURRENT NOISE
vs
FREQUENCY
THS3122
SOIC (D) AND
SOIC PowerPAD? (DDA) PACKAGE
THS3125
SOIC (D) AND
TSSOP PowerPAD? (PWP) PACKAGE
(TOP VIEW)
100
VCC
= 5 V to 15 V
(TOP VIEW)
TA = +25°C
I
n−
1 OUT
1 IN−
1 IN+
V
CC+
1
2
3
4
8
7
6
5
1 OUT
1 IN−
1 IN+
V
CC+
1
2
3
4
5
6
7
14
2 OUT
2 IN−
2 IN+
13 2 OUT
12 2 IN−
11 2 IN+
10 N/C
I
n+
10
V
CC−
V
CC−
N/C
REF
N/C
V
n
9
8
SHUTDOWN
N/C
1
0.01
0.1
1
10
100
f − Frequency − kHz
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
© 2001–2011, Texas Instruments Incorporated
THS3122
THS3125
SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
AVAILABLE OPTIONS(1)
PACKAGED DEVICE
EVALUATION
TA
SOIC-8
(D)
SOIC-8 PowerPAD
(DDA)
SOIC-14
(D)
TSSOP-14
(PWP)
MODULES
0°C to +70°C
40°C to +85°C
THS3122CD
THS3122ID
THS3122CDDA
THS3122IDDA
THS3125CD
THS3125ID
THS3125CPWP
THS3125IPWP
THS3122EVM
THS3125EVM
(1) For the most current specification and package information, refer to the Package Option Addendum located at the end of this data sheet
or see the TI web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature (unless otherwise noted).
UNIT
Supply voltage, VCC+ to VCC–
33 V
±VCC
Input voltage
(2)
Output current (see
)
550 mA
Differential input voltage
±4 V
Maximum junction temperature
+150°C
Total power dissipation at (or below) +25°C free-air temperature
See Dissipation Ratings Table
0°C to +70°C
–40°C to +85°C
–65°C to +125°C
–65°C to +125°C
Commercial
Operating free-air temperature, TA
Industrial
Commercial
Storage temperature, Tstg
Industrial
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The THS3122 and THS3125 may incorporate a PowerPAD™ on the underside of the chip. This pad acts as a heatsink and must be
connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction
temperature which could permanently damage the device. See TI Technical Brief SLMA002 for more information about utilizing the
PowerPAD™ thermally-enhanced package.
DISSIPATION RATING TABLE
TA = +25°C
POWER RATING
PACKAGE
θJA
D-8
DDA
D-14
PWP
95°C/W(1)
67°C/W
66.6°C/W(1)
1.32 W
1.87 W
1.88 W
37.5°C/W
3.3 W
(1) These data were taken using the JEDEC proposed high-K test PCB.
For the JEDEC low-K test PCB, the θJA is 168°C/W for the D-8
package and 122.3°C/W for the D-14 package.
2
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© 2001–2011, Texas Instruments Incorporated
Product Folder Link(s): THS3122 THS3125
THS3122
THS3125
www.ti.com
SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX UNIT
Dual supply
±5
10
±15
V
Supply voltage, VCC+ to VCC–
Single supply
C-suffix
30
0
+70
°C
Operating free-air temperature, TA
I-suffix
–40
+85
ELECTRICAL CHARACTERISTICS
Over operating free-air temperature range, TA = +25°C, VCC = ±15 V, RF = 750 Ω, and RL = 100 Ω (unless otherwise noted).
DYNAMIC PERFORMANCE
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
VCC = ±5 V
VCC= ±15 V
VCC = ±5 V
VCC= ±15 V
VCC = ±5 V
VCC= ±15 V
VCC = ±5 V
VCC= ±15 V
VCC = ±15 V
VCC = ±5 V
VCC= ±15 V
VCC = ±5 V
VCC = ±15 V
138
160
126
128
20
RL = 50Ω
RF = 50 Ω, G = 1
Small-signal bandwidth (–3 dB)
RF = 470 Ω, G =
2
RL = 50 Ω
RF = 470 Ω, G = 2
G = -1
MHz
BW
Bandwidth (0.1 dB)
30
VO(PP) = 4 V
VO(pp)= 20 V
VO= 10 VPP
47
Full power bandwidth
MHz
V/µs
ns
64
1550
500
1000
53
SR
ts
Slew rate(1), G = 8
G = 2, RF = 680Ω
VO = 5 VPP
VO = 2 VPP
VO= 5 VPP
Settling time to 0.1%
G = -1
64
(1) Slew rate is defined from the 25% to the 75% output levels.
NOISE/DISTORTION PERFORMANCE
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
–80
UNIT
VO(PP) = 2 V
VO(PP) = 8 V
VO(PP)= 2 V
VO(PP)= 5 V
f = 10 kHz
G = 2, RF = 470 Ω, VCC= ±15 V,
f = 1 MHz
–75
THD
Total harmonic distortion
Input voltage noise
dBc
–77
G = 2, RF = 470 Ω, VCC= ±5 V,
f = 1 MHz
–76
Vn
In
VCC = ±5 V, ±15 V
VCC = ±5 V, ±15 V
2.2
nV/√Hz
pA/√Hz
Noninverting Input
Inverting Input
2.9
Input current noise
Crosstalk
f = 10 kHz
10.8
–67
VCC = ±5 V
VCC= ±15 V
VCC = ±5 V
VCC= ±15 V
VCC = ±5 V
VCC= ±15 V
G = 2, f = 1 MHz, VO = 2 VPP
dBc
%
–67
0.01
0.01
0.011
0.011
G = 2, RL = 150 Ω
40 IRE modulation
±100 IRE Ramp
NTSC and PAL
Differential gain error
Differential phase error
degrees
© 2001–2011, Texas Instruments Incorporated
Submit Documentation Feedback
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Product Folder Link(s): THS3122 THS3125
THS3122
THS3125
SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Over operating free-air temperature range, TA = +25°C, VCC = ±15 V, RF = 750 Ω, and RL = 100 Ω (unless otherwise noted).
DC PERFORMANCE
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
mV
TA = +25°C
6
10
13
3
Input offset voltage
TA = full range
TA = +25°C
VIC = 0 V, VO = 0 V,
VCC = ±5 V, VCC = ±15 V
VIO
1
Channel offset voltage matching
Offset drift
TA = full range
TA = full range
TA = +25°C
4
10
6
µV/°C
µA
23
30
2
IN- Input bias current
TA = full range
TA = +25°C
VIC = 0 V, VO = 0 V,
VCC = ±5 V, VCC = ±15 V
IIB
0.33
5.4
1
IN+ Input bias current
TA = full range
TA = +25°C
3
22
30
VIC = 0 V, VO = 0 V,
VCC = ±5 V, VCC = ±15 V
IIO
Input offset current
µA
TA = full range
RL = 1 kΩ
ZOL
Open-loop transimpedance
VCC = ±5 V, VCC = ±15 V
MΩ
INPUT CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN TYP
±2.5 ±2.7
±12. ±12.
MAX
UNIT
VCC = ±5 V
VCC= ±15 V
VICR
Input common-mode voltage range
TA = full range
V
5
58
56
63
60
7
TA = +25°C
62
VCC = ±5 V,
VI = -2.5 V to 2.5 V
TA = full range
TA = +25°C
CMRR
Common-mode rejection ratio
dB
67
VCC = ±15 V,
VI = –12.5 V to 12.5 V
TA = full range
IN+
1.5
15
2
MΩ
Ω
RI
CI
Input resistance
IN–
Input capacitance
pF
OUTPUT CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
TYP
4.1
4
MAX UNIT
G = 4,
G = 4,
G = 4,
G = 4,
VI = 1.06 V, VCC = ±5 V
VI = 1.025 V, VCC= ±5 V,
VI = 3.6 V, VCC= ±15 V,
RL = 1 kΩ
RL = 50Ω
RL = 1 kΩ
TA = +25°C
TA = +25°C
V
3.8
3.7
TA = full
range
V
VO
Output voltage swing
TA = +25°C
TA = +25°C
14.2
13.3
12
11.5
200
360
VI = 3.325 V, VCC= ±15 V, RL = 50Ω
V
TA = full
range
G = 4,
VI = 1.025 V, VCC= ±5 V,
RL = 10 Ω
RL = 25 Ω
TA = +25°C
TA = +25°C
TA = +25°C
280
440
14
mA
mA
Ω
IO
ro
Output current drive
Output resistance
VI = 3.325 V, VCC = ±15
G = 4,
V,
Open loop
4
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© 2001–2011, Texas Instruments Incorporated
Product Folder Link(s): THS3122 THS3125
THS3122
THS3125
www.ti.com
SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
ELECTRICAL CHARACTERISTICS (continued)
Over operating free-air temperature range, TA = +25°C, VCC = ±15 V, RF = 750 Ω, and RL = 100 Ω (unless otherwise noted).
POWER SUPPLY
PARAMETER
TEST CONDITIONS
TA = +25°C
MIN
TYP
MAX
9
UNIT
7.2
VCC = ±5 V
TA = full range
TA = +25°C
10
ICC
Quiescent current (per channel)
mA
8.4
60
69
10.5
11.5
VCC = ±15 V
TA = full range
TA = +25°C
53
50
60
55
VCC = ±5 V ±1 V
VCC = ±15 V ±1 V
TA = full range
TA = +25°C
PSRR
Power-supply rejection ratio
dB
TA = full range
SHUTDOWN CHARACTERISTICS (THS3125 Only)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Shutdown quiescent current (per
ICC(SHDN)
channel)
VSHDN = 3.3 V
370
500
µA
(1)
tDIS
Disable time
500
200
18
µs
µs
µA
µA
V
REF = 0 V,
VCC= ±5 V to ±15 V
tEN
Enable time(1)
IIL(SHDN)
IIH(SHDN)
VREF
Shutdown pin low level leakage current
Shutdown pin high level leakage current
REF pin voltage level
VSHDN = 0 V
25
130
VSHDN = 3.3 V
110
VCC–
V
CC+ –4
Enable
Disable
REF+0.8
VSHDN
SHUTDOWN pin voltage level
V
REF+2
(1) Disable/enable time is defined as the time from when the shutdown signal is applied to the SHDN pin to when the supply current has
reached half of its final value.
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
Small-signal closed-loop gain
Small- and large-signal output
vs Frequency
Figure 1 to Figure 10
Figure 11, Figure 12
Figure 13 to Figure 15
Figure 16, Figure 17
Figure 18
vs Frequency
vs Frequency
Harmonic distortion
vs Peak-to-peak output voltage
vs Frequency
Vn, In
Voltage noise and current noise
Common-mode rejection ratio
Crosstalk
CMRR
vs Frequency
Figure 19
vs Frequency
Figure 20
Zo
Output impedance
Slew rate
vs Frequency
Figure 21
SR
vs Output voltage step
vs Free-air temperature
vs Common-mode input voltage
vs Free-air temperature
vs Load current
Figure 22
Figure 24
VIO
Input offset voltage
Figure 24
IB
Input bias current
Output voltage
Figure 25
VO
Figure 26
vs Free-air temperature
vs Supply voltage
Figure 27
Quiescent current
Figure 28
ICC
Shutdown supply current
Differential gain and phase error
Shutdown response
vs Free-air temperature
vs 75-Ω serially terminated loads
Figure 29
Figure 30, Figure 31
Figure 32
Small-signal pulse response
Large-signal pulse response
Figure 33, Figure 34
Figure 35, Figure 36
© 2001–2011, Texas Instruments Incorporated
Submit Documentation Feedback
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Product Folder Link(s): THS3122 THS3125
THS3122
THS3125
SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
www.ti.com
TYPICAL CHARACTERISTICS
SMALL-SIGNAL CLOSED-LOOP
GAIN
SMALL-SIGNAL CLOSED-LOOP
GAIN
SMALL-SIGNAL CLOSED-LOOP
GAIN
vs
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
2
1
6
3
3
R
= 330 Ω
F
R
= 470 Ω
F
0
R
= 680 Ω
= 500 Ω
0
−3
F
R
F
= 680 Ω
= 500 Ω
0
−3
R
−6
−9
F
R
= 750 Ω
= 560 Ω
F
−6
R
F
R
F
= 330 Ω
−1
−9
R
F
−12
−15
−18
−21
−24
−27
−30
−2
−3
−4
−5
−6
−12
−15
−18
−21
−24
−27
−30
G = −1,
= ±15 V,
G = 1,
V = ±5 V,
CC
G = −1,
= ±5 V,
V
V
CC
CC
R
L
= 50 Ω
R
L
= 50 Ω
R
L
= 50 Ω
0.1
1
10
100
1000
0.1
1
10
100
1000
0.1
1
10
100
1000
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 1.
Figure 2.
Figure 3.
SMALL-SIGNAL CLOSED-LOOP
GAIN
SMALL-SIGNAL CLOSED-LOOP
GAIN
SMALL-SIGNAL CLOSED-LOOP
GAIN
vs
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
9
6
3
0
9
3
R
F
= 470 Ω
R
F
= 430 Ω
R
F
= 430 Ω
R
= 500 Ω
F
R
= 500 Ω
= 470 Ω
F
R
F
= 560 Ω
R
= 470 Ω
F
3
6
0
−3
−6
−9
−12
R
F
R
F
= 750 Ω
0
−3
−3
−6
G = 2,
= ±15 V,
G = 1,
= ±15 V,
G = 2,
V = ±5 V,
CC
V
V
CC
CC
R
L
= 50 Ω
R
L
= 50 Ω
R
L
= 50 Ω
−6
0.1
1
10
100
1000
0.1
1
10
100
1000
0.1
1
10
100
1000
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 4.
Figure 5.
Figure 6.
SMALL-SIGNAL CLOSED-LOOP
GAIN
SMALL-SIGNAL CLOSED-LOOP
GAIN
SMALL-SIGNAL CLOSED-LOOP
GAIN
vs
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
15
15
12
15
12
9
R
F
= 200 Ω
R
F
= 200 Ω
12
9
R
F
= 200 Ω
9
6
R
F
= 270 Ω
R
F
= 270 Ω
6
6
3
3
3
R
= 390 Ω
R
= 390 Ω
F
F
R
R
= 470 Ω
= 560 Ω
F
0
0
−3
−6
−3
−6
−9
−12
−15
−18
0
F
−3
−9
−12
−15
−18
−6
G = 4,
= ±15 V,
G = 4,
= ±5 V,
V
= ±5 V,
R = 50 Ω
L
V
CC
V
CC
CC
−9
R
L
= 50 Ω
R
L
= 50 Ω
−12
0.1
1
10
100
1000
0.1
1
10
100
1000
0.1
1
10
100
1000
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 7.
Figure 8.
Figure 9.
6
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Product Folder Link(s): THS3122 THS3125
THS3122
THS3125
www.ti.com
SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
TYPICAL CHARACTERISTICS (continued)
SMALL- AND LARGE-SIGNAL
SMALL- AND LARGE-SIGNAL
SMALL-SIGNAL CLOSED-LOOP
GAIN
vs
OUTPUT
vs
OUTPUT
vs
FREQUENCY
FREQUENCY
FREQUENCY
15
18
12
6
18
12
6
G = 2, V = ±5 V,
G = 2, V = ±15 V,
CC
CC
R
= 200 Ω
4 V
PP
4 V
PP
F
R
L
= 680 Ω, R = 50 Ω
R
L
= 680 Ω,R = 50 Ω
12
9
L
L
2 V
1 V
2 V
1 V
PP
PP
PP
PP
PP
PP
R
= 470 Ω
F
6
3
0
0
−6
0.5 V
0.5 V
R
F
= 560 Ω
0
−6
0.25 V
PP
0.25 V
PP
−3
−12
−12
−6
0.125 V
PP
0.125 V
PP
V
R
= ±15 V,
= 50 Ω
−18
−24
CC
−18
−24
−9
L
−12
0.1
10
100
1000
0.1
1
10
100
1000
0.1
1
10
100
1000
1
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 10.
Figure 11.
Figure 12.
HARMONIC DISTORTION
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
0
0
0
−10
−20
−30
−40
−50
G = 2,
G = 2,
G = 2,
−10
−20
−30
−40
−50
−60
−70
−10
−20
−30
−40
−50
−60
−70
−80
V
V
= ±15 V,
V
V
= ±15 V,
CC
= 8 V,
O(PP)
V
V
R
R
= ±5 V,
CC
CC
= 2 V,
= 2 V,
= 470 Ω,
= 50 Ω
O(PP)
O(PP)
3rd Harmonic
R
R
= 470 Ω,
= 50 Ω
R
R
= 470 Ω,
= 50 Ω
F
F
F
2nd Harmonic
L
L
L
3rd Harmonic
5th Harmonic
5th Harmonic
3rd Harmonic
−60
−70
2nd Harmonic
5th Harmonic
2nd Harmonic
−80
−90
−80
4th Harmonic
10
−90
−90
4th Harmonic
10
4th Harmonic
−100
−100
−100
0.1
1
100
0.1
1
10
0.1
1
100
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 13.
Figure 14.
Figure 15.
VOLTAGE NOISE AND CURRENT
NOISE
HARMONIC DISTORTION
vs
HARMONIC DISTORTION
vs
vs
PEAK-TO-PEAK OUTPUT VOLTAGE
PEAK-TO-PEAK OUTPUT VOLTAGE
FREQUENCY
100
0
0
V
T
= ±5 V to ±15 V
= 25°C
G = 2,
CC
G = 2,
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−10
−20
−30
V
= ±15 V,
A
V
= ±5 V,
CC
f = 1 MHz,
CC
f = 1 MHz,
R
R
= 470 Ω,
= 50 Ω
I
n−
R
R
= 470 Ω,
= 50 Ω
F
F
L
L
−40
−50
−60
−70
I
10
n+
5th Harmonic
5th Harmonic
2nd Harmonic
2nd Harmonic
3rd Harmonic
3rd Harmonic
V
n
−80
−90
4th Harmonic
4th Harmonic
2.5 3.5
1
−100
0
0.5
1
1.5
2
3
4
4.5
5
0.01
1
10
0
1
2
3
4
5
6
7
8
9
0.1
100
V
− Peak-to-Peak Output Voltage − V
f − Frequency − kHz
V
− Peak-to-Peak Output Voltage − V
PP
PP
Figure 16.
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
COMMON-MODE REJECTION RATIO
CROSSTALK
OUTPUT IMPEDANCE
vs
FREQUENCY
80
vs
vs
FREQUENCY
FREQUENCY
100
10
0
G = 2,
= ±5 V, ±15 V
V
R
= ±5 V, ±15 V
= 1 kΩ,
CC
−10
V
70
CC
F
V
= ±15 V
CC
R
F
R
L
= 470 Ω,
= 50 Ω,
−20
−30
−40
−50
−60
60
50
40
30
20
V
= ±5 V
CC
1
0.1
G = 2,
= 470 Ω,
= 50 Ω,
= 25°C
R
R
F
L
−70
−80
10
0
T
A
0.01
0.1
1
10
100
1000
0.1
1
10
100
1000
0.1
1
10
100
1000
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 19.
Figure 20.
Figure 21.
SLEW RATE
vs
INPUT OFFSET VOLTAGE
vs
INPUT OFFSET VOLTAGE
vs
OUTPUT VOLTAGE STEP
FREE-AIR TEMPERATURE
COMMON-MODE INPUT VOLTAGE
2
1800
1600
1400
1200
1000
800
600
400
200
0
0
1
V
R
T
A
= ±15 V,
= 100 Ω,
= 25°C
CC
G = 2,
V
V
R
= ±15 V,
= 0 V,
= 100 Ω
CC
CM
1.5
1
L
R
R
= 470 Ω,
= 50 Ω,
= 25°C
F
L
L
2
T
A
V
= ±15 V
0.5
0
CC
3
4
−0.5
−1
5
V
5
= ±5 V
CC
6
7
−1.5
−2
0
1
2
3
4
6
7
8
9
−40
−15
10
35
60
85
10
−15
−10
−5
0
5
10
15
V
− Output Voltage Step − V
T
A
− Free-Air Temperature −° C
V
− Common-Mode Input Voltage − V
O
CM
Figure 22.
Figure 23.
Figure 24.
INPUT BIAS CURRENT
vs
OUTPUT VOLTAGE
vs
QUIESCENT CURRENT
vs
FREE-AIR TEMPERATURE
LOAD CURRENT
FREE-AIR TEMPERATURE
15
14
13
12
11
10
12
10
8
12
10
8
V
= ±15 V, I
V = ±15 V
CC
CC
IB+
V
= ±15 V, I
IB−
CC
6
V
= ±5 V
CC
6
V
= ±5 V, I
IB+
CC
4
4
V
= ±5 V, I
CC
IB−
2
V
R
T
A
= ±15 V,
= 330 Ω,
= 25°C
CC
F
2
0
0
−2
−40
−40
−15
10
35
60
85
0
50 100 150 200 250 300 350 400 450
−15
10
35
60
85
T
A
− Free-Air Temperature − °C
I
− Load Current − mA
T
A
− Free-Air Temperature − °C
L
Figure 25.
Figure 26.
Figure 27.
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TYPICAL CHARACTERISTICS (continued)
QUIESCENT CURRENT
SHUTDOWN SUPPLY CURRENT
vs
vs
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
450
400
350
300
250
200
150
100
12
10
V
R
= 3.3 V
= 750 Ω
SD
85 °C
F
V
= ±15 V
CC
8
6
4
2
0
25 °C
V
= ±5 V
−40 °C
CC
50
0
−40
−15
10
35
60
85
0
2.5
5
7.5
10
12.5
15
T
A
− Free-Air Temperature − °C
V
− Supply Voltage −± V
CC
Figure 28.
Figure 29.
DIFFERENTIAL PHASE AND GAIN ERROR
DIFFERENTIAL PHASE AND GAIN ERROR
vs
vs
75-Ω SERIALLY-TERMINATED LOADS
75-Ω SERIALLY-TERMINATED LOADS
0.3
0.08
0.35
V
= ±5 V,
CC
0.07
0.06
G = 2,
0.3
0.2
0.1
40 IRE Modulation
±100 IRE Ramp
NTSC
0.25
0.2
0.05
0.04
0.03
0.02
Gain Error
0
Phase Error
0.15
0.1
−0.1
V
= ±5 V,
CC
G = 2,
−0.2
−0.3
R
R
= 470 Ω,
= 50 Ω
F
L
0.05
0
0.01
0
1
2
3
4
5
6
7
8
0
100
200
300
400
500
600
75 Ω Serially Terminated Loads
t − Time − ns
Figure 30.
Figure 31.
THS3125
THS3125
SHUTDOWN RESPONSE
SHUTDOWN RESPONSE
5
4
3
2
1
0
0.3
0.2
0.1
0
2
−0.1
1.5
1
V
= ±5 V,
CC
G = 2,
−0.2
−0.3
R
R
= 470 Ω,
= 50 Ω
0.5
0
F
L
0
100
200
300
400
500
600
0
1
2
3
4
5
6
7
8
9
10
t − Time − ns
t − Time − ns
Figure 32.
Figure 33.
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TYPICAL CHARACTERISTICS (continued)
SMALL-SIGNAL PULSE RESPONSE
LARGE-SIGNAL PULSE RESPONSE
LARGE-SIGNAL PULSE RESPONSE
0.3
3
3
2
1
0
0.2
0.1
2
1
0
0
−1
−2
−3
−0.1
−1
−2
−3
V
= ±15 V,
V
= ±15 V,
V
= ±5 V,
CC
G = 2,
CC
G = 2,
CC
G = 2,
−0.2
−0.3
R
R
= 470 Ω,
= 50 Ω
R
R
= 470 Ω,
= 50 Ω
R
R
= 470 Ω,
= 50 Ω
F
L
F
L
F
L
0
100
200
300
400
500
600
0
100
200
300
400
500
600
0
100
200
300
400
500
600
t − Time − ns
t − Time − ns
t − Time − ns
Figure 34.
Figure 35.
Figure 36.
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SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
APPLICATION INFORMATION
Current-feedback amplifiers are highly dependent on
the feedback resistor RF for maximum performance
and stability. Table 1 shows the optimal gain setting
resistors RF and RG at different gains to give
maximum bandwidth with minimal peaking in the
frequency response. Higher bandwidths can be
achieved, at the expense of added peaking in the
frequency response, by using even lower values for
RF. Conversely, increasing RF decreases the
bandwidth, but stability is improved.
Maximum Slew Rate for Repetitive Signals
The THS3125 and THS3122 are recommended for
high slew rate pulsed applications where the internal
nodes of the amplifier have time to stabilize between
pulses. It is recommended to have at least 20-ns
delay between pulses.
The THS3125 and THS3122 are not recommended
for applications with repetitive signals (sine, square,
sawtooth, or other) that exceed 900 V/µs. Using the
part in these applications results in excessive current
draw from the power supply and possible device
damage.
Table 1. Recommended Resistor Values for
Optimum Frequency Response
THS3125 and THS3122 RF and RG VALUES FOR MINIMAL
PEAKING WITH RL = 50 Ω, ±5-V to ±15-V POWER SUPPLY
For applications with high slew rate, repetitive signals,
the THS3091 and THS3095 (single versions), or
THS3092 and THS3096 (dual versions) are
recommended.
GAIN (V/V)
RG (Ω)
—
RF (Ω)
560
1
2
4
470
470
66.5
200
Wideband, Noninverting Operation
The THS3125 and THS3122 are unity gain stable
130-MHz current-feedback operational amplifiers,
designed to operate from a ±5-V to ±15-V power
supply.
Wideband, Inverting Operation
Figure 38 shows the THS3125 in a typical inverting
gain configuration where the input and output
impedances from Figure 37 are retained in an
inverting circuit configuration.
Figure 37 shows the THS3125 in a noninverting gain
of 2-V/V configuration used to generate the typical
characteristic curves. Most of the curves were
characterized using signal sources with 50-Ω source
impedance and with measurement equipment that
presents a 50-Ω load impedance.
+15 V
+VS
+
6.8 mF
0.1 mF
49.9 W
+15 V
+VS
THS3125
470 W
RG
50-W Source
+
50-W Load
470 W
6.8 mF
0.1 mF
49.9 W
50-W Source
VI
RF
VI
56.2 W
RM
THS3125
470 W
49.9 W
+
-VS
50-W Load
6.8 mF
0.1 mF
-15 V
RF
470 W
RG
Figure 38. Wideband, Inverting Gain
Configuration
+
-VS
6.8 mF
0.1 mF
-15 V
Figure 37. Wideband, Noninverting Gain
Configuration
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Single-Supply Operation
470 W
470 W
The THS3125 and THS3122 have the capability to
operate from a single supply voltage ranging from 10
V to 30 V. When operating from a single power
supply, biasing the input and output at mid-supply
allows for the maximum output voltage swing. The
circuits in Figure 39 show inverting and noninverting
amplifiers configured for single-supply operation.
+15 V
75-W Transmission Line
VO(1)
75 W
VI
75 W
n lines
75 W
75 W
-15 V
VO(n)
75 W
+VS
50-W Source
Figure 40. Video Distribution Amplifier
Application
VI
49.9 W
THS3125
RT
49.9 W
50-W Load
RF
470 W
Driving Capacitive Loads
+VS/2
Applications such as FET drivers and line drivers can
be highly capacitive and cause stability problems for
high-speed amplifiers.
RG
470 W
Figure 41 through Figure 47 show recommended
methods for driving capacitive loads. The basic idea
is to use a resistor or ferrite chip to isolate the phase
shift at high frequency caused by the capacitive load
from the amplifier feedback path. See Figure 41 for
recommended resistor values versus capacitive load.
RF
470 W
+VS/2
+VS
RG
50-W Source
470 W
VI
49.9 W
THS3125
56.2 W
RT
60
50
40
30
20
10
0
50-W Load
+VS/2
+VS/2
Figure 39. DC-Coupled, Single-Supply Operation
Video Distribution
The wide bandwidth, high slew rate, and high output
drive current of the THS3125 and THS3122 match
the demands for video distribution to deliver video
signals down multiple cables. To ensure high signal
quality with minimal degradation of performance, a
0.1-dB gain flatness should be at least 7x the
passband frequency to minimize group delay
variations from the amplifier. A high slew rate
minimizes distortion of the video signal, and supports
component video and RGB video signals that require
fast transition times and fast settling times for high
signal quality. Figure 40 illustrates a typical video
distribution amplifier application configuration.
10
100
C
L - Capacitive Load (pF)
Figure 41. Recommended RISO vs Capacitive
Load
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Placing a small series resistor, RISO, between the
amplifier output and the capacitive load, as shown in
Figure 42, is an easy way of isolating the load
capacitance.
Figure 44 shows another method used to maintain
the low-frequency load independence of the amplifier
while isolating the phase shift caused by the
capacitance at high frequency. At low frequency,
feedback is mainly from the load side of RISO. At high
frequency, the feedback is mainly via the 27-pF
capacitor. The resistor RIN in series with the negative
input is used to stabilize the amplifier and should be
equal to the recommended value of RF at unity gain.
Replacing RIN with a ferrite of similar impedance at
about 100 MHz as shown in Figure 45 gives similar
results with reduced dc offset and low frequency
noise.
RF
+VS
RG
RISO
100-W Load
5.11 W
1 mF
RF
-VS
49.9 W
+VS
27 pF
+VS
RG
560 W
100-W Load
1 mF
5.11 W
Figure 42. Resistor to Isolate Capacitive Load
RIN
Using a ferrite chip in place of RISO, as Figure 43
shows, is another approach of isolating the output of
the amplifier. The ferrite impedance characteristic
versus frequency is useful to maintain the low
frequency load independence of the amplifier while
isolating the phase shift caused by the capacitance at
high frequency. Use a ferrite with similar impedance
to RISO, 20 Ω to 50 Ω, at 100 MHz and low
impedance at dc.
-VS
49.9 W
+VS
Figure 44. Feedback Technique with Input
Resistor for Capacitive Load
RF
RF
+VS
27 pF
RG
Ferrite
100-W Load
+VS
Bead
Ferrite
Bead
RG
100-W Load
5.11 W
FIN
1 mF
-VS
1 mF
+VS
49.9 W
-VS
49.9 W
+VS
Figure 43. Ferrite Bead to Isolate Capacitive Load
Figure 45. Feedback Technique with Input Ferrite
Bead for Capacitive Load
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Figure 46 shows a configuration that uses two
amplifiers in parallel to double the output drive current
to larger capacitive loads. This technique is used
when more output current is needed to charge and
discharge the load faster as when driving large FET
transistors.
Saving Power with Shutdown Functionality
and Setting Threshold Levels with the
Reference Pin
The
THS3125
features
a
shutdown
pin
(SHUTDOWN) that lowers the quiescent current from
8.4 mA/amp down to 370 µA/amp, ideal for reducing
system power.
RF
The shutdown pin of the amplifier defaults to the REF
pin voltage in the absence of an applied voltage,
putting the amplifier in the normal on mode of
operation. To turn off the amplifier in an effort to
conserve power, the shutdown pin can be driven
towards the positive rail. The threshold voltages for
power-on and power-down (or shutdown) are relative
to the supply rails and are given in the Shutdown
Characteristics (THS3125 Only) table. Below the
Enable threshold voltage, the device is on. Above the
Disable threshold voltage, the device is off. Behavior
between these threshold voltages is not specified.
+VS
RG
5.11 W
24.9 W
-VS
RF
+VS
1 nF
+VS
RG
5.11 W
Note that this shutdown functionality is self-defining:
the amplifier consumes less power in shutdown
mode. The shutdown mode is not intended to provide
24.9 W
-VS
a
high-impedance output. In other words, the
shutdown functionality is not intended to allow use as
a 3-state bus driver. When in shutdown mode, the
impedance looking back into the output of the
amplifier is dominated by the feedback and gain
setting resistors, but the output impedance of the
device itself varies depending on the voltage applied
to the outputs.
Figure 46. Parallel Amplifiers for Higher Output
Drive
Figure 47 shows a push-pull FET driver circuit typical
of ultrasound applications with isolation resistors to
isolate the gate capacitance from the amplifier.
As with most current feedback amplifiers, the internal
architecture places some limitations on the system
when in shutdown mode. Most notably is the fact that
the amplifier actually turns on if there is a ±0.7 V or
greater difference between the two input nodes (IN+
and IN–) of the amplifier. If this difference exceeds
±0.7 V, the output of the amplifier creates an output
voltage equal to approximately [(IN+ – IN–) – 0.7V] ×
Gain. Also, if a voltage is applied to the output while
in shutdown mode, the IN– node voltage is equal to
VO(applied) × RG/(RF + RG) . For low gain configurations
and a large applied voltage at the output, the
amplifier may actually turn on because of the
behavior described here.
+VS
+VS
5.11 W
-VS
RF
RF
2RG
+VS
5.11 W
The time delays associated with turning the device on
and off are specified as the time it takes for the
amplifier to reach either 10% or 90% of the final
output voltage. The time delays are in the order of
microseconds because the amplifier moves in and out
of the linear mode of operation in these transitions.
-VS
-VS
Figure 47. PowerFET Drive Circuit
space
space
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Power-Down Reference Pin Operation
Printed-Circuit Board Layout Techniques for
Optimal Performance
In addition to the shutdown pin, the THS3125
features a reference pin (REF) which allows the user
to control the enable or disable power-down voltage
levels applied to the SHUTDOWN pin. In most
split-supply applications, the reference pin is
connected to ground. In either case, the user must be
aware of voltage-level thresholds that apply to the
shutdown pin. Table 2 shows examples and illustrate
the relationship between the reference voltage and
the power-down thresholds. In the table, the threshold
levels are derived by the following equations:
Achieving optimum performance with high-frequency
amplifiers such as the THS3125 and THS3122
requires careful attention to board layout parasitic and
external component types. Recommendations that
optimize performance include:
•
Minimize parasitic capacitance to any ac ground
for all of the signal I/O pins. Parasitic capacitance
on the output and input pins can cause instability.
To reduce unwanted capacitance,
a window
around the signal I/O pins should be opened in all
of the ground and power planes around those
pins. Otherwise, ground and power planes should
be unbroken elsewhere on the board.
SHUTDOWN ≤ REF + 0.8 V for enable
SHUTDOWN ≥ REF + 2V for disable
Where the usable range at the REF pin is:
•
Minimize the distance [0.25 inch, (6,4 mm)] from
the power-supply pins to high-frequency 0.1-µF
and 100-pF decoupling capacitors. At the device
pins, the ground and power plane layout should
not be in close proximity to the signal I/O pins.
Avoid narrow power and ground traces to
minimize inductance between the pins and the
VCC– ≤ VREF ≤ (VCC+ – 4V)
The recommended mode of operation is to tie the
REF pin to midrail, therefore setting the
enable/disable thresholds to V(midrail) + 0.8 V and
V(midrail) = 2 V, respectively.
decoupling
capacitors.
The
power-supply
Table 2. Shutdown Threshold Voltage Levels
connections should always be decoupled with
these capacitors. Larger (6.8 µF or more)
tantalum decoupling capacitors, effective at lower
frequencies, should also be used on the main
supply pins. These capacitors may be placed
somewhat farther from the device and may be
shared among several devices in the same area
of the printed circuit board (PCB).
REFERENCE
SUPPLY
PIN
ENABLE
DISABLE
VOLTAGE (V) VOLTAGE (V)
LEVEL (V)
LEVEL (V)
±15, ±5
±15
±15
±5
0
0.8
2.8
2.0
4.0
0
2.0
–2.0
1.0
–1.2
1.8
3.0
1.0
17
•
Careful selection and placement of external
components
±5
–1.0
15.0
5.0
–0.2
15.8
5.8
preserve
the
high-frequency
+30
+10
performance of the THS3125 and THS3122.
Resistors should be a very low reactance type.
Surface-mount resistors work best and allow a
tighter overall layout. Again, keep the leads and
PCB trace length as short as possible. Never use
wirebound type resistors in a high-frequency
application. Because the output pin and inverting
input pins are the most sensitive to parasitic
capacitance, always position the feedback and
series output resistors, if any, as close as possible
to the inverting input pins and output pins. Other
network components, such as input termination
resistors, should be placed close to the
gain-setting resistors. Even with a low parasitic
capacitance that shunts the external resistors,
excessively high resistor values can create
significant time constants that can degrade
7.0
Note that if the REF pin is left unterminated, it floats
to the positive rail and falls outside of the
recommended operating range given above VCC–
≤
VREF ≤ (VCC+ – 4V). As a result, it no longer serves as
a reliable reference for the SHUTDOWN pin, and the
enable/disable thresholds given above no longer
apply. If the SHUTDOWN pin is also left
unterminated, it floats to the positive rail and the
device is disabled. If balanced, split supplies are used
(±VS) and the REF and SHUTDOWN pins are
grounded, the device is enabled.
space
space
space
performance.
Good
axial
metal-film
or
surface-mount resistors have approximately 0.2
pF in shunt with the resistor. For resistor values
greater than 2.0 kΩ, this parasitic capacitance can
add a pole and/or a zero that can affect circuit
operation. Keep resistor values as low as
possible,
consistent
with
load
driving
considerations.
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•
Connections to other wideband devices on the
board may be made with short direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to
the next device as a lumped capacitive load.
Relatively wide traces [0.05 inch (1,3 mm) to 0.1
inch (2,54 mm)] should be used, preferably with
ground and power planes opened up around
them. Estimate the total capacitive load and
determine if isolation resistors on the outputs are
necessary. Low parasitic capacitive loads (less
than 4 pF) may not need an RS because the
•
Socketing a high-speed device such as the
THS3125 and THS3122 is not recommended. The
additional lead length and pin-to-pin capacitance
introduced by the socket can create an extremely
troublesome parasitic network which can make it
almost impossible to achieve a smooth, stable
frequency response. Best results are obtained by
soldering the THS3125/THS3122 amplifiers
directly onto the board.
PowerPAD™ Design Considerations
The THS3125 and THS3122 are available in a
thermally-enhanced PowerPAD family of packages.
These packages are constructed using a downset
leadframe upon which the die is mounted [see
Figure 48(a) and Figure 48(b)]. This arrangement
results in the lead frame being exposed as a thermal
pad on the underside of the package [see
Figure 48(c)]. Because this thermal pad has direct
thermal contact with the die, excellent thermal
performance can be achieved by providing a good
thermal path away from the thermal pad. Note that
devices such as the THS312x have no electrical
connection between the PowerPAD and the die.
THS3125
and
THS3122
are
nominally
compensated to operate with a 2-pF parasitic
load. Higher parasitic capacitive loads without an
RS are allowed as the signal gain increases (thus
increasing the unloaded phase margin). If a long
trace is required, and the 6-dB signal loss intrinsic
to
a
doubly-terminated transmission line is
matched-impedance
acceptable, implement
a
transmission line using microstrip or stripline
techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A 50-Ω
environment is not necessary onboard, and in
fact, a higher impedance environment improves
distortion as shown in the distortion versus load
plots. With a characteristic board trace impedance
based on board material and trace dimensions, a
matching series resistor into the trace from the
output of the THS3125/THS3122 is used as well
as a terminating shunt resistor at the input of the
destination device. Remember also that the
terminating impedance is the parallel combination
of the shunt resistor and the input impedance of
the destination device: this total effective
impedance should be set to match the trace
DIE
(a) Side View
Thermal
Pad
DIE
(b) End View
(c) Bottom View
Figure 48. Views of Thermally-Enhanced Package
impedance. If the 6-dB attenuation of
a
is
be
The PowerPAD package allows for both assembly
and thermal management in one manufacturing
operation. During the surface-mount solder operation
(when the leads are being soldered), the thermal pad
can also be soldered to a copper area underneath the
package. Through the use of thermal paths within this
copper area, heat can be conducted away from the
package into either a ground plane or other heat
dissipating device.
doubly-terminated
unacceptable,
transmission
long trace
line
can
a
series-terminated at the source end only. Treat
the trace as a capacitive load in this case. This
configuration does not preserve signal integrity as
well as a doubly-terminated line. If the input
impedance of the destination device is low, there
is some signal attenuation as a result of the
voltage divider formed by the series output into
the terminating impedance.
The PowerPAD package represents a breakthrough
in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward
mechanical methods of heatsinking.
16
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© 2001–2011, Texas Instruments Incorporated
Product Folder Link(s): THS3122 THS3125
THS3122
THS3125
www.ti.com
SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
PowerPAD™ Layout Considerations
transfer. Therefore, the holes under the
THS3125/THS3122 PowerPAD package should
make the connection to the internal ground plane
with a complete connection around the entire
circumference of the plated-through hole.
0.205
(5,21)
0.060
(1,52)
0.017
(0,432)
6. The top-side solder mask should leave the
terminals of the package and the thermal pad
area with its five holes exposed. The bottom-side
solder mask should cover the five holes of the
thermal pad area. This configuration prevents
solder from being pulled away from the thermal
pad area during the reflow process.
0.013
(0,33)
Pin 1
0.075
(1,91)
0.094
(2,39)
0.030
(0,76)
0.025
(0,64)
7. Apply solder paste to the exposed thermal pad
area and all of the IC terminals.
0.040
(1,01)
0.010
(0,254)
vias
0.035
(0,89)
8. With these preparatory steps in place, the IC is
simply placed in position and run through the
solder reflow operation as any standard
surface-mount component. This procedure results
in a part that is properly installed.
Top View
Dimensions are in inches (millimeters).
Figure 49. DGN PowerPAD PCB Etch and Via
Pattern
Power Dissipation and Thermal
Considerations
Although there are many ways to properly heatsink
the PowerPAD package, the following steps illustrate
the recommended approach.
The THS3125 and THS3122 incorporate automatic
thermal shutoff protection. This protection circuitry
shuts down the amplifier if the junction temperature
exceeds approximately +160°C. When the junction
temperature reduces to approximately +140°C, the
amplifier turns on again. However, for maximum
performance and reliability, the designer must take
care to ensure that the design does not exceed a
junction temperature of +125°C. Between +125°C
and +150°C, damage does not occur, but the
performance of the amplifier begins to degrade and
1. PCB with a top side etch pattern as shown in
Figure 49.
2. Place five holes in the area of the thermal pad.
These holes should be 0.01 inch (0,254 mm) in
diameter. Keep them small so that solder wicking
through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along
the thermal plane outside of the thermal pad
area. These vias help dissipate the heat
generated by the THS3125/THS3122 IC. These
additional vias may be larger than the 0.01-inch
(0,254-mm) diameter vias directly under the
thermal pad. They can be larger because they
are not in the thermal pad area to be soldered so
that wicking is not a problem.
long-term
reliability
suffers.
The
thermal
characteristics of the device are dictated by the
package and the PCB. Maximum power dissipation
for a given package can be calculated using the
following formula.
T
max - TA
PDMax
=
qJA
4. Connect all holes to the internal ground plane.
Note that the PowerPAD is electrically isolated
from the silicon and all leads. Connecting the
PowerPAD to any potential voltage, such as VS–,
is acceptable as there is no electrical connection
to the silicon.
where:
•
PDMax is the maximum power dissipation in the
amplifier (W)
•
Tmax is the absolute maximum junction
temperature (°C)
•
TA is the ambient temperature (°C)
5. When connecting these holes to the ground
plane, do not use the typical web or spoke via
connection methodology. Web connections have
a high thermal resistance connection that is
useful for slowing the heat transfer during
soldering operations. This resistance makes the
soldering of vias that have plane connections
easier. In this application; however, low thermal
resistance is desired for the most efficient heat
θJA = θJC + θCA
where:
•
θJC is the thermal coefficient from the silicon
junctions to the case (°C/W)
•
θCA is the thermal coefficient from the case to
ambient air (°C/W)
© 2001–2011, Texas Instruments Incorporated
Submit Documentation Feedback
17
Product Folder Link(s): THS3122 THS3125
THS3122
THS3125
SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
www.ti.com
For systems where heat dissipation is more critical,
the THS3125 and THS3122 are also available in an
8-pin MSOP with PowerPAD package that offers
even better thermal performance. The thermal
coefficient for the PowerPAD packages are
substantially improved over the traditional SOIC.
Maximum power dissipation levels are depicted in
Figure 50 for the available packages. The data for the
PowerPAD packages assume a board layout that
follows the PowerPAD layout guidelines discussed
above and detailed in the PowerPAD application note
(literature number SLMA002). Figure 50 also
illustrates the effect of not soldering the PowerPAD to
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
TJ = +125°C
q
= 58.4°C/W
JA
q
= 95°C/W
JA
q
= 158°C/W
JA
-40
-20
0
20
40
60
80
100
a
PCB. The thermal impedance increases
T
A - Free-Air Temperature (°C)
substantially, which may cause serious heat and
performance issues. Always solder the PowerPAD to
the PCB for optimum performance.
Results shown are with no air flow and PCB size of 3 in × 3 in
(76,2 mm × 76,2 mm).
When determining whether or not the device satisfies
the maximum power dissipation requirement, it is
important to not only consider quiescent power
dissipation, but also dynamic power dissipation. Often
times, this type of dissipation is difficult to quantify
because the signal pattern is inconsistent, but an
estimate of the RMS power dissipation can provide
visibility into a possible problem.
•
θJA = 58.4°C/W for 8-pin MSOP with PowerPAD (DGN
package)
•
•
θJA = 95°C/W for 8-pin SOIC High-K test PCB (D package)
θJA = 158°C/W for 8-pin MSOP with PowerPAD without solder
Figure 50. Maximum Power Dissipation vs
Ambient Temperature
18
Submit Documentation Feedback
© 2001–2011, Texas Instruments Incorporated
Product Folder Link(s): THS3122 THS3125
THS3122
THS3125
www.ti.com
SLOS382D –SEPTEMBER 2001–REVISED FEBRUARY 2011
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (July, 2010) to Revision D
Page
•
Changed output current (absolute maximum) from 275 mA to 550 mA ............................................................................... 2
Changes from Revision B (October, 2009) to Revision C
Page
•
•
•
•
•
•
•
Corrected REF pin name for THS3125 shown in front-page figure ...................................................................................... 1
Deleted Shutdown pin input levels parameters and specifications from Recommended Operating Conditions table ......... 3
Updated Shutdown Characteristics table test conditions; changed GND to REF, corrected VSHDN notations ..................... 5
Added VREF and VSHDN parameters and speciifications to Shutdown Characteristics table ................................................. 5
Revised second and fourth paragraphs of Saving Power with Shutdown Functionality section ........................................ 14
Updated equation in Power-Down Reference Pin Operation section that describes usable range at the REF pin ........... 15
Revised paragraph in Power-Down Reference Pin Operation that discusses behavior of unterminated REF pin ............ 15
© 2001–2011, Texas Instruments Incorporated
Submit Documentation Feedback
19
Product Folder Link(s): THS3122 THS3125
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
THS3122CD
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
SOIC
D
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
3122C
THS3122CDDA
THS3122CDDAG3
THS3122CDG4
THS3122CDR
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
DDA
DDA
D
75
75
Green (RoHS
& no Sb/Br)
0 to 70
3122C
8
Green (RoHS
& no Sb/Br)
CU SN
0 to 70
3122C
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU SN
0 to 70
3122C
D
8
2500
2500
75
Green (RoHS
& no Sb/Br)
0 to 70
3122C
THS3122CDRG4
THS3122ID
D
8
Green (RoHS
& no Sb/Br)
0 to 70
3122C
D
8
Green (RoHS
& no Sb/Br)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
0 to 70
3122I
THS3122IDDA
THS3122IDDAG3
THS3122IDG4
THS3125CPWP
THS3125CPWPG4
THS3125ID
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
DDA
DDA
D
8
75
Green (RoHS
& no Sb/Br)
3122I
8
75
Green (RoHS
& no Sb/Br)
CU SN
3122I
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
HTSSOP
HTSSOP
SOIC
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
3122I
PWP
PWP
D
14
14
14
14
14
14
14
90
Green (RoHS
& no Sb/Br)
HS3125C
HS3125C
THS3125I
THS3125I
HS3125I
HS3125I
HS3125I
90
Green (RoHS
& no Sb/Br)
0 to 70
50
Green (RoHS
& no Sb/Br)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
THS3125IDG4
THS3125IPWP
THS3125IPWPG4
THS3125IPWPR
SOIC
D
50
Green (RoHS
& no Sb/Br)
HTSSOP
HTSSOP
HTSSOP
PWP
PWP
PWP
90
Green (RoHS
& no Sb/Br)
90
Green (RoHS
& no Sb/Br)
2000
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
THS3125IPWPRG4
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
HTSSOP
PWP
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
HS3125I
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
THS3122CDR
SOIC
D
8
2500
2000
330.0
330.0
12.4
12.4
6.4
6.9
5.2
5.6
2.1
1.6
8.0
8.0
12.0
12.0
Q1
Q1
THS3125IPWPR
HTSSOP PWP
14
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
THS3122CDR
SOIC
D
8
2500
2000
367.0
367.0
367.0
367.0
35.0
35.0
THS3125IPWPR
HTSSOP
PWP
14
Pack Materials-Page 2
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