THS3061 [TI]
LOW DISTORTION HIGH SLEW RATE CURRENT FREEBACK AMPLIFIERS; 低失真，高摆率电流放大器客户反馈
| 型号： | THS3061 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LOW DISTORTION HIGH SLEW RATE CURRENT FREEBACK AMPLIFIERS |
| 文件： | 总25页 (文件大小：206K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLOS394A – JULY 2002 – OCTOBER 2002
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ꢖ ꢒꢒꢌ ꢗꢓ ꢔꢘ ꢓ ꢙꢚ ꢈꢍ ꢖꢍ ꢒꢎ ꢂ
The THS3061 and THS3062 provide well-regulated ac
performance characteristics with power supplies ranging
from ±5-V operation up to ±15-V supplies. Most notable,
the 0.1-dB flat bandwidth is exceedingly high, reaching
beyond 100 MHz, and the THS306x has less than 0.3 dB
of peaking in the frequency response when configured in
unity gain. The unity gain bandwidth of 300 MHz allows for
excellent distortion characteristics at 10 MHz. The
flexibility of the current feedback design allows for a
220-MHz, –3-dB bandwidth in a gain of 10 indicating
excellent performance even at high gains.
FEATURES
D
D
D
D
D
D
Unity Gain Bandwidth: 300 MHz
0.1 dB Bandwidth: 120 MHz (G=2)
High Slew Rate: 7000 V/µs
HD3 at 10 MHz: –81 dBc (G=2, R = 150 Ω)
L
High Output Current: ±145 mA into 50 Ω
Power Supply Voltage Range: ±5 V to ±15 V
APPLICATIONS
D
D
D
D
D
High-Speed Signal Processing
Test and Measurement Systems
VDSL Line Driver
The THS306x consumes 8.3-mA per channel quiescent
current at room temperature and has the capability of
producing up to ±145 mA of output current. The THS3061
is packaged in an 8-pin SOIC and an 8-pin MSOP with
PowerPAD . The THS3062 is available in an 8-pin SOIC
with PowerPAD and an 8-pin MSP with PowerPAD.
High-Voltage ADC Preamplifier
Video Line Driver
DESCRIPTION
The THS3061 (single) and THS3062 (dual) are
high-voltage, high slew-rate current feedback amplifiers
utilizing Texas Instruments BICOM-1 process. Designed
for low-distortion with a high slew rate of 7000 V/µs, the
THS306x amplifiers are ideally suited for applications
requiring large, linear output signals such as video line
drivers and VDSL line drivers.
RELATED DEVICES AND DESCRIPTIONS
THS3001 Low Distortion Current Feedback Amplifier
THS3112
Dual Current Feedback Amplifier With 175 mA Drive
THS3122 Dual Current Feedback Amplifier With 350 mA Drive
OPA691
Wideband Current Feedback Amplifier With 350 mA
Drive
SLEW RATE
vs
HARMONIC DISTORTION
vs
OUTPUT STEP
FREQUENCY
8000
–20
–30
–40
–50
–60
–70
–80
–90
G = 5
V
G = 1
7000
6000
5000
= ±15
CC
R = 375 Ω
= 25°C
V
= ±15 V
= ±5 V
= 1 kΩ
R = 750 Ω
CC
V
f
CC
T
A
R
L
f
O
V
= 2V
PP
4000
3000
V
= ±15
2nd HD
CC
2000
1000
0
3rd HD
–100
100 k
0
5
10
15
20
25
1 M
10 M
100 M
Output Step – V
f – Frequency – Hz
PP
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
ꢚꢎ ꢉ ꢌꢕ ꢔ ꢀꢍ ꢉꢏ ꢌ ꢓꢀꢓ ꢛꢜ ꢝꢞ ꢟ ꢠꢡ ꢢꢛꢞꢜ ꢛꢣ ꢤꢥ ꢟ ꢟ ꢦꢜꢢ ꢡꢣ ꢞꢝ ꢧꢥꢨ ꢩꢛꢤ ꢡꢢꢛ ꢞꢜ ꢪꢡ ꢢꢦꢫ ꢚꢟ ꢞꢪꢥ ꢤꢢꢣ
ꢤ ꢞꢜ ꢝꢞꢟ ꢠ ꢢꢞ ꢣ ꢧꢦ ꢤ ꢛ ꢝꢛ ꢤ ꢡ ꢢꢛ ꢞꢜꢣ ꢧ ꢦꢟ ꢢꢬꢦ ꢢꢦ ꢟ ꢠꢣ ꢞꢝ ꢀꢦꢭ ꢡꢣ ꢍꢜꢣ ꢢꢟ ꢥꢠ ꢦꢜꢢ ꢣ ꢣꢢ ꢡꢜꢪ ꢡꢟ ꢪ ꢮ ꢡꢟ ꢟ ꢡ ꢜꢢꢯꢫ
ꢚꢟ ꢞ ꢪꢥꢤ ꢢ ꢛꢞ ꢜ ꢧꢟ ꢞ ꢤ ꢦ ꢣ ꢣ ꢛꢜ ꢰ ꢪꢞ ꢦ ꢣ ꢜꢞꢢ ꢜꢦ ꢤꢦ ꢣꢣ ꢡꢟ ꢛꢩ ꢯ ꢛꢜꢤ ꢩꢥꢪ ꢦ ꢢꢦ ꢣꢢꢛ ꢜꢰ ꢞꢝ ꢡꢩ ꢩ ꢧꢡ ꢟ ꢡꢠ ꢦꢢꢦ ꢟ ꢣꢫ
Copyright 2002, Texas Instruments Incorporated
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SLOS394A – JULY 2002 – OCTOBER 2002
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handledwith appropriate precautions. Failure to observe
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
proper handling and installation procedures can cause damage.
UNIT
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
Supply voltage, V
16.5 V
±
S
Input voltage, V
I
±V
S
Output current, I
200 mA
O
Differential input voltage, V
±3 V
ID
PACKAGE DISSIPATION RATINGS
Continuous power dissipation
See Dissipation Rating Table
POWER RATING
(T = 125°C)
J
Maximum junction temperature, T
150°C
J
θ
θ
JA
JC
(°C/W) (°C/W)
PACKAGE
Operating free-air temperature range, T
–40°C to 85°C
–65°C to 150°C
A
T
A
≤ 25°C
T = 85°C
A
Storage temperature range, T
stg
(1)
D(8 pin)
38.3
9.2
95
1.05 W
2.18 W
1.71 W
0.42 W
0.87 W
0.68 W
Lead temperature
1,6 mm (1/16 inch) from case for 10 seconds
300°C
DDA (8 pin)
(2)
45.8
58.4
(1)
DGN (8 pin)
4.7
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
The THS306x may incorporate a PowerPAD on the underside of
the chip. This acts as a heatsink and must be connected to a
thermally dissipative plane for proper power dissipation. Failure
to do so may result in exceeding the maximum junction
temperature which could permanently damage the device. See TI
technical brief SLMA002 for more information about utilizing the
PowerPAD thermally enhanced package.
(1)
This data was taken using the JEDEC High-K test PCB. For the
JEDEC Low-K test PCB, θ is 167°C/W with power rating at
JA
T
A
= 25°C of 0.6 W.
(2)
This data was taken using 2 oz. trace and copper pad that is
soldered directly to a 3 in. x 3 in. PCB.
(2)
RECOMMENDED OPERATING CONDITIONS
MIN
MAX UNIT
Dual supply
±5
±15
Supply voltage
V
Single supply
10
30
Operating free-air temperature, T
–40
85
°C
A
PACKAGE/ORDERING INFORMATION
ORDERABLE PACKAGE AND NUMBER
(OPERATING RANGE FROM –40°C TO 85°C)
NUMBER OF CHANNELS
(1)
(1)
PLASTIC SOIC-8
(1)
PLASTIC MSOP-8
PLASTIC SOIC-8
(D)
PACKAGE MARKING
PowerPAD (DDA)
PowerPAD (DGN)
THS3061DGN
THS3062DGN
1
2
THS3061D
THS3062D
—
BIB
BIC
THS3062DDA
(1)
This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., THS3062DGNR).
PIN ASSIGNMENTS
TOP VIEW
D, DGN
TOP VIEW
D, DDA, DGN
THS3061
THS3062
NC
NC
V +
1
2
3
4
8
7
6
5
1V
V +
S
1
2
3
4
8
7
6
5
OUT
V
V
IN–
S
1V
1V
2V
2V
IN–
OUT
OUT
V
IN+
IN+
IN–
V
NC
S–
V
2
VIN+
S–
NC – No internal connection
2
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SLOS394A – JULY 2002 – OCTOBER 2002
ELECTRICAL CHARACTERISTICS
V
S
= ±15 V: R = 560 Ω, R = 150 Ω, and G = +2 unless otherwise noted
f L
THS3061, THS3062
TYP
OVER TEMPERATURE
PARAMETER
TEST CONDITIONS
0°C to
70°C
–40°C
to 85°C
MIN/TYP/
MAX
25°C
25°C
UNITS
AC PERFORMANCE
G = +1, R = 750 Ω
300
275
260
220
120
0.3
f
G = +2, R = 560 Ω
Small-signal bandwidth
f
MHz
Typ
(V = 100 mV , Peaking < 0.3 dB)
G = +5, R = 357 Ω
O
PP
f
G = +10, R = 200 Ω
f
Bandwidth for 0.1 dB flatness
Peaking at a gain of +1
G = +2, V = 100mV
pp
MHz
dB
Typ
Typ
Typ
O
V
O
= 100 mV
pp
Large-signal bandwidth
G = +2, V = 4 V
pp
G = +5, 20 V Step
G = +2, 10 V Step
120
7000
5700
1
MHz
O
Slew rate (25% to 75% level)
V/µs
Typ
Rise and fall time
Settling time to 0.1%
0.01%
G = +2, V = 10 V Step
ns
ns
ns
Typ
Typ
Typ
O
G = –2, V = 2 V Step
30
O
G = –2, V = 2 V Step
125
O
Harmonic distortion
G = +2, f = 10 MHz, V = 2 V
pp
O
R
L
R
L
R
L
R
L
= 150 Ω
= 1 kΩ
= 150 Ω
= 1 kΩ
–78
–73
–81
–82
nd
2
3
harmonic
harmonic
dBc
dBc
Typ
Typ
rd
G = +2, f = 10 MHz,
c
rd
V
O
= 2 V
3
order intermodulation distortion
–93
dBc
Typ
pp(envelope)
∆f = 200 kHz
f > 10 kHz
f > 10 kHz
Input voltage noise
2.6
20
nV/√Hz
pA/√Hz
pA/√Hz
Typ
Typ
Typ
Typ
Typ
Input current noise (noninverting)
Input current noise (inverting)
Differential gain (NTSC, PAL)
Differential phase (NTSC, PAL)
DC PERFORMANCE
f > 10 kHz
36
G = +2, R = 150 Ω
0.02%
0.01°
L
G = +2, R = 150 Ω
L
Open-loop transimpedance gain
Input offset voltage
V
V
V
V
V
V
V
= 0 V, R = 1 kΩ
1
0.7
0.6
±4.4
±10
±32
±25
±38
±45
0.6
±4.5
±10
±35
±30
±40
±50
MΩ
mV
Min
Max
Typ
Max
Typ
Max
Typ
O
L
= 0 V
= 0 V
= 0 V
= 0 V
= 0 V
= 0 V
±0.7
±3.5
CM
CM
CM
CM
CM
CM
Average offset voltage drift
Input bias current (inverting)
Average bias current drift (–)
Input bias current (noninverting)
Average bias current drift (+)
INPUT
µV/°C
µA
±2.0
±6.0
±20
±25
nA/°C
µA
nA/°C
Common-mode input range
Common-mode rejection ratio
±13.9
72
±13.1
±13.1
±13.1
V
Min
Min
Typ
Typ
Typ
V
= ±0.5 V
60
58
58
dB
kΩ
Ω
CM
Noninverting
Inverting
518
71
Input resistance
Input capacitance
Noninverting
1
pF
3
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SLOS394A – JULY 2002 – OCTOBER 2002
ELECTRICAL CHARACTERISTICS (continued)
V
S
= ±15 V: R = 560 Ω, R = 150 Ω, and G = +2 unless otherwise noted
f L
THS3061, THS3062
OVER TEMPERATURE
TYP
PARAMETER
TEST CONDITIONS
0°C to
–40°C
MIN/TYP/
MAX
25°C
25°C
UNITS
70°C
to 85°C
OUTPUT
R
R
R
R
= 1 kΩ
±13.7
±13
±13.4
±12.6
140
±13.4
±12.4
135
±13.3
±12.3
130
L
L
L
L
Voltage output swing
V
Min
= 150 Ω
= 50 Ω
= 50 Ω
Current output, sourcing
145
mA
mA
Ω
Min
Min
Typ
Current output, sinking
–145
0.1
–140
–135
–130
Closed-loop output impedance
POWER SUPPLY
G = +1, f = 1 MHz
Specified operating voltage
Maximum operating voltage
Maximum quiescent current/channel
Minimum quiescent current/channel
Power supply rejection (+PSRR)
Power supply rejection (–PSRR)
±15
V
Typ
Max
Max
Min
Min
Min
±16.5
10
±16.5
11.7
6
±16.5
12
V
8.3
8.3
76
mA
mA
dB
dB
6.1
65
6
V
V
= 14.50 V to 15.50 V
63
63
S+
= –14.50 V to –15.50 V
74
65
63
63
S–
4
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SLOS394A – JULY 2002 – OCTOBER 2002
ELECTRICAL CHARACTERISTICS
V
S
= ±5 V: R = 560 Ω, R = 150 Ω, and G = +2 unless otherwise noted
f
L
THS3061, THS3062
TYP
OVER TEMPERATURE
PARAMETER
TEST CONDITIONS
0°C to
70°C
–40°C
to 85°C
MIN/TYP/
MAX
25°C
25°C
UNITS
AC PERFORMANCE
G = +1, R = 750 Ω
275
250
230
210
100
< 0.3
100
2700
1300
2
f
G = +2, R = 560 Ω
Small-signal bandwidth
f
MHz
Typ
(V = 100 mV , peaking < 0.3 dB)
G = +5, R = 383 Ω
O
PP
f
G = +10, R = 200 Ω
f
Bandwidth for 0.1 dB flatness
Peaking at a gain of +1
G = +2, V = 100 mV
pp
MHz
dB
Typ
Typ
Typ
O
V
O
= 100 mV
pp
Large-signal bandwidth
G = +2, V = 4 V
pp
MHz
O
G = +1, 5 V Step, R = 750 Ω
f
Slew rate (25% to 75% level)
V/µs
ns
Typ
Typ
Typ
G = +5, 5 V Step, R = 357 Ω
f
Rise and fall time
Settling time to 0.1%
0.01%
G = +2, V = 5 V Step
O
G = –2, V = 2 V Step
20
O
ns
G = –2, V = 2 V Step
160
O
Harmonic distortion
G = +2, f = 10 MHz, V = 2 V
pp
O
R
L
R
L
R
L
R
L
= 150 Ω
= 1 kΩ
= 150 Ω
= 1 kΩ
–76
–70
–79
–77
nd
2
3
harmonic
harmonic
dBc
dBc
Typ
Typ
rd
G = +2, f = 10 MHz,
c
rd
V
O
= 2 V
3
order intermodulation distortion
–91
dBc
Typ
pp(envelope)
∆f = 200 kHz
f > 10 kHz
f > 10 kHz
f > 10 kHz
Input voltage noise
2.6
20
nV/√Hz
pA/√Hz
pA/√Hz
Typ
Typ
Typ
Typ
Typ
Input current noise (noninverting)
Input current noise (inverting)
Differential gain (NTSC, PAL)
Differential phase (NTSC, PAL)
36
G = +2, R = 150 Ω
0.025%
0.01°
L
G = +2, R = 150 Ω
L
DC PERFORMANCE
Open-loop transimpedance gain
Input offset voltage
V
V
V
V
V
V
V
= 0 V, R = 1 kΩ
0.8
0.6
0.5
±4.4
±9
0.5
±4.5
±9
MΩ
mV
Min
Max
Typ
Max
Typ
Max
Typ
O
L
= 0 V
= 0 V
= 0 V
= 0 V
= 0 V
= 0 V
±0.3
±3.5
CM
CM
CM
CM
CM
CM
Average offset voltage drift
Input bias current (inverting)
Average bias current drift (–)
Input bias current (noninverting)
Average bias current drift (+)
µV/°C
µA
±2.0
±6.0
±20
±25
±32
±20
±38
±30
±35
±25
±40
±35
nA/°C
µA
nA/°C
INPUT
Common-mode input range
Common-mode rejection ratio
±3.9
70
±3.1
±3.1
±3.1
V
Min
Min
Typ
Typ
Typ
V
= ±0.5 V
60
58
58
dB
kΩ
Ω
CM
Noninverting
Inverting
518
71
Input resistance
Input capacitance
Noninverting
1
pF
5
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SLOS394A – JULY 2002 – OCTOBER 2002
ELECTRICAL CHARACTERISTICS (continued)
V
S
= ±5 V: R = 560 Ω, R = 150 Ω, and G = +2 unless otherwise noted
f
L
THS3061, THS3062
OVER TEMPERATURE
TYP
PARAMETER
TEST CONDITIONS
0°C to
–40°C
MIN/TYP/
MAX
25°C
25°C
UNITS
70°C
to 85°C
OUTPUT
R
R
R
R
= 1 kΩ
±4.1
±4.0
63
±3.8
±3.6
61
±3.8
±3.6
60
±3.7
±3.5
59
L
L
L
L
Voltage output swing
V
Min
= 150 Ω
= 50 Ω
= 50 Ω
Current output, sourcing
Current output, sinking
mA
mA
Ω
Min
Min
Typ
–63
0.1
–61
–60
–59
Closed-loop output impedance
G = +1, f = 1 MHz
POWER SUPPLY
Specified operating voltage
Minimum operating voltage
Maximum quiescent current
Minimum quiescent current
Power supply rejection (+PSRR)
Power supply rejection (–PSRR)
±5
V
Typ
Min
Max
Min
Min
Min
±4.5
8.0
5.0
65
±4.5
9.2
4.7
63
±4.5
9.5
4.6
63
V
6.3
6.3
73
mA
mA
dB
dB
V
V
= 4.50 V to 5.50 V
S+
= –4.50 V to –5.50 V
75
65
63
63
S–
PARAMETER MEASUREMENT INFORMATION
R
g
R
f
R
R
f
g
V
I
_
+
_
+
V
O
R
V
O
V
I
T
R
L
R
L
50 Ω
Figure 1. Noninverting Test Circuit
Figure 2. Inverting Test Circuit
6
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TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
3 – 14
15, 16
17 – 23
24 – 29
30
Small signal frequency response
Large signal frequency response
Harmonic distortion
vs Frequency
vs Output voltage
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Frequency
Harmonic distortion
Output impedance
Common-mode rejection ratio
Input current noise
31
32
Voltage noise density
Power supply rejection ratio
Common-mode rejection ratio (DC)
Supply current
33
34
vs Input common-mode range
vs Power supply voltage
35
36, 37
38, 39
40
Slew rate
vs Output voltage
vs Output step
Slew rate
Input offset voltage
vs Output voltage swing
41
Overdrive recovery time
Differential gain
42, 43
44, 45
46, 47
vs Number of 150-Ω loads
vs Number of 150-Ω loads
Differential phase
7
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TYPICAL CHARACTERISTICS
SMALL SIGNAL FREQUENCY RESPONSE SMALL SIGNAL FREQUENCY RESPONSE
SMALL SIGNAL FREQUENCY RESPONSE
2
3
3
G = 1
R
f
500 Ω
G = 1
G = 1
R
f
500 Ω
V
R
= ±15 V
= 150 Ω
R
f
500 Ω
CC
L
I
2
1
V
= ±5 V
2
1
V
= ±5 V
1
0
CC
CC
R
V
= 150 Ω
= 100 mV
R
V
= 1 kΩ
= 100 mV
PP
L
I
L
I
V
= 100 mV
PP
PP
0
0
R
f
1 kΩ
–1
–1
–2
–3
–4
–1
–2
–3
–4
R
f
1 kΩ
R 1 kΩ
f
R
750 Ω
f
–2
–3
–4
R
f
750 Ω
R
750 Ω
f
100 k
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100M
1 G
100 k
1 M
10 M
100 M
1 G
f – Frequency – Hz
f – Frequency – Hz
f – Frequency – Hz
Figure 3
Figure 4
Figure 5
SMALL SIGNAL FREQUENCY RESPONSE SMALL SIGNAL FREQUENCY RESPONSE SMALL SIGNAL FREQUENCY RESPONSE
2
1
0
10
9
8
7
6
5
G = 1
R
357 Ω
R
357 Ω
f
f
R
500 Ω
f
V
= ±15 V
CC
8
R
V
= 1 kΩ
= 100 mV
PP
L
I
6
4
2
–1
R
f
1 kΩ
R
f
1 kΩ
4
3
2
1
0
R
1 kΩ
f
–2
–3
–4
R
560 Ω
f
0
–2
–4
G = 2
G = 2
V = ±15, ±5 V
CC
R
750 Ω
f
R
f
560 Ω
V
R
V
= ±15, ±5 V
= 150 Ω
= 100 mV
CC
L
I
R
V
= 1 kΩ
= 100 mV
L
I
PP
PP
100 k
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
1 G
f – Frequency – Hz
f – Frequency – Hz
f – Frequency – Hz
Figure 6
Figure 7
Figure 8
SMALL SIGNAL FREQUENCY RESPONSE SMALL SIGNAL FREQUENCY RESPONSE
SMALL SIGNAL FREQUENCY RESPONSE
18
18
18
G = 5
G = 5
= ±15 V
G = 5
R
200 Ω
V
R
V
= ±5 V
= 150 Ω
= 100 mV
f
CC
L
I
V
V
R
= ±15 V
= 150 Ω
CC
= 1 kΩ
R
200 Ω
CC
L
R
f
200 Ω
f
16
14
R
V
L
16
14
16
14
12
PP
= 100 mV
V
= 100 mV
I
PP
I
PP
12
10
8
12
10
8
R
f
560 Ω
R
f
560 Ω
R
f
560 Ω
10
8
R
383 Ω
f
R
357 Ω
R
f
357 Ω
f
100 k
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
1 G
f – Frequency – Hz
f – Frequency – Hz
f – Frequency – Hz
Figure 9
Figure 10
Figure 11
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SMALL SIGNAL FREQUENCY RESPONSE SMALL SIGNAL FREQUENCY RESPONSE SMALL SIGNAL FREQUENCY RESPONSE
3
2
1
3
2
1
21
20
19
18
G = –1
=±5 V
G = –1
=±15 V
V
V
CC
R 332 Ω
f
CC
R
L
V
= 150 Ω
= 100 mV
R
L
V
= 150 Ω
= 100 mV
R
332 Ω
f
I
PP
I
PP
0
0
–1
–1
R
f
560 Ω
R
f
560 Ω
G = 10
–2
–2
V
R
=±5 V, ±15 V
= 150 Ω, 1 kΩ
CC
L
R
f
511 Ω
R
475 Ω
f
17
16
V
= 100 mV
,
PP
–3
–4
–3
–4
I
100 k
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
1 G
f – Frequency – Hz
f – Frequency – Hz
f – Frequency – Hz
Figure 12
Figure 13
Figure 14
THS3061
HARMONIC DISTORTION
vs
LARGE SIGNAL FREQUENCY RESPONSE
LARGE SIGNAL FREQUENCY RESPONSE
FREQUENCY
9
–20
–30
–40
–50
–60
–70
–80
–90
–100
8
V
= ±15 V
CC
G = 1
7
6
R
L
= 150 Ω
R
R
= 150 Ω
= 1 KΩ
L
V
= 2 V
PP
= 750 Ω
O
6
R
f
f
5
2nd HD
G = 2
3
0
V
= ±5 V
= 604 Ω
= 150 Ω
= 1 kΩ
4
CC
f
L
L
I
G = 2
R
R
R
V
V
= ±15 V
CC
3
2
3rd HD
R
f
= 560 Ω
V
= 2 V
,
= 2 V
,
I
PP
PP
100 k
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
f – Frequency – Hz
f – Frequency – Hz
f – Frequency – Hz
Figure 15
Figure 16
Figure 17
THS3062
HARMONIC DISTORTION
vs
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
–20
–40
–60
–70
–80
–20
–30
–40
–50
–60
–70
–80
V
G = 2
R
R
V
= ±5 V, V
= ±15 V
CC
V
G = 1
R
V
R
= ±15 V
CC
V
G = 1
R
V
R
= ±5 V
CC
CC
= 560 Ω
= 150 Ω
= 1 V
PP
= 150 Ω
f
L
O
= 150 Ω
L
L
= 2 V
= 2 V
O
PP
= 845 Ω
O
PP
= 750 Ω
f
f
2nd HD
–60
–80
2nd HD
2nd HD
–90
3rd HD
–100
–110
–90
3rd HD
10 M
3rd HD
10 M
–100
–100
100 k
1 M
100 M
1 M
10 M
100 M
100 k
1 M
100 M
f – Frequency – Hz
f – Frequency – Hz
f – Frequency – Hz
Figure 18
Figure 19
Figure 20
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HARMONIC DISTORTION
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
FREQUENCY
–40
vs
vs
FREQUENCY
FREQUENCY
–20
–30
–40
–50
–60
–70
–80
–40
V = ±5 V
CC
G = 2
V
G = 2
R
R
V
= ±15 V
CC
G = 1
V
V
= ±15 V
= ±5 V
CC
CC
R
R
V
= 560 Ω
= 150 Ω
= 560 Ω
= 150 Ω
= 2V
PP
–50
–60
–50
–60
f
L
O
f
L
O
R
R
= 1 kΩ
= 750 Ω
L
f
= 2V
PP
V
= 2V
PP
O
2nd HD
2nd HD
2nd HD
–70
–70
–80
–90
–80
–90
3rd HD
3rd HD
3rd HD
–90
–100
–100
–100
1 M
10 M
100 M
1 M
10 M
100 M
100 k
1 M
10 M
100 M
f – Frequency – Hz
f – Frequency – Hz
f – Frequency – Hz
Figure 21
Figure 22
Figure 23
THS3061
THS3061
THS3061
HARMONIC DISTORTION
vs
HARMONIC DISTORTION
vs
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
OUTPUT VOLTAGE
OUTPUT VOLTAGE
–60
–65
–70
–60
–60
–65
–70
V
= ±15 V
CC
G = 1
= 150 Ω
2nd HD
2nd HD
2nd HD
–65
–70
R
L
f= 1 MHz
R
f
= 750 Ω
3rd HD
–75
–80
–75
–80
–75
–80
3rd HD
3rd HD
–85
–90
–85
–85
–90
V = ±5 V
CC
G = 1
V = ±15 V
CC
G = 1
–90
R
R
= 1 kΩ
= 750 Ω
R
R
= 1 kΩ
= 750 Ω
L
f
L
f
–95
–95
–95
f = 10 MHz
f = 10 MHz
–100
–100
–100
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
V
– Output Voltage – V
O
V
– Output Voltage – V
V
– Output Voltage – V
O
O
Figure 24
Figure 25
Figure 26
THS3061
HARMONIC DISTORTION
vs
HARMONIC DISTORTION
vs
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
OUTPUT VOLTAGE
–60
–70
–80
–90
–60
–70
–80
–90
OUTPUT VOLTAGE
3rd HD 8 MHz
2nd HD 1 MHz
–60
–65
–70
V
G = 1
R
= ±5 V
2nd HD 1 MHz
CC
2nd HD
= 150 Ω
2nd HD f = 8 MHz
L
f= 1 MHz
2nd HD 8 MHz
3rd HD 1 MHz
3rd HD 8 MHz
3rd HD f = 1 MHz
–75
–80
3rd HD
V
= ±5 V
CC
G = 2
V
= ±15 V
CC
G = 2
–85
–90
–95
–100
–110
–100
–110
R
R
= 560 Ω
= 150 Ω
f
L
R
R
= 560 Ω
= 150 Ω
f
L
0
1
2
3
4
5
6
0
2
4
6
8
10
12
0
1
2
3
4
5
6
V
– Output Voltage – V
O
V
– Output Voltage – V
O
V
– Output Voltage – V
O
Figure 27
Figure 28
Figure 29
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COMMON-MODE REJECTION RATIO
OUTPUT IMPEDANCE
INPUT CURRENT NOISE
vs
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
1000
100
90
300
250
200
150
100
G = 2
V
V
V
= ±15 V,
= ±5 V,
= ±2.5 V,
G = 2
CC
CC
CC
80
70
60
50
40
30
20
V
R
R
= ±15 V, ±5 V
= 150 Ω
= 1 kΩ
CC
L
f
R
V
= 560 Ω
= ±15 V
f
CC
THS3062
10
1
In–
THS3061
0.1
50
0
10
0
In+
0.01
100 k
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
1 G
10
100
1 k
10 k
100 k
f – Frequency – Hz
f – Frequency – Hz
f – Frequency – Hz
Figure 32
Figure 30
Figure 31
POWER SUPPLY REJECTION RATIO
COMMON-MODE REJECTION RATIO (DC)
VOLTAGE NOISE DENSITY
vs
vs
vs
FREQUENCY
INPUT COMMON-MODE RANGE
FREQUENCY
45
40
35
30
25
20
15
10
70
80
V
= ±15 V, ±5 V
CC
G = 2
R
L
= 150 Ω
70
60
50
40
30
20
10
60
50
R
R
V
= 560 Ω
= 150 Ω
f
L
O
= 35 mV
PP
PSRR+
40
30
20
10
V
= ±5 V
CC
PSRR–
5
0
0
V
= ±15 V
CC
–10
100 k
0
–15
10
100
1 k
10 k
100 k
–10
–5
0
5
10
15
1 M
10 M
100 M
f – Frequency – Hz
Input Common-Mode Voltage Range – V
f – Frequency – Hz
Figure 33
THS3061
Figure 34
Figure 35
THS3062
SLEW RATE
vs
SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
OUTPUT VOLTAGE
POWER SUPPLY VOLTAGE
POWER SUPPLY VOLTAGE
3500
12
24
21
18
15
12
9
G = –1
85°C
25°C
R
R
T
A
= 475 Ω
= 150 Ω
= 25°C
f
L
3000
2500
2000
1500
1000
500
85°C
10
8
25°C
V
= ±15
CC
–40°C
6
4
–40°C
V
= ±5
CC
6
2
0
3
0
0
0
2
4
6
2.5
4.5
6.5
8.5 10.5 12.5 14.5 16.5
4
6
8
10
12
14
16
V
– Output Voltage – V
Power Supply Voltage – V
Power Supply Voltage – V
O
Figure 36
Figure 37
Figure 38
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SLEW RATE
vs
SLEW RATE
vs
INPUT OFFSET VOLTAGE
vs
OUTPUT VOLTAGE
OUTPUT STEP
OUTPUT VOLTAGE SWING
3000
8000
7000
6000
5000
0
G = 1
G = 5
R
R
T
= 750 Ω
= 150 Ω
= 25°C
V
= ±15
= 375 Ω
= 25°C
f
L
A
CC
2500
2000
1500
1000
500
–40°C
R
f
T
A
25°C
85°C
–0.5
V
= ±15
CC
4000
3000
V
= ±15
CC
V
= ±5
CC
–1
2000
1000
0
–1.5
0
0
1
2
3
4
5
6
0
5
10
15
20
25
–20 –15 –10 –5
0
5
10 15 20
V
– Output Voltage – V
Output Step – V
O
V
– Output Voltage Swing – V
PP
O
Figure 39
Figure 40
Figure 41
DIFFERENTIAL GAIN
vs
OVERDRIVE RECOVERY TIME
NUMBER OF 150-Ω LOADS
OVERDRIVE RECOVERY TIME
15
4
3
2
1
0
3
2
1
5
4
3
2
1
0.6
G = 2
R
f
= 560 Ω
10
5
0.5
0.4
0.3
0.2
NTSC Modulation
V
= ±5
CC
0
0
0
–1
–2
–1
–2
–5
–1
G = 5
G = 2
V
R
R
= ±15
= 560 Ω
= 150 Ω
CC
f
L
–3
V
= ±5
CC
V
= ±15
–10
–15
–2
–3
CC
0.1
0
R
f
= 604 Ω
–3
–4
–4
–5
R
L
= 150 Ω
0.5
1
1.5
2
0
0.5
1
1.5
2
0
1
2
3
4
t – Time – µs
t – Time – µs
Number of 150-Ω Loads
Figure 42
Figure 43
Figure 44
DIFFERENTIAL PHASE
vs
DIFFERENTIAL GAIN
vs
DIFFERENTIAL PHASE
vs
NUMBER OF 150-Ω LOADS
NUMBER OF 150-Ω LOADS
NUMBER OF 150-Ω LOADS
0.08
0.06
0.04
0.02
0
0.07
0.6
G = 2
G = 2
G = 2
R
f
= 560 Ω
R
f
= 560 Ω
0.06
0.05
0.04
0.03
0.02
R
f
= 560 Ω
0.5
0.4
PAL Modulation
NTSC Modulation
PAL Modulation
V
= ±5
V
= ±5
CC
CC
V
= ±5
CC
0.3
0.2
V
= ±15
CC
0.1
0
V
= ±15
0.01
0
CC
3
V
= ±15
CC
1
2
4
1
2
3
4
1
2
3
4
Number of 150-Ω Loads
Number of 150-Ω Loads
Number of 150-Ω Loads
Figure 45
Figure 46
Figure 47
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APPLICATION INFORMATION
INTRODUCTION
The THS306x is a high-speed, operational amplifier configured in a current-feedback architecture. The device is built
using Texas Instruments BiCOM–I process, a 30-V, dielectrically isolated, complementary bipolar process with NPN
and PNP transistors possessing fTs of several GHz. This configuration implements an exceptionally
high-performance amplifier that has a wide bandwidth, high slew rate, fast settling time, and low distortion.
RECOMMENDED FEEDBACK AND GAIN RESISTOR VALUES
As with all current-feedback amplifiers, the bandwidth of the THS306x is an inversely proportional function of the
value of the feedback resistor. The recommended resistors for the optimum frequency response are shown in Table 1.
These should be used as a starting point and once optimum values are found, 1% tolerance resistors should be used
to maintain frequency response characteristics. For most applications, a feedback resistor value of 750 Ω is
recommended a good compromise between bandwidth and phase margin that yields a very stable amplifier.
Table 1. Recommended Resistor Values for Optimum Frequency Response
GAIN
1
R
F
for V
CC
= ±15 V
R
F
for V = ±5 V
CC
750 Ω
560 Ω
357 Ω
200 Ω
750 Ω
560 Ω
383 Ω
200 Ω
2, –1
5
10
As shown in Table 1, to maintain the highest bandwidth with an increasing gain, the feedback resistor is reduced. The
advantage of dropping the feedback resistor (and the gain resistor) is the noise of the system is also reduced
compared to no reduction of these resistor values, see noise calculations section. Thus, keeping the bandwidth as
high as possible maintains very good distortion performance of the amplifier by keeping the excess loop gain as high
as possible.
Care must be taken to not drop these values too low. The amplifier’s output must drive the feedback resistance (and
gain resistance) and may place a burden on the amplifier. The end result is that distortion may actually increase due
to the low impedance load presented to the amplifier. Careful management of the amplifier bandwidth and the
associated loading effects needs to be examined by the designer for optimum performance.
The THS3061/62 amplifiers exhibit very good distortion performance and bandwidth with the capability of utilizing
up to +15 V power supplies. Their excellent current drive capability of up to +145 mA driving into a 50-Ω load allows
for many versatile applications. One application is driving a twisted pair line (i.e. telephone line). Figure 48 shows
a simple circuit for driving a twisted pair differentially.
13
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SLOS394A – JULY 2002 – OCTOBER 2002
+12 V
+
0.1 µF
10 µF
THS3062(a)
R
S
+
_
V +
I
R
Line
2
2n
499 Ω
1:n
0.1 µF
Telephone Line
R
Line
210 Ω
THS3062(b)
R
S
+
_
V –
I
R
Line
2
2n
499 Ω
10 µF
0.1 µF
+
–12 V
Figure 48. Simple Line Driver With THS3062
Due to the large power supply voltages and the large current drive capability, power dissipation of the amplifier must
not be neglected. To have as much power dissipation as possible in a small package, the THS3062 is available only
in a MSOP–8 PowerPAD package (DGN) and an even lower thermal impedance SOIC–8 PowerPAD package
(DDA). The thermal impedance of a standard SOIC package is too large to allow for useful applications with up to
30 V across the power supply terminals with this dual amplifier. But, the THS3061 – a single amplifier, can be utilized
in the standard SOIC package. Again, power dissipation of the amplifier must be carefully examined or else the
amplifiers could become too hot and performance can be severely degraded. See the Power Dissipation and Thermal
Considerations section for more information on thermal management.
14
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SLOS394A – JULY 2002 – OCTOBER 2002
NOISE CALCULATIONS
Noise can cause errors on very small signals. This is especially true for amplifying small signals coming over a
transmission line or an antenna. The noise model for current-feedback amplifiers (CFB) is the same as for voltage
feedback amplifiers (VFB). The only difference between the two is that CFB amplifiers generally specify different
current-noise parameters for each input, while VFB amplifiers usually only specify one noise-current parameter. The
noise model is shown in Figure 49. This model includes all of the noise sources as follows:
•
•
•
•
en = Amplifier internal voltage noise (nV/√Hz)
IN+ = Noninverting current noise (pA/√Hz)
IN– = Inverting current noise (pA/√Hz)
eRx = Thermal voltage noise associated with each resistor (eRx = 4 kTRx)
e
Rs
e
n
R
S
Noiseless
+
_
e
ni
e
no
IN+
e
Rf
R
f
e
Rg
IN–
R
g
Figure 49. Noise Model
The total equivalent input noise density (eni) is calculated by using the following equation:
) ǒIN ) R Ǔ2 ) ǒIN * ǒR ø RgǓǓ2 ) 4 kTR ) 4 kTǒR ø RgǓ
2
Ǹ
ǒe Ǔ
e
+
s
n
ni
where
f
f
S
k = Boltzmann’s constant = 1.380658 × 10–23
T = Temperature in degrees Kelvin (273 +°C)
Rf || Rg = Parallel resistance of Rf and Rg
To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (eni) by the overall
amplifier gain (AV).
R
f
e
+ e
A
+ e
ǒ
1 )
Ǔ
(Noninverting Case)
no
ni
V
ni
R
g
As the previous equations show, to keep noise at a minimum, small value resistors should be used. As the closed-loop
gain is increased (by reducing RF and RG), the input noise is reduced considerably because of the parallel resistance
term. This leads to the general conclusion that the most dominant noise sources are the source resistor (RS) and the
internal amplifier noise voltage (en). Because noise is summed in a root-mean-squares method, noise sources
smaller than 25% of the largest noise source can be effectively ignored. This can greatly simplify the formula and
make noise calculations much easier.
15
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SLOS394A – JULY 2002 – OCTOBER 2002
PRINTED-CIRCUIT BOARD LAYOUT TECHNIQUES FOR OPTIMAL PERFORMANCE
Achieving optimum performance with high frequency amplifier-like devices in the THS306x family requires careful
attention to board layout parasitic and external component types.
Recommendations that optimize performance include:
D
D
Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the output
and input pins can cause instability. To reduce unwanted capacitance, a window around the signal I/O pins should
be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should
be unbroken elsewhere on the board.
Minimize the distance (< 0.25”) from the power supply pins to high frequency 0.1-µF decoupling capacitors. At
the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid
narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The
power supply connections should always be decoupled with these capacitors. Larger (6.8 µF or more) tantalum
decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may
be placed somewhat farther from the device and may be shared among several devices in the same area of the
PC board. The primary goal is to minimize the impedance seen in the differential-current return paths. For driving
differential loads with the THS3062, adding a capacitor between the power supply pins improves 2nd order
harmonic distortion performance. This also minimizes the current loop formed by the differential drive.
D
D
Careful selection and placement of external components preserve the high frequency performance of the
THS306x family. Resistors should be a very low reactance type. Surface-mount resistors work best and allow
a tighter overall layout. Again, keep their leads and PC board trace length as short as possible. Never use
wirebound type resistors in a high frequency application. Since the output pin and inverting input pins are the most
sensitive to parasitic capacitance, always position the feedback and series output resistors, if any, as close as
possible to the inverting input pins and output pins. Other network components, such as input termination
resistors, should be placed close to the gain-setting resistors. Even with a low parasitic capacitance shunting
the external resistors, excessively high resistor values can create significant time constants that can degrade
performance. Good axial metal-film or surface-mount resistors have approximately 0.2 pF in shunt with the
resistor. For resistor values > 2.0 kΩ, this parasitic capacitance can add a pole and/or a zero that can effect circuit
operation. Keep resistor values as low as possible, consistent with load driving considerations.
Connections to other wideband devices on the board may be made with short direct traces or through onboard
transmission lines. For short connections, consider the trace and the input to the next device as a lumped
capacitive load. Relatively wide traces (50 mils to 100 mils) should be used, preferably with ground and power
planes opened up around them. Estimate the total capacitive load and determine if isolation resistors on the
outputs are necessary. Low parasitic capacitive loads (< 4 pF) may not need an R since the THS306x family
S
is nominally compensated to operate with a 2-pF parasitic load. Higher parasitic capacitive loads without an R
S
are allowed as the signal gain increases (increasing the unloaded phase margin). If a long trace is required, and
the 6-dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched
impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for
microstrip and stripline layout techniques).
A 50-Ω environment is not necessary onboard, and in fact, a higher impedance environment improves distortion
as shown in the distortion versus load plots. With a characteristic board trace impedance based on board material
and trace dimensions, a matching series resistor into the trace from the output of the THS306x is used as well as
a terminating shunt resistor at the input of the destination device.
Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input
impedance of the destination device: this total effective impedance should be set to match the trace impedance. If
the 6-dB attenuation of a doubly terminated transmission line is unacceptable, a long trace can be
series-terminated at the source end only. Treat the trace as a capacitive load in this case. This does not preserve
signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there is
some signal attenuation due to the voltage divider formed by the series output into the terminating impedance.
D
Socketing a high speed part like the THS306x family is not recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which
can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by
soldering the THS306x family parts directly onto the board.
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SLOS394A – JULY 2002 – OCTOBER 2002
PowerPAD DESIGN CONSIDERATIONS
The THS306x family is available in a thermally-enhanced PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which the die is mounted [see Figure 50(a) and Figure 50(b)]. This
arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see
Figure 50(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can
be achieved by providing a good thermal path away from the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During
the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a
copper area underneath the package. Through the use of thermal paths within this copper area, heat can be
conducted away from the package into either a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of surface
mount with the, heretofore, awkward mechanical methods of heatsinking.
DIE
Thermal
Pad
Side View (a)
DIE
End View (b)
Bottom View (c)
Figure 50. Views of Thermally Enhanced Package
Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the
recommended approach.
68 Mils x 70 Mils
(Via diameter = 10 mils)
Figure 51. DGN PowerPAD PCB Etch and Via Pattern
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SLOS394A – JULY 2002 – OCTOBER 2002
PowerPAD PCB LAYOUT CONSIDERATIONS
1. Prepare the PCB with a top side etch pattern as shown in Figure 51. There should be etch for the leads as well
as etch for the thermal pad.
2. Place five holes in the area of the thermal pad. These holes should be 10 mils in diameter. Keep them small so
that solder wicking through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the THS306x family IC. These additional vias may be larger than the 10-mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area
to be soldered so that wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this
application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes
under the THS306x family PowerPAD package should make their connection to the internal ground plane with
a complete connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five holes
exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This prevents solder
from being pulled away from the thermal pad area during the reflow process.
7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
8. With these preparatory steps in place, the IC is simply placed in position and run through the solder reflow
operation as any standard surface-mount component. This results in a part that is properly installed.
POWER DISSIPATION AND THERMAL CONSIDERATIONS
To maintain maximum output capabilities, the THS360x does not incorporate automatic thermal shutoff protection.
The designer must take care to ensure that the design does not violate the absolute maximum junction temperature
of the device. Failure may result if the absolute maximum junction temperature of 150°C is exceeded. For best
performance, design for a maximum junction temperature of 125°C. Between 125°C and 150°C, damage does not
occur, but the performance of the amplifier begins to degrade.
The thermal characteristics of the device are dictated by the package and the PC board. Maximum power dissipation
for a given package can be calculated using the following formula.
Tmax * TA
qJA
PDmax
+
where
P
is the maximum power dissipation in the amplifier (W).
Dmax
T
max
is the absolute maximum junction temperature (°C).
T is the ambient temperature (°C).
A
θ
θ
θ
= θ + θ
JA
JC
CA
JC CA
is the thermal coefficient from the silicon junctions to the case (°C/W).
is the thermal coefficient from the case to ambient air (°C/W).
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SLOS394A – JULY 2002 – OCTOBER 2002
For systems where heat dissipation is more critical, the THS306x family of devices is offered in an 8-pin MSOP with
PowerPAD and the THS3062 is available in the SOIC–8 PowerPAD package offering even better thermal
performance. The thermal coefficient for the PowerPAD packages are substantially improved over the traditional
SOIC. Maximum power dissipation levels are depicted in the graph for the available packages. The data for the
PowerPAD packages assume a board layout that follows the PowerPAD layout guidelines referenced above and
detailed in the PowerPAD application note number SLMA002. The following graph also illustrates the effect of not
soldering the PowerPAD to a PCB. The thermal impedance increases substantially which may cause serious heat
and performance issues. Be sure to always solder the PowerPAD to the PCB for optimum performance.
4
T
J
= 125°C
3.5
3
θ
= 45.8°C/W
JA
θ
= 58.4°C/W
JA
2.5
2
θ
= 98°C/W
JA
1.5
1
0.5
0
θ
= 158°C/W
JA
–40 –20
0
20
40
60
80
100
T
A
– Free-Air Temperature – °C
Results are With No Air Flow and PCB Size = 3”x3”
θ
θ
θ
θ
= 45.8°C/W for 8-Pin SOIC w/PowerPad (DDA)
= 58.4°C/W for 8-Pin MSOP w/PowerPad (DGN)
= 98°C/W for 8-Pin SOIC High Test PCB (D)
= 158°C/W for 8-Pin MSOP w/PowerPad w/o Solder
JA
JA
JA
JA
Figure 52. Maximum Power Dissipation vs Ambient Temperature
When determining whether or not the device satisfies the maximum power dissipation requirement, it is important
to not only consider quiescent power dissipation, but also dynamic power dissipation. Often times, this is difficult to
quantify because the signal pattern is inconsistent, but an estimate of the RMS power dissipation can provide visibility
into a possible problem.
DRIVING A CAPACITIVE LOAD
Driving capacitive loads with high-performance amplifiers is not a problem as long as certain precautions are taken.
The first is to realize that the THS306x has been internally compensated to maximize its bandwidth and slew-rate
performance. When the amplifier is compensated in this manner, capacitive loading directly on the output decreases
the device’s phase margin leading to high-frequency ringing or oscillations. Therefore, for capacitive loads of greater
than 10 pF, it is recommended that a resistor be placed in series with the output of the amplifier, as shown in Figure 53.
A minimum value of 10 Ω should work well for most applications. For example, in 75-Ω transmission systems, setting
the series resistor value to 75 Ω both isolates any capacitance loading and provides the proper line impedance
matching at the source end.
R
f
R
g
_
+
Input
10 Ω
Output
LOAD
THS306x
C
Figure 53. Driving a Capacitive Load
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SLOS394A – JULY 2002 – OCTOBER 2002
GENERAL CONFIGURATIONS
A common error for the first-time CFB user is creating a unity gain buffer amplifier by shorting the output directly to
the inverting input. A CFB amplifier in this configuration oscillates and is not recommended. The THS306x, like all
CFB amplifiers, must have a feedback resistor for stable operation. Additionally, placing capacitors directly from the
output to the inverting input is not recommended. This is because, at high frequencies, a capacitor has a very low
impedance. This results in an unstable amplifier and should not be considered when using a current-feedback
amplifier. Because of this, integrators and simple low-pass filters, which are easily implemented on a VFB amplifier,
have to be designed slightly differently. If filtering is required, simply place an RC-filter at the noninverting terminal
of the operational-amplifier (see Figure 54).
R
g
R
f
1
f
+
–3dB
2pR1C1
V
R
–
O
f
1
ǒ
Ǔ
Ǔ
+
ǒ
1 )
V
O
V
R
1 ) sR1C1
g
I
+
V
I
R1
C1
Figure 54. Single-Pole Low-Pass Filter
If a multiple-pole filter is required, the use of a Sallen-Key filter can work very well with CFB amplifiers. This is because
the filtering elements are not in the negative feedback loop and stability is not compromised. Because of their high
slew-rates and high bandwidths, CFB amplifiers can create very accurate signals and help minimize distortion. An
example is shown in Figure 55.
C1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
+
_
V
I
1
R1
R2
f
+
–3dB
2pRC
C2
R
f
1
R
g
=
R
f
2 –
)
R
g
(
Q
Figure 55. 2-Pole Low-Pass Sallen-Key Filter
20
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SLOS394A – JULY 2002 – OCTOBER 2002
There are two simple ways to create an integrator with a CFB amplifier. The first, shown in Figure 56, adds a resistor
in series with the capacitor. This is acceptable because at high frequencies, the resistor is dominant and the feedback
impedance never drops below the resistor value. The second, shown in Figure 57, uses positive feedback to create
the integration. Caution is advised because oscillations can occur due to the positive feedback.
C1
R
f
1
S )
ȡ
ȣ
ꢀ
V
R
R
g
f
O
f
+
ǒ Ǔ
–
ȧ
R C1ȧ
V
I
V
R
S
g
I
V
O
Ȣ
+
THS306x
Figure 56. Inverting CFB Integrator
R
g
R
f
For Stable Operation:
R
R
R2
f
≥
R1 || R
–
g
A
THS306x
V
O
+
R
R
f
1 +
V
O
V
I
g
)
(
R1
R2
sR1C1
V
I
C1
R
A
Figure 57. Noninverting CFB Integrator
The THS306x may also be employed as a very good video distribution amplifier. One characteristic of distribution
amplifiers is the fact that the differential phase (DP) and the differential gain (DG) are compromised as the number
of lines increases and the closed-loop gain increases. Be sure to use termination resistors throughout the distribution
system to minimize reflections and capacitive loading.
R
g
R
f
75-Ω Transmission Line
75 Ω
–
V
O1
+
V
I
THS306x
75 Ω
75 Ω
N Lines
75 Ω
V
ON
75 Ω
Figure 58. Video Distribution Amplifier Application
21
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SLOS394A – JULY 2002 – OCTOBER 2002
MECHANICAL INFORMATION
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
PINS **
0.050 (1,27)
8
14
16
DIM
0.020 (0,51)
0.010 (0,25)
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
M
0.014 (0,35)
A MAX
A MIN
14
8
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
7
A
0.010 (0,25)
0°–8°
ā
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
4040047/D 10/96
NOTES:A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
22
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SLOS394A – JULY 2002 – OCTOBER 2002
MECHANICAL INFORMATION
DDA (S–PDSO–G8)
Power PADt PLASTIC SMALL-OUTLINE
0,49
0,35
M
0,10
1,27
8
5
Thermal Pad
(See Note D)
0,20 NOM
6,20
5,84
3,99
3,81
Gage Plane
0,25
1
4
4,98
4,80
0°–8°
0,89
0,41
1,68 MAX
Seating Plane
0,10
1,55
1,40
0,13
0,03
4202561/A02/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.
PowerPAD is a trademark of Texas Instruments.
23
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SLOS394A – JULY 2002 – OCTOBER 2002
MECHANICAL INFORMATION
DGN (S-PDSO-G8)
PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
0,38
0,25
0,65
M
0,25
8
5
Thermal Pad
(See Note D)
0,15 NOM
3,05
2,95
4,98
4,78
Gage Plane
0,25
0°–6°
ā
1
4
0,69
0,41
3,05
2,95
Seating Plane
0,10
0,15
0,05
1,07 MAX
4073271/A 01/98
NOTES:A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions include mold flash or protrusions.
D. The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad. This pad is electrically and
thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-187
PowerPAD is a trademark of Texas Instruments.
24
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