TDP142RNQR [TI]
8.1Gbps DP1.4 线性转接驱动器 | RNQ | 40 | 0 to 70;
| 型号： | TDP142RNQR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8.1Gbps DP1.4 线性转接驱动器 | RNQ | 40 | 0 to 70 驱动 驱动器 |
| 文件： | 总36页 (文件大小：1249K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TDP142
ZHCSGQ7C –SEPTEMBER 2017–REVISED MAY 2019
TDP142 DisplayPortTM 8.1Gbps 线性转接驱动器
1 特性
3 说明
1
•
DisplayPort™1.4 高达 8.1Gbps (HBR3)
超低功耗架构
TDP142 是一款能够嗅探 AUX 和 HPD 信号的
DisplayPortTM(DP) 线性转接驱动器。该器件符合
VESA DisplayPort 标准版本 1.4，支持 1-4 通道主链
路接口，以符合 HBR3 标准的速率（每个通道
8.1Gbps）发送信号。此外，该器件与位置无关。它可
置于源设备、电缆或接收设备内，从而为总体链路预算
有效提供“负损耗”分量。
•
•
•
•
•
•
具有高达 14dB 均衡功能的线性转接驱动器
透明呈现 DisplayPort 链路训练
可通过 GPIO 或 I2C 进行配置
支持热插拔
支持 DisplayPort 双模标准版本 1.1（交流耦合
HDMI）
TDP142 提供多个接收线性均衡级别，用于补偿线缆或
电路板走线中因码间串扰 (ISI) 而产生的损耗。该器件
由 3.3V 单电源供电，支持商业级温度范围 (TDP142)
和工业级温度范围 (TDP142I)。
•
•
•
工业级温度范围：-40ºC 至 85ºC (TDP142I)
商业级温度范围：0ºC 至 70ºC (TDP142)
4mm x 6mm、0.4mm 间距 WQFN 封装
2 应用
器件信息(1)
•
•
•
•
平板电脑、笔记本电脑、台式电脑、PC
器件型号
TDP142
TDP142I
封装
WQFN (40)
WQFN (40)
封装尺寸（标称值）
4.00mm x 6.00mm
4.00mm x 6.00mm
有源电缆
监视器
扩展坞
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
空白
简化电路原理图
显示屏
ML0_IN
ML0_OUT
ML1_OUT
ML1_IN
ML2_IN
ML3_IN
ML2_OUT
ML3_OUT
TDP142
x
DP
Receptacle
GPU
TDP142
Scaler
GPU
TDP142
AUX
HPD
Copyright © 2017, Texas Instruments Incorporated
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSEZ1
TDP142
ZHCSGQ7C –SEPTEMBER 2017–REVISED MAY 2019
www.ti.com.cn
目录
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 13
8.5 Programming........................................................... 15
8.6 Register Maps......................................................... 17
Application and Implementation ........................ 20
9.1 Application Information............................................ 20
9.2 Typical Application .................................................. 22
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Power Supply Characteristics ................................... 6
6.6 DC Electrical Characteristics .................................... 6
6.7 AC Electrical Characteristics..................................... 7
6.8 Timing Requirements................................................ 8
6.9 Switching Characteristics.......................................... 8
6.10 Typical Characteristics............................................ 9
Parameter Measurement Information ................ 10
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
9
10 Power Supply Recommendations ..................... 25
11 Layout................................................................... 26
11.1 Layout Guidelines ................................................. 26
11.2 Layout Example .................................................... 26
12 器件和文档支持 ..................................................... 28
12.1 相关链接................................................................ 28
12.2 接收文档更新通知 ................................................. 28
12.3 社区资源................................................................ 28
12.4 商标....................................................................... 28
12.5 静电放电警告......................................................... 28
12.6 Glossary................................................................ 28
13 机械、封装和可订购信息....................................... 28
7
8
4 修订历史记录
Changes from Revision B (August 2018) to Revision C
Page
•
Added following to pin 11 description: If I2C_EN = “F”, then this pin must be set to “F” or “0”. ........................................... 3
Changes from Revision A (October 2017) to Revision B
Page
•
•
Changed the appearance of the pinout image in the Pin Configuration and Function section.............................................. 3
Added Note 2 To pins 29 and 32 in the Pin Functions table.................................................................................................. 4
Changes from Original (September 2017) to Revision A
Page
•
Changed the Human-body model (HBM) value From: ±6000 To: ±5000 in the ESD Ratings............................................... 5
2
Copyright © 2017–2019, Texas Instruments Incorporated
TDP142
www.ti.com.cn
ZHCSGQ7C –SEPTEMBER 2017–REVISED MAY 2019
5 Pin Configuration and Functions
RNQ Package
40-Pin (WQFN)
Top View
VCC
1
28
27
26
25
24
23
22
21
VCC
DPEQ1
RSVD1
2
3
RSVD7
RSVD6
RSVD2
RSVD3
VCC
4
5
6
7
8
AUXn
Thermal
Pad
AUXp
DPEN/HPDIN
TEST2/SDA
TEST1/SCL
RSVD4
RSVD5
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
VCC
1, 6, 20, 28
2
P
3.3-V Power Supply.
DisplayPort Receiver EQ control. This along with DPEQ0 will select the DisplayPort receiver
equalization gain. Refer to 表 2 for equalization settings.
DPEQ1
4 Level I
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
INDP0p
INDP0n
3
4
I
O
O
I
Reserved.(1)
Reserved.(1)
Reserved.(1)
Reserved.(1)
5
7
8
I
Reserved.(1)
9
I
DP Differential positive input for DisplayPort Lane 0.
DP Differential negative input for DisplayPort Lane 0.
10
I
When I2C_EN = 0, leave the pin unconnected. When I2C_EN is not ‘0’, this pin will also set the
TDP142 I2C address. See 表 4. If I2C_EN = “F”, then this pin must be set to “F” or “0”.
A0
11
4 Level I
INDP1p
INDP1n
12
13
Diff I
Diff I
DP Differential positive input for DisplayPort Lane 1.
DP Differential negative input for DisplayPort Lane 1.
DisplayPort Receiver EQ control. This along with DPEQ1 will select the DisplayPort receiver
equalization gain. Refer to 表 2 for equalization settings. When I2C_EN is not ‘0’, this pin will also
set the TDP142 I2C address. See 表 4.
DPEQ0/A1
14
4 Level I
INDP2p
INDP2n
15
16
Diff I
Diff I
DP Differential positive input for DisplayPort Lane 2.
DP Differential negative input for DisplayPort Lane 2.
(1) Leave unconnected on PCB.
Copyright © 2017–2019, Texas Instruments Incorporated
3
TDP142
ZHCSGQ7C –SEPTEMBER 2017–REVISED MAY 2019
www.ti.com.cn
Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
I2C Programming Mode or GPIO Programming Select. I2C is only disabled when this pin is ‘0".
0 = GPIO mode (I2C disabled).
R = TI Test Mode (I2C enabled at 3.3 V).
F = I2C enabled at 1.8 V.
1 = I2C enabled at 3.3 V.
I2C_EN
17
4 Level I
INDP3p
INDP3n
18
19
Diff I
Diff I
DP Differential positive input for DisplayPort Lane 3.
DP Differential negative input for DisplayPort Lane 3.
When I2C_EN=’0’, pull down with 10k or directly connect to ground. Otherwise this pin is I2C
clock. . When used for I2C clock pullup to I2C master's VCC I2C supply.
TEST1/SCL
TEST2/SDA
21
22
2 Level I
2 Level I
When I2C_EN=’0’ , pull down with 10k or directly connect to ground. Otherwise this pin is I2C data.
When used for I2C data pullup to I2C master's VCC I2C supply.
DP Enable Pin. When I2C_EN = ‘0’, this pin will enable or disable DisplayPort functionality.
Otherwise, when I2C_EN is not "0", DisplayPort functionality is enabled and disabled through I2C
registers.
L = DisplayPort Disabled. (Pull-down with 10k resistor)
H = DisplayPort Enabled. (Pull-up with10k resistor)
2 Level I
(Failsafe)
(PD)
DPEN/HPDIN
23
When I2C_EN is not "0" this pin is an input for Hot Plug Detect (HPD) received from DisplayPort
sink. When this HPDIN is low for greater than 2 ms, all DisplayPort lanes are disabled.
This pin along with AUXN is used by the TDP142 for AUX snooping. See the Application and
Implementation section for more detail.
AUXp
AUXn
24
25
I/O, CMOS
I/O, CMOS
This pin along with AUXP is used by the TDP142 for AUX snooping. See the Application and
Implementation section for more detail.
RSVD6
RSVD7
26
27
I/O, CMOS
I/O, CMOS
Reserved.(1)
Reserved.(1)
I/O
(PD)
When I2C_EN ! = 0, this pin is reserved. When I2C_EN = 0 , this pin is SNOOPENZ (L = AUX
snoop enabled and H = AUX snoop disabled with all lanes active).
SNOOPENZ/RSVD8
29(2)
OUTDP3p
OUTDP3n
30
31
Diff O
Diff O
DP Differential positive output for DisplayPort Lane 3.
DP Differential negative output for DisplayPort Lane 3.
When I2C_EN ! = 0, this pin is reserved. When I2C_EN = 0, this pin is an input for Hot Plug Detect
received from DisplayPort sink. When HPDIN is low for greater than 2ms, all DisplayPort lanes are
disabled.
I/O
(PD)
HPDIN/RSVD9
32(2)
OUTDP2p
OUTDP2n
RSVD10
OUTDP1n
OUTDP1p
RSVD11
OUTDP0n
OUTDP0p
GND
33
Diff O
Diff O
I
DP Differential positive output for DisplayPort Lane 2.
DP Differential negative output for DisplayPort Lane 2.
Reserved.(1)
34
35
36
Diff O
Diff O
I
DP Differential negative output for DisplayPort Lane 1.
DP Differential positive output for DisplayPort Lane 1.
Reserved.(1)
37
38
39
40
Diff O
Diff O
G
DP Differential negative output for DisplayPort Lane 0.
DP Differential positive output for DisplayPort Lane 0.
Ground.
Thermal Pad
(2) Not a fail-safe I/O. Actively driving pin high while VCC is removed results in leakage voltage on VCC pins.
4
Copyright © 2017–2019, Texas Instruments Incorporated
TDP142
www.ti.com.cn
ZHCSGQ7C –SEPTEMBER 2017–REVISED MAY 2019
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Supply Voltage Range(2), VCC
–0.3
4
V
Differential voltage between positive and
negative inputs
–2.5
2.5
V
Voltage Range at any input or output pin
Voltage at differential inputs
CMOS Inputs
–0.5
–0.5
VCC + 0.5
VCC + 0.5
125
V
V
Maximum junction temperature, TJ
Storage temperature, Tstg
°C
°C
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the GND terminals.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±5000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
3.6
100
3.6
100
70
UNIT
V
Main power supply
3
3.3
VCC
Supply Ramp Requirement
ms
V
V(12C)
V(PSN)
Supply that external resistors are pulled up to on SDA and SCL
Supply Noise on VCC pins
1.7
mV
°C
TDP142
Operating free-air temperature
0
TA
TDP142I
–40
85
°C
6.4 Thermal Information
TDP142
THERMAL METRIC(1)
RNQ (WQFN)
UNIT
40 PINS
37.6
20.7
9.5
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJB
9.4
RθJC(bot)
2.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2017–2019, Texas Instruments Incorporated
5
TDP142
ZHCSGQ7C –SEPTEMBER 2017–REVISED MAY 2019
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6.5 Power Supply Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Four active DP lanes operating at
8.1 Gbps;
DPEN = H; TEST2 = L;
Average active power
4 Lane DP Only
PCC(ACTIVE--DP)
660
mW
PCC(NC)
Average power with no connection
Device Shutdown
No device is connected
2.4
mW
mW
PCC(SHUTDOWN)
DPEN = L; TEST2 = L; I2C_EN = 0;
0.85
6.6 DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
4-State CMOS Inputs(DPEQ[1:0], I2C_EN)
IIH
IIL
High level input current
Low level input current
Threshold 0 / R
VCC = 3.6 V; VIN = 3.6 V
VCC = 3.6 V; VIN = 0 V
VCC = 3.3 V
20
80
µA
µA
V
–160
-40
0.55
1.65
2.7
35
4-Level VTH
Threshold R/ Float
VCC = 3.3 V
V
Threshold Float / 1
VCC = 3.3 V
V
RPU
RPD
Internal pull-up resistance
Internal pull-down resistance
kΩ
kΩ
95
2-State CMOS Input (DPEN, Test1, Test2, SNOOPENZ, HPDIN) DPEN, TEST1 and TEST2 are Failsafe.
VIH
VIL
High-level input voltage
2
0
3.6
0.8
V
V
Low-level input voltage
RPD
Internal pull-down resistance for DPEN
500
150
kΩ
Internal pull-down resistance for
SNOOPENZ (pin 29), and HPDIN (pin
32)
R(ENPD)
kΩ
IIH
IIL
High-level input current
Low-level input current
VIN = 3.6 V
–25
–25
25
25
µA
µA
VIN = GND, VCC = 3.6 V
I2C Control Pins SCL, SDA
VIH
High-level input voltage
I2C_EN = 0
0.7 x V(I2C)
3.6
0.3 x V(I2C)
0.4
V
V
VIL
Low-level input voltage
Low-level output voltage
Low-level output current
Input current on SDA pin
Input capacitance
I2C_EN = 0
0
0
VOL
IOL
I2C_EN = 0; IOL = 3 mA
I2C_EN = 0; VOL = 0.4 V
0.1 x V(I2C) < Input voltage < 3.3 V
V
20
mA
µA
pF
pF
pF
II(I2C)
CI(I2C)
–10
10
10
C(I2C_FM+_BUS) I2C bus capacitance for FM+ (1MHz)
150
150
C(I2C_FM_BUS)
R(EXT_I2C_FM+)
I2C bus capacitance for FM (400kHz)
External resistors on both SDA and SCL
when operating at FM+ (1MHz)
C(I2C_FM+_BUS) = 150 pF
C(I2C_FM_BUS) = 150 pF
620
620
820
910
Ω
Ω
External resistors on both SDA and SCL
when operating at FM (400kHz)
R(EXT_I2C_FM)
1500
2200
6
Copyright © 2017–2019, Texas Instruments Incorporated
TDP142
www.ti.com.cn
ZHCSGQ7C –SEPTEMBER 2017–REVISED MAY 2019
6.7 AC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DisplayPort Transmitter (OUTDP[3:0]p or OUTDP[3:0]n)
VTX(DIFF-PP)
Transmitter dynamic differential voltage swing range.
Amount of voltage change allowed during receiver detection
1500
mVPP
mV
VTX(RCV-DETECT)
600
100
Max mismatch from Txp + Txn for both
time and amplitude
VTX(CM-AC-PP-ACTIVE)
VTX(IDLE-DIFF-AC-PP)
VTX(IDLE-DIFF-DC)
Tx AC common-mode voltage active
mVPP
mV
AC electrical idle differential peak-to-
peak output voltage
At package pins
0
0
10
14
DC electrical idle differential output
voltage
At package pins after low pass filter to
remove AC component
mV
RTX(DIFF)
Differential impedance of the driver
AC coupling capacitor
75
75
120
265
Ω
CAC(COUPLING)
nF
Measured with respect to AC ground
over
0–500 mV
Common-mode impedance of the
driver
RTX(CM)
18
30
Ω
CTX(PARASITIC)
RLTX(DIFF)
TX input capacitance for return loss
Differential return loss
At package pins, at 2.5GHz
50 MHz – 1.25 GHz at 90 Ω
2.5 GHz at 90 Ω
1.25
pF
dB
dB
dB
mA
V
-15
-12
-13
RLTX(CM)
Common-mode return loss
TX short circuit current
50 MHz – 2.5 GHz at 90 Ω
TX± shorted to GND
ITX(SHORT)
67
0
VTX(DC-CM)
Common-mode voltage bias in the transmitter (DC)
0
AC Characteristics
Differential crosstalk between TX and
at 2.5 GHz
Crosstalk
C(P1dB-LF)
–30
dB
RX signal pairs
Low frequency 1-dB compression
point
at 100 MHz, 200 mVPP < VID
< 2000 mVPP
1300
mVPP
High frequency 1-dB compression
point
at 2.5 GHz, 200 mVPP < VID
< 2000 mVPP
C(P1dB-HF)
fLF
1300
20
mVPP
kHz
Low frequency cutoff
200 mVPP< VID < 2000 mVPP
50
200 mVPP < VID < 2000 mVPP, PRBS7,
5 Gbps
0.05
UIpp
TX output deterministic jitter
200 mVPP < VID < 2000 mVPP, PRBS7,
8.1 Gbps
0.08
0.08
UIpp
UIpp
UIpp
200 mVPP < VID < 2000 mVPP, PRBS7,
5 Gbps
TX output total jitter
200 mVPP < VID < 2000 mVPP, PRBS7,
8.1 Gbps
0.135
DisplayPort Receiver (INDP[3:0]p or INDP[3:0]n)
VID(PP)
Peak-to-peak input differential dynamic voltage range
2000
V
V
VIC
Input common mode voltage
AC coupling capacitance
Receiver equalization
Data rate
0
2
200
14
C(AC)
75
nF
EQ(DP)
DPEQ[1:0] at 4.05 GHz
HBR3
dB
Gbps
Ω
dR
8.1
120
R(ti)
Input termination resistance
80
100
AUXp or AUXn
AUX Channel DC common mode
voltage for AUXp
V(AUXP_DC_CM)
V(AUXN_DC_CM)
VCC = 3.3 V
VCC = 3.3 V
0
0.4
3.6
V
V
AUX Channel DC common mode
voltage for AUXn
2.7
Copyright © 2017–2019, Texas Instruments Incorporated
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TDP142
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www.ti.com.cn
6.8 Timing Requirements
MIN
NOM
MAX
UNIT
tDIFF_DLY
tR, tF
Differential Propagation Delay
See 图 7
300
2.6
ps
20%-80% of differential
voltage measured 1 inch
from the output pin
Output Rise/Fall time (see 图 9)
40
ps
ps
20%-80% of differential
voltage measured 1 inch
from the output pin
tRF_MM
Output Rise/Fall time mismatch
6.9 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
10
UNIT
DPEN and HPDIN
tDPEN_DEBOUNCE DPEN and HPDIN debounce time when transitioning from H to L.
2
ms
I2C (Refer to 图 6)
fSCL
tBUF
I2C clock frequency
1
MHz
µs
Bus free time between START and STOP conditions
0.5
Hold time after repeated START condition. After this period, the first
clock pulse is generated
tHDSTA
0.26
µs
tLOW
Low period of the I2C clock
High period of the I2C clock
Setup time for a repeated START condition
Data hold time
0.5
0.26
0.26
0
µs
µs
µs
μs
ns
ns
tHIGH
tSUSTA
tHDDAT
tSUDAT
tR
Data setup time
50
Rise time of both SDA and SCL signals
120
120
20 × (V(I2C)/5.5
V)
tF
Fall time of both SDA and SCL signals
ns
tSUSTO
Cb
Setup time for STOP condition
Capacitive load for each bus line
0.26
μs
150
pF
8
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TDP142
www.ti.com.cn
ZHCSGQ7C –SEPTEMBER 2017–REVISED MAY 2019
6.10 Typical Characteristics
15
10
5
1.6
1.4
1.2
1
0
0.8
0.6
0.4
0.2
0
-5
EQ0
EQ1
EQ2
EQ3
EQ4
EQ5
EQ6
EQ7
EQ8
EQ9
EQ10
EQ11
EQ12
EQ13
EQ14
EQ15
EQ0
EQ1
EQ2
EQ3
EQ4
EQ5
EQ6
EQ7
EQ8
EQ9
EQ10
EQ11
EQ12
EQ13
EQ14
EQ15
-10
-15
0.01
0.1
1
10
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
Frequency (GHz)
Differential Input Voltage (V)
D001
D004
图 1. DisplayPort EQ Settings Curves
图 2. DisplayPort Linearity Curves at 4.05 GHz
5
0
0
-5
OUT DP0
OUT DP1
OUT DP2
OUT DP3
-5
-10
-15
-20
-25
-30
-35
-40
-10
-15
-20
-25
-30
DP0
DP1
DP2
DP3
0.01
0.1
1
10 20
0.01
0.1
1
10 20
Frequency (GHz)
Frequency (GHz)
D003
D004
图 3. Input Return Loss Performance
图 4. Output Return Loss Performance
Time (20.57 ps/Div)
图 5. DisplayPort HBR3 Eye-Pattern Performance with 12-inch Input PCB Trace at 8.1 Gbps
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7 Parameter Measurement Information
70%
SDA
30%
t
t
t
F
HDSTA
R
tHIGH
t
t
LOW
BUF
70%
30%
SCL
S
P
P
S
t
t
SUSTO
t
t
SUDAT
HDDAT
HDSTA
t
SUSTA
图 6. I2C Timing Diagram Definitions
IN
T
T
DIFF_DLY
DIFF_DLY
OUT
图 7. Propagation Delay
IN+
V
Vcm
RX-LFPS-DET-DIFF-PP
IN-
T
T
IDLEEntry
IDLEExit
OUT+
Vcm
OUT-
图 8. Electrical Idle Mode Exit and Entry Delay
80%
20%
t
r
t
f
图 9. Output Rise and Fall Times
10
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8 Detailed Description
8.1 Overview
The TDP142 is a DisplayPortTM linear re-driver that supports up to 8.1 Gbps for each lane. Additionally, its
transparency to the DP link training makes TDP142 a position independent device, suitable for source/sink or
cable application.
The TDP142 helps the system to pass compliance of both transmitter and receiver for DisplayPort version 1.4
HBR3. The re-driver recovers incoming data by applying equalization that compensates for channel loss, and
drives out signals with a high differential voltage. Each channel has a receiver equalizer with selectable gain
settings. The equalization should be set based on the amount of insertion loss before the TDP142 receivers. The
equalization control can be controlled by DPEQ[1:0] pins or I2C registers.
The device ultra-low-power architecture operates at a 3.3-V power supply and achieves enhanced performance.
Also, it comes in a commercial temperature range and industrial temperature range.
8.2 Functional Block Diagram
INDP0p
INDP0n
OUTDP0p
OUTDP0n
Driver
EQ
DPEQ_SEL
INDP1p
INDP1n
OUTDP1p
OUTDP1n
Driver
EQ
EQ
DPEQ_SEL
OUTDP2p
OUTDP2n
INDP2p
INDP2n
Driver
DPEQ_SEL
INDP3p
INDP3n
OUTDP3p
OUTDP3n
Driver
EQ
DPEQ_SEL
DPEQ_SEL
DPEQ0/A1
DPEQ1
A0
Control Logic and Registers
I2C_EN
TEST1/SCL
I2C
Slave
HPDIN/RSVD9
TEST2/SDA
DPEN/HPDIN
SNOOPENZ/RSVD8
AUXp
AUXn
AUX
Snooping
VREG
VCC
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8.3 Feature Description
8.3.1 DisplayPort
The TDP142 supports up to 4 DisplayPort lanes at data rates up to 8.1Gbps (HBR3). The TDP142 monitors the
native AUX traffic as it traverses between DisplayPort source and DisplayPort sink. For the purposes of reducing
power, the TDP142 manages the number of active DisplayPort lanes based on the content of the AUX
transactions. The TDP142 snoops native AUX writes to DisplayPort sink’s DPCD registers 0x00101
(LANE_COUNT_SET) and 0x00600 (SET_POWER_STATE). TDP142 disables/enables lanes based on value
written to LANE_COUNT_SET. The TDP142 disables all lanes when SET_POWER_STATE is in the D3.
Otherwise active lanes will be based on value of LANE_COUNT_SET.
DisplayPort AUX snooping is enabled by default but can be disabled by changing the AUX_SNOOP_DISABLE
register. Once AUX snoop is disabled, management of TDP142 DisplayPort lanes are controlled through various
configuration registers. When TDP142 is enabled for GPIO mode (I2C_EN = "0"), the SNOOPENZ pin can be
used to disable AUX snooping. When SNOOPENZ pin is high, the AUX snooping functionality is disabled and all
four DisplayPort lanes will be active.
8.3.2 4-level Inputs
The TDP142 has (I2C_EN, A0, and DPEQ[1:0]) 4-level inputs pins that are used to control the equalization gain
and place TDP142 into different modes of operation. These 4-level inputs utilize a resistor divider to help set the
4 valid levels and provide a wider range of control settings. There are internal pull-up and pull-down and combine
with the external resistor connection to achieve the desired voltage level.
表 1. 4-Level Control Pin Settings
LEVEL
SETTINGS
Option 1: Tie 1 kΩ 5% to GND.
Option 2: Tie directly to GND.
0
R
F
Tie 20 kΩ 5% to GND.
Float (leave pin open)
Option 1: Tie 1 kΩ 5% to VCC
.
1
Option 2: Tie directly to VCC
.
spacer
注
All four-level inputs are latched on rising edge of internal reset. After tcfg_hd, the internal
pull-up and pull-down resistors will be isolated in order to save power.
8.3.3 Receiver Linear Equalization
The purpose of receiver equalization is to compensate for channel insertion loss and inter-symbol interference in
the system before the input of the TDP142. The receiver overcomes these losses by attenuating the low
frequency components of the signals with respect to the high frequency components. The proper gain setting
should be selected to match the channel insertion loss before the input of the TDP142 receivers. Two 4-level
inputs pins enable up to 16 possible equalization settings. The TDP142 also provides the flexibility of adjusting
settings through I2C registers.
12
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8.4 Device Functional Modes
8.4.1 Device Configuration in GPIO Mode
The TDP142 is in GPIO configuration when I2C_EN = “0”. The DPEN pin controls whether DisplayPort is
enabled and SNOOPENZ pin controls whether AUX snoop mode is enabled.
8.4.2 Device Configuration In I2C Mode
The TDP142 is in I2C mode when I2C_EN is not equal to “0”. The same configurations defined in GPIO mode
are also available in I2C mode. The TDP142 DisplayPort configuration is programmed based on the
Programming section .
8.4.3 Linear EQ Configuration
The receiver equalization gain value can be controlled either through I2C registers or through GPIOs. 表 2 details
the gain value for each available combination when TDP142 is in GPIO mode. The I2C mode can do the same
option or even individual lane EQ setting by updating registers DP0EQ_SEL, DP1EQ_SEL, DP2EQ_SEL, and
DP3EQ_SEL.
表 2. TDP142 Receiver Equalization GPIO Control
ALL DISPLAYPORT LANES
Equalization Setting #
DPEQ1 PIN LEVEL
DPEQ0 PIN LEVEL
EQ GAIN at 4.05 GHz (dB)
0
1
0
0
0
R
F
1
1.0
3.3
2
0
4.9
3
0
6.5
4
R
R
R
R
F
F
F
F
1
0
7.5
5
R
F
1
8.6
6
9.5
7
10.4
11.1
11.7
12.3
12.8
13.2
13.6
14.0
14.4
8
0
9
R
F
1
10
11
12
13
14
15
0
1
R
F
1
1
1
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8.4.4 Operation Timing – Power Up
TDP142
VCC
t
d_pg
Internal
Power Good
t
cfg_su
t
cfg_hd
CFG pins
图 10. Power-Up Timing
表 3. Power-Up Timing(1)(2)
PARAMETER
MIN
MAX
UNIT
µs
td_pg
VCC (minimum) to Internal Power Good asserted high
CFG(1) pins setup(2)
500
tcfg_su
50
10
µs
tcfg_hd
CFG(1) pins hold
µs
tVCC_RAMP
VCC supply ramp requirement
100
ms
(1) Following pins comprise CFG pins: I2C_EN, DPEQ[1:0].
(2) Recommend CFG pins are stable when VCC is at min.
14
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8.5 Programming
For further programmability, the TDP142 can be controlled using I2C. When I2C_EN !=0, the SCL and SDA pins
are used for I2C clock and I2C data respectively.
表 4. TDP142 I2C Target Address
DPEQ0/A1
PIN LEVEL
A0
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (W/R)
PIN LEVEL
0
0
0
R
F
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0
0
R
R
R
R
F
F
F
F
1
0
R
F
1
0
R
F
1
0
1
R
F
1
1
1
The following procedure should be followed to write to TDP142 I2C registers:
1. The master initiates a write operation by generating a start condition (S), followed by the TDP142 7-bit
address and a zero-value “W/R” bit to indicate a write cycle.
2. The TDP142 acknowledges the address cycle.
3. The master presents the sub-address (I2C register within TDP142) to be written, consisting of one byte of
data, MSB-first.
4. The TDP142 acknowledges the sub-address cycle.
5. The master presents the first byte of data to be written to the I2C register.
6. The TDP142 acknowledges the byte transfer.
7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing
with an acknowledge from the TDP142.
8. The master terminates the write operation by generating a stop condition (P).
The following procedure should be followed to read the TDP142 I2C registers:
1. The master initiates a read operation by generating a start condition (S), followed by the TDP142 7-bit
address and a one-value “W/R” bit to indicate a read cycle.
2. The TDP142 acknowledges the address cycle.
3. The TDP142 transmit the contents of the memory registers MSB-first starting at register 00h or last read sub-
address+1. If a write to the T I2C register occurred prior to the read, then the TDP142 shall start at the sub-
address specified in the write.
4. The TDP142 shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after
each byte transfer; the I2C master acknowledges reception of each data byte transfer.
5. If an ACK is received, the TDP142 transmits the next byte of data.
6. The master terminates the read operation by generating a stop condition (P).
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The following procedure should be followed for setting a starting sub-address for I2C reads:
1. The master initiates a write operation by generating a start condition (S), followed by the TDP142 7-bit
address and a zero-value “W/R” bit to indicate a write cycle.
2. The TDP142 acknowledges the address cycle.
3. The master presents the sub-address (I2C register within TDP142) to be written, consisting of one byte of
data, MSB-first.
4. The TDP142 acknowledges the sub-address cycle.
5. The master terminates the write operation by generating a stop condition (P).
注
If no sub-addressing is included for the read procedure, and reads start at register offset
00h and continue byte by byte through the registers until the I2C master terminates the
read operation. If a I2C address write occurred prior to the read, then the reads start at the
sub-address specified by the address write.
表 5. Register Legend
ACCESS TAG
NAME
Read
MEANING
R
W
S
The field may be read by software
The field may be written by software
Write
Set
The field may be set by a write of one. Writes of zeros to the field have no effect.
The field may be cleared by a write of one. Write of zero to the field have no effect.
Hardware may autonomously update this field.
C
Clear
U
Update
No Access
NA
Not accessible or not applicable
16
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8.6 Register Maps
8.6.1 General Register (address = 0x0A) [reset = 00000001]
图 11. General Registers
7
6
5
4
3
2
1
0
Reserved
R
SWAP_HPDIN EQ_OVERRID HPDIN_OVRRI
Reserved.
CTLSEL[1:0].
R/W
E
DE
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 6. General Registers
Bit
Field
Type
Reset
Description
7:6
Reserved
R
00
Reserved.
0 – HPDIN is in default location (Default)
5
4
SWAP_HPDIN
EQ_OVERRIDE
R/W
R/W
0
0
1 – HPDIN location is swapped (PIN 23 to PIN 32, or PIN 32 to
PIN 23).
Setting of this field will allow software to use EQ settings from
registers instead of value sample from pins.
0 – EQ settings based on sampled state of the EQ pins
(DPEQ[1:0]).
1 – EQ settings based on programmed value of each of the EQ
registers
0 – HPD based on state of HPDIN pin (Default)
1 – HPD high.
3
2
HPDIN_OVRRIDE
Reserved
R/W
R/W
0
0
Reserved.
Upon power-on, software must write 2'b10 to enable DisplayPort
functionality. If DisplayPort functionality is not required, then
software must write 2'b00 to disable DisplayPort.
00 - Shutdown. DP disabled and lowest power state.
01 - DP disabled but not in lowest power state.
10 - DP enabled
1:0
CTLSEL[1:0]
R/W
01
11 - Reserved.
8.6.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]
图 12. DisplayPort Control/Status Registers (0x10)
7
6
5
4
3
2
1
0
DP1EQ_SEL
R/W/U
DP0EQ_SEL
R/W/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 7. DisplayPort Control/Status Registers (0x10)
Bit
Field
Type
Reset
Description
Field selects between 0 to 14dB of EQ for DP lane 1. When
EQ_OVERRIDE = 1’b0, this field reflects the sampled state of
DPEQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can
change the EQ setting for DP lane 1 based on value written to
this field.
7:4
DP1EQ_SEL
R/W/U
0000
Field selects between 0 to 14dB of EQ for DP lane 0. When
EQ_OVERRIDE = 1’b0, this field reflects the sampled state of
DPEQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can
change the EQ setting for DP lane 0 based on value written to
this field.
3:0
DP0EQ_SEL
R/W/U
0000
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8.6.3 DisplayPort Control/Status Registers (address = 0x11) [reset = 00000000]
图 13. DisplayPort Control/Status Registers (0x11)
7
6
5
4
3
2
1
0
DP3EQ_SEL
R/W/U
DP2EQ_SEL
R/W/U
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 8. DisplayPort Control/Status Registers (0x11)
Bit
Field
Type
Reset
Description
Field selects between 0 to 14dB of EQ for DP lane 3. When
EQ_OVERRIDE = 1’b0, this field reflects the sampled state of
DPEQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can
change the EQ setting for DP lane 3 based on value written to
this field.
7:4
DP3EQ_SEL
R/W/U
0000
Field selects between 0 to 14dB of EQ for DP lane 2. When
EQ_OVERRIDE = 1’b0, this field reflects the sampled state of
DPEQ[1:0] pins. When EQ_OVERRIDE = 1’b1, software can
change the EQ setting for DP lane 2 based on value written to
this field.
3:0
DP2EQ_SEL
R/W/U
0000
8.6.4 DisplayPort Control/Status Registers (address = 0x12) [reset = 00000000]
图 14. DisplayPort Control/Status Registers (0x12)
7
Reserved
R
6
5
4
3
2
LANE_COUNT_SET
RU
1
0
SET_POWER_STATE
RU
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 9. DisplayPort Control/Status Registers (0x12)
Bit
Field
Type
Reset
Description
7
Reserved
R
0
Reserved.
This field represents the snooped value of the AUX write to
DPCD address 0x00600. When AUX_SNOOP_DISABLE = 1’b0,
the TDP142 will enable/disable DP lanes based on the snooped
value. When AUX_SNOOP_DISABLE = 1’b1, then DP lane
enable/disable are determined by state of DPx_DISABLE
registers, where x = 0, 1, 2, or 3. This field is reset to 2’b00 by
hardware when CTLSEL1 registers changes from a 1’b1 to a
1’b0.
6:5
4:0
SET_POWER_STATE
LANE_COUNT_SET
R/U
R/U
00
This field represents the snooped value of AUX write to DPCD
address 0x00101 register. When AUX_SNOOP_DISABLE =
1’b0, TDP142 will enable DP lanes specified by the snoop value.
Unused DP lanes will be disabled to save power. When
AUX_SNOOP_DISABLE = 1’b1, then DP lanes enable/disable
are determined by DPx_DISABLE registers, where x = 0, 1, 2, or
3. This field is reset to 0x0 by hardware when CTLSEL1 register
changes from a 1’b1 to a 1’b0.
00000
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8.6.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000]
图 15. DisplayPort Control/Status Registers (0x13)
7
6
5
4
3
2
1
0
AUX_SNOOP_
DISABLE
Reserved
AUX_SBU_OVR
DP3_DISABLE DP2_DISABLE DP1_DISABLE DP0_DISABLE
R/W
R
R/W
R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
表 10. DisplayPort Control/Status Registers (0x13)
Bit
Field
Type
Reset
Description
0 – AUX snoop enabled. (Default)
1 – AUX snoop disabled.
7
AUX_SNOOP_DISABLE
R/W
0
6
Reserved
Reserved
R
0
Reserved.
Reserved.
5:4
R/W
00
When AUX_SNOOP_DISABLE = 1’b1, this field can be used to
enable or disable DP lane 3. When AUX_SNOOP_DISABLE =
1’b0, changes to this field will have no effect on lane 3
functionality.
0 – DP Lane 3 Enabled (default)
1 – DP Lane 3 Disabled.
3
2
1
0
DP3_DISABLE
DP2_DISABLE
DP1_DISABLE
DP0_DISABLE
R/W
R/W
R/W
R/W
0
0
0
0
When AUX_SNOOP_DISABLE = 1’b1, this field can be used to
enable or disable DP lane 2. When AUX_SNOOP_DISABLE =
1’b0, changes to this field will have no effect on lane 2
functionality.
0 – DP Lane 2 Enabled (default)
1 – DP Lane 2 Disabled.
When AUX_SNOOP_DISABLE = 1’b1, this field can be used to
enable or disable DP lane 1. When AUX_SNOOP_DISABLE =
1’b0, changes to this field will have no effect on lane 1
functionality.
0 – DP Lane 1 Enabled (default)
1 – DP Lane 1 Disabled.
DISABLE. When AUX_SNOOP_DISABLE = 1’b1, this field can
be used to enable or disable DP lane 0. When
AUX_SNOOP_DISABLE = 1’b0, changes to this field will have
no effect on lane 0 functionality.
0 – DP Lane 0 Enabled (default)
1 – DP Lane 0 Disabled.
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TDP142 is a linear redriver designed specifically to compensate the inter-symbol interference (ISI) jitter
caused by signal attenuation through a passive medium like PCB traces and cable. It can be used in Source,
Sink, and cable applications, where the device is transparent to the link training. For illustrating purposes, this
section shows the implementations of Source application and Sink application. 图 16 and 图 17 are the high level
block diagram for DisplayPort Source side application and DisplayPort Sink side application respectively, where
the TDP142 is snooping both channels of AUX signal and HPD signal.
PCB trace of Length B
PCB trace of Length A
ML0_OUT
ML0_IN
ML1_OUT
ML2_OUT
ML1_IN
ML2_IN
TDP142
ML3_OUT
ML3_IN
DP
Receptacle
GPU
3.3 V
AUX
HPD
3.3 V
Power
Source
Copyright © 2017, Texas Instruments Incorporated
图 16. Source Application for TDP142
20
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Application Information (接下页)
PCB trace of Length D
PCB trace of Length C
ML0_OUT
ML0_IN
ML1_OUT
ML2_OUT
ML1_IN
ML2_IN
TDP142
ML3_OUT
ML3_IN
DP
Receptacle
Scaler
3.3 V
AUX
HPD
3.3 V
Power
Source
Copyright © 2017, Texas Instruments Incorporated
图 17. The Implementation of Sink Application
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9.2 Typical Application
9.2.1 Source Application Implementation
图 18 shows the schematic for the Source side application. The TDP142 is placed between the DisplayPort
Graphics Processor Unit (GPU) and the DisplayPort receptacle. The TDP142 monitors AUX traffic for power
management purposes when SNOOPENZ is low.
3P3V
C1
10uF
C2
0.1uF
C3
0.1uF
C4
0.1uF
C5
0.1uF
3V3P
Board_3P3V
FB
220 ohm
U1
GPU with Dual mode support
AUX_P
25 AUX_N
1
6
24
VCC
VCC
VCC
VCC
AUXP
AUXN
20
28
ML0_P
ML0_N
C6
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C13
C14
C15
C16
C17
C18
C19
C20
0.1uF OUTDP0P
0.1uF OUTDP0N
0.1uF OUTDP1P
0.1uF OUTDP1N
0.1uF OUTDP2P
0.1uF OUTDP2N 3.3V
0.1uF OUTDP3P
0.1uF OUTDP3N
OUTDP1P
OUTDP1N
4
6
ML1_P
ML1_N
9
40
39
13 CAD R9
14
1M
5M
INDP0P
INDP0N
OUTDP0P
OUTDP0N
CONFIG1
CONFIG2
ML1_P
ML1_N
C7
10
R10
OUTDP0P
OUTDP0N
1
3
ML0_P
ML0_N
C8
12
13
37
36
19
INDP1P
INDP1N
OUTDP1P
OUTDP1N
RTN
ML2_P
ML2_N
C9
OUTDP3P10
OUTDP3N12
ML3_P
ML3_N
15
16
33
34
2
INDP2P
INDP2N
OUTDP2P
OUTDP2N
GND
GND
GND
GND
GND
GND
GND
GND
GND
ML3_P
ML3_N
C10
C11
C12
C23
5
3P3V
OUTDP2P
OUTDP2N
7
9
8
ML2_P
ML2_N
18
19
30
31
11
16
21
22
23
24
INDP3P
INDP3N
OUTDP3P
OUTDP3N
R1
100k
20
DP_PWR
I2C_EN
17
I2C_EN
C21
C22
0.1uF
0.1uF
AUX_N
3
AUX_P
AUX_N
15
17
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD10
RSVD11
AUX_P
AUX_N
AUX_N
AUX_P
21
22
4
TEST1/SCL
TEST2/SDA
AUX_P
3P3V
R5
R6
R7
10k
10k
1k
5
7
HPDIN
18
HPD
R2
100k
A0
DPEQ2
DPEQ1
11
14
2
8
A0
R3
2k
R4
2k
DDC_EN
DDC_EN
26
27
35
38
DPEQ0/A1
DPEQ1
DDC_EN
SDA
3V3P
DisplayPort Receptacle
GND
GND
AUX_N
AUX_P
R8
10k
23
32
DPEN/HPDIN
HPDIN
HPDIN/RSVD9
SNOOPENZ/RSVD8
SCL
SNOOPENZ 29
41
TPAD
CAD
CAD
HPDIN
GND
TDP142RNQ
HPD
GND
3P3V
3P3V
R12
1k
R15
1k
GND
SN74AHC1G125DBVR
U2
I2C_EN
DPEQ0
DPEQ1
SNOOPENZ
CAD
4
2
1
R11
1k
R13
1k
R14
20k
R16
1k
R17
20k
3V3P
GND
GND
GND
Copyright © 2017, Texas Instruments Incorporated
图 18. The Block Diagram of DisplayPort Source Application
9.2.1.1 Design Requirement
The TDP142 can be designed into many types of applications. All applications have certain requirements for the
system to work properly. For example, source application uses different hardware configuration on the HPD
channel and AUX channel from a sink application. The device can be configured by using I2C. However, the
GPIO configuration is provided as I2C is not available in all cases. Additionally, because sources may have
different naming conventions, please confirm the link between source and receptacle is correctly mapped through
the TDP142.
表 11. Design Parameters
PARAMETER
VALUE
Maximum Operating data rate
(RBR, HBR, HBR2, or HBR3)
HBR3 (8.1 Gbps)
Supply voltage
3.3V
Trace length/width of A
Trace length/width of B
12 inch /6 mil width
2 inch/ 6 mil width
Main link AC decoupling capacitor
(75 nF to 265 nF)
Recommend 100nF
Control mode (I2C or GPIO)
GPIO (I2C_EN = 0)
Dual Mode DisplayPort Support (Yes/No)
Yes. SNOOPENZ must be connected to CONFIG1 thru a buffer.
22
版权 © 2017–2019, Texas Instruments Incorporated
TDP142
www.ti.com.cn
ZHCSGQ7C –SEPTEMBER 2017–REVISED MAY 2019
9.2.1.2 Detail Design Procedure
Designing in the TDP142 requires the following:
•
Determine the loss profile on the DisplayPort input (A) and output (B) channels. See 图 20 for 6 mil trace
insertion loss.
•
Based upon the loss profile, determine the optimal configuration for the TDP142, to pass electrical
compliance. DPEQ[1:0] must be set to appropriate value. For this case, 12-in of FR4 trace approximately
equates to 8 dB loss at 4.05 GHz. Therefore, DPEQ1 should be tied 20k ohms to ground and DPEQ0 should
be tied 1 kΩ to ground.
•
See 图 18 for information of Source application on using the AC coupling capacitors, control pin resistors, and
for recommended decouple capacitors from VCC pins to ground.
–
AUX: AUXP should have a 100 kΩ pull-down resistor and AUXN should have a 100 kΩ pull-up resistor.
These 100 kΩ resistors must be on the TDP142 side of the 100 nF capacitors.
–
HPDIN is used to enable or disable DisplayPort functionality for power saving. The HPD signal should be
routed to either pin 23 or pin 32 based on the GPIO/I2C mode.
表 12. HPD GPIO/I2C Selection
MODE
HPD
Pin 32
Pin 23
GPIO (I2C_EN = 0)
I2C (I2C_EN != 0)
spacer
–
For the application supporting Dual mode DisplayPort: SNOOPENZ pin must be connected to the
CONFIG1 on DisplayPort Receptacle through a buffer like the SN74AHC125. The buffer is needed
because the internal pulldown on SNOOPENZ pin is too strong to register a valid VIH when a Dual mode
adapter is plugged into the DisplayPort receptacle.
•
•
Configure the TDP142 using the GPIO terminals or the I2C interface:
–
–
GPIO – Using the terminals DPEQ0 and DPEQ1.
I2C - Refer to the I2C Register Maps and the Programming section for a detail configuration procedures.
The thermal pad must be connected to ground.
版权 © 2017–2019, Texas Instruments Incorporated
23
TDP142
ZHCSGQ7C –SEPTEMBER 2017–REVISED MAY 2019
www.ti.com.cn
9.2.2 Sink Application Implementation
图 19 is the schematic for the Sink application, and the left side of TDP142 is connected to DisplayPort
receptacle and the right side of TDP142 is connected to Scaler or DisplayPort sink.
3P3V
C1
10uF
C2
0.1uF
C3
0.1uF
C4
0.1uF
C5
0.1uF
3V3P
Board_3P3V
DisplayPort Sink
FB
220 ohm
U1
ML0_P
ML0_N
AUX_P
AUX_N
1
24
25
VCC
AUXP
AUXN
Note:
AC-coupled is needed if there is no
ac-coupled on the other end of source side.
6
VCC
20
VCC
VCC
28
24
23
22
21
16
11
8
1
3
ML3_N
ML3_P
ML0_P
C6
0.1uF OUTDP0P
0.1uF OUTDP0N
0.1uF OUTDP1P
0.1uF OUTDP1N
0.1uF OUTDP2P
0.1uF OUTDP2N
0.1uF OUTDP3P
0.1uF OUTDP3N
GND
GND
GND
GND
GND
GND
GND
GND
GND
ML3_N
ML3_P
ML1_P
ML1_N
9
40
39
INDP0P
INDP0N
OUTDP0P
OUTDP0N
ML0_N
ML1_P
ML1_N
ML2_P
ML2_N
ML3_P
ML3_N
10
C7
4
6
ML2_N
ML2_P
ML2_N
ML2_P
C8
12
13
37
36
INDP1P
INDP1N
OUTDP1P
OUTDP1N
ML2_P
ML2_N
ML1_N
ML1_P
C9
7
9
ML1_N
ML1_P
5
15
16
33
34
INDP2P
INDP2N
OUTDP2P
OUTDP2N
2
C10
C11
C12
C13
10 ML0_N
12 ML0_P
ML0_N
ML0_P
18
19
30
31
INDP3P
INDP3N
OUTDP3P
OUTDP3N
ML3_P
ML3_N
19
20
RTN
CAD R1
R2
1M
5M
13
14
CONFIG1
CONFIG2
I2C_EN
3P3V
17
I2C_EN
3
DP_PWR
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD10
RSVD11
R6
1M
15
17
AUX_N
AUX_P
21
22
4
AUX_P
AUX_N
TEST1/SCL
TEST2/SDA
R3
R4
R5
10k
10k
1k
5
7
AUX_P
AUX_N
C14
C15
0.1uF
0.1uF
AUX_P
AUX_N
18
HPDIN
A0
11
8
HPD
A0
DPEQ2 14
DPEQ1
26
27
35
38
DPEQ0/A1
DPEQ1
DisplayPort Recepticle Sink
3V3P
2
R7
1M
GND
R15
10k
HPDIN
23
32
29
DPEN/HPDIN
HPD
HPDIN
CAD
HPDIN/RSVD9
SNOOPENZ/RSVD8
41
TPAD
GND
GND
TDP142RNQ
GND
GND
3P3V
3P3V
R9
1k
R12
1k
I2C_EN
DPEQ0
DPEQ1
R8
1k
R10
1k
R11
20k
R13
1k
R14
20k
GND
GND
GND
Copyright © 2017, Texas Instruments Incorporated
图 19. The Block diagram of DisplayPort Sink Application
9.2.2.1 Design Requirements
For this design example, the parameters listed in 表 13 are used.
表 13. Design Parameters
PARAMETER
VALUE
Maximum Operating data rate
(RBR, HBR, HBR2, or HBR3)
HBR3 (8.1Gbps)
Supply voltage
3.3V
Trace length/width of C
Trace length/width of D
12 inch/ 6 mil
2 inch/ 6 mil
Main link AC decoupling capacitor
(75 nF to 265 nF)
Recommend 100 nF
GPIO (I2C_EN = 0)
Control mode (I2C or GPIO)
24
版权 © 2017–2019, Texas Instruments Incorporated
TDP142
www.ti.com.cn
ZHCSGQ7C –SEPTEMBER 2017–REVISED MAY 2019
9.2.2.2 Detailed Design Procedure
The design procedure for Sink application is listed as follows:
•
•
•
Determine the loss profile on the DP input (C) and output (D) channels and cables. See 图 20 for 6 mil trace
insertion loss.
Based upon the loss profile, determine the optimal configuration for the TDP142, to pass electrical
compliance.
See 图 19 for information of Sink application on using the AC coupling capacitors, control pin resistors, and
for recommended decouple capacitors from VCC pins to ground.
–
AUX: AUXP has a 1 MΩ pull-up resistor and AUXN should have a 1 MΩ pull-down resistor. Theses 1 MΩ
resistors must be on the TDP142 side of the 100 nF capacitors.
–
HPDIN: The HPD signal should be routed to either pin 23 or pin 32 based on the GPIO/I2C mode. In that
way, the TDP142 will always be able to conserve power when a source is not connected.
表 14. HPD GPIO/I2C Selection
MODE
HPD
Pin 32
Pin 23
GPIO (I2C_EN = 0)
I2C (I2C_EN != 0)
spacer
Configure the TDP142 using the GPIO terminals or the I2C interface:
•
•
–
–
GPIO – Using the terminals DPEQ0 and DPEQ1.
It is recommended to start a higher equalization value like 13 dB and 15 dB first and adjust the value if
necessary.
–
I2C - Refer to the I2C Register Maps and the Programming section for a detail configuration procedures.
The thermal pad must be connected to ground.
9.2.3 Application Curve
0
-5
-10
-15
-20
-25
-30
6 mil Loss at 2.7 GHz
4 mil Loss at 2.7 GHz
6 mil Loss at 4.05 GHz
4 mil Loss at 4.05 GHz
0
5
10
15
20
25
30
35
40
Length of Trace (inch)
D009
图 20. Insertion Loss of FR4 PCB Traces
10 Power Supply Recommendations
The TDP142 is designed to operate with a 3.3-V power supply. Levels above those listed in the Absolute
Maximum Ratings table should not be used. If using a higher voltage system power supply, a voltage regulator
can be used to step down to 3.3 V. Decoupling capacitors should be used to reduce noise and improve power
supply integrity. A 0.1-µF capacitor should be used on each power pin.
版权 © 2017–2019, Texas Instruments Incorporated
25
TDP142
ZHCSGQ7C –SEPTEMBER 2017–REVISED MAY 2019
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
1. INDP[3:0]P/N and OUTDP[3:0]P/N pairs should be routed with controlled 100-Ω differential impedance
(±10%).
2. Keep away from other high speed signals.
3. Intra-pair routing should be kept to within 5 mils.
4. Inter-pair skew should be kept within 2 UI according to the DisaplyPort Design Guide
5. Length matching should be near the location of mismatch.
6. Each pair should be separated at least by 3 times the signal trace width.
7. The use of bends in differential traces should be kept to a minimum. When bends are used, the number of
left and right bends should be as equal as possible and the angle of the bend should be ≥ 135 degrees. This
will minimize any length mismatch causes by the bends and therefore minimize the impact bends have on
EMI.
8. Route all differential pairs on the same of layer.
9. The number of VIAS should be kept to a minimum. It is recommended to keep the VIAS count to 2 or less.
10. Refer to figure 28, the layout might face signal crossing on OUTDP2 and OUTDP3 due to mismatched
order between the output pins of the device and the connector. One of the solutions is to do polarity swap on
the input of the device when GPU is BGA package. It can minimize the number of VIAS being used.
11. Keep traces on layers adjacent to ground plane.
12. Do NOT route differential pairs over any plane split.
13. Adding Test points will cause impedance discontinuity, and therefore, negatively impact signal performance.
If test points are used, they should be placed in series and symmetrically. They must not be placed in a
manner that causes a stub on the differential pair.
11.2 Layout Example
DPEQ1
INDP0
A0
OUTDP0
OUTDP1
INDP1
DPEQ0/A1
OUTDP2
HPDIN
INDP2
I2CEN
OUTDP3
SNOOPENZ
INDP3
SCL SDA DPEN
AUX
图 21. Layout Example
26
版权 © 2017–2019, Texas Instruments Incorporated
TDP142
www.ti.com.cn
ZHCSGQ7C –SEPTEMBER 2017–REVISED MAY 2019
Layout Example (接下页)
Figure 22 demonstrates the solution of mismatched order between the output of the device and the DisplayPort
connector for the source using BGA package. Top image of Figure 22 shows the crossing section between
TDP142 and connector. Usually, Vias would be applied to avoid the cross, but using Via can attenuate the signal
integrity. Therefore, the polarity swap would be implemented at the input of TDP142. The bottom image shows
there is no more crossing section between the TDP142 and connector, which can minimize the number of Vias
being used. Note that, the solution is only useful for the source using BGA package.
TDP142
GPU-BGA package
Connector
DP0P
DP0P
DP0P
P
DP0
N
DP0N
DP1P
DP0N
DP1P
DP0N
DP1P
P
DP1
N
DP1N
DP2P
DP1N
DP2N
DP1N
DP2P
P
DP2
N
DP2N
DP3P
DP3N
DP2P
DP2N
DP3N
DP3P
DP3P
DP3N
P
DP3
N
TDP142
Connector
GPU-BGA package
DP0P
DP0P
DP0P
P
DP0
N
DP0N
DP1P
DP0N
DP1P
DP0N
DP1P
P
DP1
N
DP1N
DP2P
DP1N
DP2N
DP1N
DP2P
P
DP2N
DP3P
DP3N
DP2P
DP2N
N
P
N
DP2
DP3
DP3N
DP3P
DP3P
DP3N
图 22. Layout Example, Top: signal crossing on the output. Bottom: INDP2 and INDP3 Polarity Swap
版权 © 2017–2019, Texas Instruments Incorporated
27
TDP142
ZHCSGQ7C –SEPTEMBER 2017–REVISED MAY 2019
www.ti.com.cn
12 器件和文档支持
12.1 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。
表 15. 相关链接
器件
产品文件夹
单击此处
单击此处
立即订购
单击此处
单击此处
技术文档
单击此处
单击此处
工具与软件
单击此处
单击此处
支持和社区
单击此处
单击此处
TDP142
TDP142I
12.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 商标
E2E is a trademark of Texas Instruments.
DisplayPort is a trademark of VESA.
12.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
28
版权 © 2017–2019, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TDP142IRNQR
TDP142IRNQT
TDP142RNQR
TDP142RNQT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
WQFN
RNQ
RNQ
RNQ
RNQ
40
40
40
40
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
0 to 70
TDP142
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
TDP142
TDP142
TDP142
0 to 70
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jun-2022
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TDP142IRNQR
TDP142IRNQT
TDP142RNQR
TDP142RNQT
WQFN
WQFN
WQFN
WQFN
RNQ
RNQ
RNQ
RNQ
40
40
40
40
3000
250
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
4.3
4.3
4.3
4.3
6.3
6.3
6.3
6.3
1.1
1.1
1.1
1.1
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q2
Q2
Q2
Q2
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TDP142IRNQR
TDP142IRNQT
TDP142RNQR
TDP142RNQT
WQFN
WQFN
WQFN
WQFN
RNQ
RNQ
RNQ
RNQ
40
40
40
40
3000
250
367.0
210.0
367.0
210.0
367.0
185.0
367.0
185.0
35.0
35.0
35.0
35.0
3000
250
Pack Materials-Page 2
PACKAGE OUTLINE
RNQ0040A
WQFN - 0.8 mm max height
S
C
A
L
E
2
.
5
0
0
PLASTIC QUAD FLATPACK - NO LEAD
6.1
5.9
B
A
PIN 1 INDEX AREA
4.1
3.9
C
0.8 MAX
SEATING PLANE
0.08
0.05
0.00
4.7±0.1
2X 4.4
(0.2) TYP
9
20
EXPOSED
THERMAL PAD
36X 0.4
8
21
2X
2.8
2.7±0.1
1
28
0.25
40X
0.15
29
40
PIN 1 ID
0.1
C A
B
0.5
0.3
(OPTIONAL)
40X
0.05
4222125/B 01/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RNQ0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(4.7)
2X (2.1)
6X (0.75)
40
29
40X (0.6)
1
28
40X (0.2)
SYMM
4X
(1.1)
(3.8)
(2.7)
36X (0.4)
8
21
(R0.05) TYP
9
20
SYMM
(5.8)
(
0.2) TYP
VIA
LAND PATTERN EXAMPLE
SCALE:15X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222125/B 01/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
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EXAMPLE STENCIL DESIGN
RNQ0040A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
4X (1.5)
40
29
40X (0.6)
1
28
40X (0.2)
SYMM
6X
(0.695)
(3.8)
6X
(1.19)
36X (0.4)
8
21
(R0.05) TYP
METAL
TYP
9
20
6X (1.3)
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD
73% PRINTED SOLDER COVERAGE BY AREA
SCALE:18X
4222125/B 01/2016
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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