TCM29C19 [TI]
ANALOG INTERFACE FOR DSP; 模拟信号接口用于DSP
| 型号： | TCM29C19 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ANALOG INTERFACE FOR DSP |
| 文件： | 总17页 (文件大小：266K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996
DW OR N PACKAGE
(TOP VIEW)
Reliable Silicon-Gate CMOS Technology
Low Power Consumption
– Operating Mode . . . 80 mW
– Power-Down Mode . . . 5 mW
V
V
CC
GSX
1
2
3
4
5
6
7
8
16
15
14
13
BB
PWRO+
PWRO–
PDN
µ-Law Coding
ANLG IN
ANLG GND
Excellent Power-Supply Rejection Ratio
Over Frequency Range of 0 Hz to 50 kHz
DCLKR
12 TSX/DCLKX
11
10
9
PCM IN
PCM OUT
FSX/TSXE
CLK
No External Components Needed for
Sample, Hold, and Autozero Functions
FSR/TSRE
DGTL GND
Precision Internal Voltage Reference
Single Chip Contains A/D, D/A, and
Associated Filters
FEATURES TABLE
Number of Pins:
description
16
Coding Law:
The TCM29C18, TCM29C19, TCM129C18, and
TCM129C19 are low-cost single-chip PCM
codecs (pulse-code-modulated encoders and
decoders) and PCM line filters. These devices
incorporate both the A/D and D/A functions, an
antialiasing filter (A/D), and a smoothing filter
(D/A). They are ideal for use with the TMS320
DSP family members, particularly those featuring
a serial port such as the TMS32020, TMS32011,
and TMS320C25.
µ-Law
Variable Mode:
64 kHz to 2.048 MHz
Fixed Mode:
2.048 MHz (TCM29C18, TCM129C18),
1.536 MHz (TCM29C19, TCM129C19)
8-Bit Resolution
12-Bit Dynamic Range
Primary applications include:
•
•
•
Digital encryption systems
Digital voice-band data storage systems
Digital signal processing
These devices are designed to perform encoding of analog input signals (A/D conversion) and decoding of
digital PCM signals (D/A conversion). They are useful for implementation in the analog interface of a digital
signal processing system. Both devices also provide band-pass filtering of the analog signals prior to encoding,
and smoothing after decoding.
The TCM29C18 and TCM29C19 are characterized for operation over the temperature range of 0°C to 70°C.
The TCM129C18 and TCM129C19 are characterized for operation over the temperature range of
–40°C to 85°C.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996
functional block diagram
Transmit Section
Autozero
11
11
12
14
15
PCM OUT
Filter
Sample
and Hold
and DAC
ANLG IN
Output
Register
Successive
Approximation
Comparator
TSX/
DCLKX
GSX
Analog-
to-Digital
Control
Logic
10
9
FSX/TSXE
CLK
Reference
Control Section
Receive Section
Control
Logic
4
Filter
PDN
Gain
Σ
Set
Buffer
6
5
Digital-
to-Analog
Control
Logic
PCM IN
DCLKR
Sample
and Hold
and DAC
Input
Register
2
3
PWRO+
PWRO–
+
–
Reference
16
1
8
13
7
FSR/TSRE
DGTL ANLG
GND GND
V
CC
V
BB
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
ANLG IN
ANLG GND
CLK
NO.
14
13
9
I
Inverting analog input to uncommitted transmit operational amplifier.
Analog ground return for all voice circuits. ANLG GND is internally connected to DGTL GND.
I
I
Master clock and data clock input for the fixed-data-rate mode. Master (filter) clock only for variable-data-rate
mode. CLK is used for both the transmit and receive sections.
DCLKR
5
Fixed-data-rate mode — variable-data-rate mode select. When DCLKR is connected to V , the device operates
BB
in the fixed-data-rate mode. When DCLKR is not connected to V , the device operates in the variable-data-rate
BB
mode and DCLKR becomes the receive data clock, which operates at frequencies from 64 kHz to 2.048 MHz.
Digital ground for all internal logic circuits. DGTL GND is internally connected to ANLG GND.
DGTL GND
FSR/TSRE
8
7
I
I
Frame-synchronization clock input/time-slot enable for the receive channel. In the variable-data-rate mode, this
signal must remain high for the duration of the time slot. The receive channel enters the standby state when FSR
is TTL low for 30 ms.
FSX/TSXE
10
Frame-synchronization clock input/time-slot enable for transmit channel. FSX/TSXE operates independently of,
but in an analogous manner to FSR/TSRE. The transmit channel enters the standby state when FSX is low for 300
ms.
GSX
15
6
O
I
Outputterminal of internal uncommitted operational amplifier. Internally, this is the voice signal input to the transmit
filter.
PCM IN
PCM OUT
PDN
Receive PCM input. PCM data is clocked in on eight consecutive negative transitions of the receive data clock,
which is CLKR in fixed-data-rate timing and DCLKR in variable-data-rate timing.
11
4
O
I
Transmit PCM output. PCM data is clocked out of pcm out on eight consecutive positive transition of the transmit
data clock, which is CLKX in fixed-data-rate timing and DCLKX in variable-data-rate timing.
Power-down select. On the TCM29C18 and the TCM129C18, the device is inactive with a TTL low-level input and
active with a TTL high-level input to the terminal. On the TCM29C19 and the TCM129C19, this terminal must be
connected to a TTL high level.
PWRO+
2
3
O
O
Noninverting output of power amplifier. PWRO+ can drive transformer hybrids or high-impedance loads directly
in either a differential or single-ended configuration.
PWRO–
Inverting output of power amplifier. PWRO– is functionally identical to PWRO+.
TSX/DCLKX
12 I/O Transmit channel time-slot strobe (output) or data clock (input). In the fixed-data-rate mode, this is an open-drain
output to be used as an enable signal for a 3-state buffer. In the variable-data-rate mode, DCLKX becomes the
transmit data clock, which operates at TTL levels from 64 kHz to 2.048 MHz.
V
V
1
Negative supply voltage. Input is –5 V ±5%.
Positive supply voltage. Input is 5 V ±5%.
BB
16
CC
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Output voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
CC
O
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
I
Digital ground voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 15 V
Operating free-air temperature range, T : TCM29C18, TCM29C19 . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
TCM129C18, TCM129C19 . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Voltage values for maximum ratings are with respect to V
.
BB
recommended operating conditions (see Note 2)
MIN NOM
MAX
UNIT
V
V
V
Supply voltage (see Note 3)
4.75
5
5.25
CC
Supply voltage
–4.75
–5 –5.25
0
V
BB
DGTL GND voltage with respect to ANLG GND
High-level input voltage, all inputs except ANLG IN
Low-level input voltage, all inputs except ANLG IN
Peak-to-peak analog input voltage (see Note 4)
V
V
V
V
2.2
V
IH
0.8
4.2
V
IL
V
I(PP)
GSX
10
kΩ
Ω
R
C
Load resistance
L
L
PWRO+ and/or PWRO–
300
GSX
50
100
70
Load capacitance
pF
PWRO+ and/or PWRO–
TCM29C18 or TCM29C19
TCM129C18 or TCM129C19
0
T
A
Operating free-air temperature
°C
–40
85
NOTES: 2. ToavoidpossibledamagetotheseCMOSdevicesandresultingreliabilityproblems, thepower-upproceduredescribedinthedevice
power-up sequence paragraphs later in this document should be followed.
3. Voltagesat analog inputs and outputs and V
to DGTL GND unless otherwise noted.
and V
terminals are with respect to ANLG GND. All other voltages are referenced
BB
CC
4. Analog inputs signals that exceed 4.2 V peak to peak may contribute to clipping and preclude correct A/D conversion. The digital
code representing values higher than 4.2 V is 10000000. For values more negative than 4.2 V, the code is 0000000.
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
supply current, f
= 2.048 MHz, outputs not loaded
DCLK
TCM29Cxx
MIN MAX
TCM129Cxx
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
14
Operating
Standby
10
1.2
1
FSX or FSR at V after 300 ms
IL
1.5
I
I
Supply current from V
Supply current from V
mA
CC
CC
BB
Power down
Operating
Standby
1.2
PDN at V after 10 µs
IL
–10
–1.2
–1
–14
–1.5
–1.2
FSX or FSR at V after 300 ms
IL
mA
BB
Power down
PDN at V after 10 µs
IL
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996
ground terminals
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MAX
UNIT
DC resistance between ANLG GND and DGTL GND
34
Ω
digital interface
†
PARAMETER
TEST CONDITIONS
MIN TYP
UNIT
I
I
I
= –9.6 mA
= –0.1 mA
= 3.2 mA
2.4
3.5
OH
OH
OL
V
V
High-level output voltage at PCM OUT
V
OH
0.5
12
12
10
V
Low-level output voltage at TSX
High-level input current, any digital input
Low-level input current, any digital input
Input capacitance
OL
I
I
V = 2.2 V to V
CC
µA
µA
pF
pF
IH
I
V = 0 to 0.8 V
IL
I
C
C
5
5
i
Output capacitance
o
†
All typical values are at V
= –5 V, V
= 5 V, and T = 25°C.
CC A
BB
transmit side (A/D) characteristics
†
PARAMETER
TEST CONDITIONS
V = –2.17 V to 2.17 V
MIN TYP
MAX
UNIT
mV
pA
Input offset voltage at ANLG IN
Input offset current at ANLG IN
Input bias current
±25
I
V = –2.17 V to 2.17 V
I
1
V = –2.17 V to 2.17 V
I
±100
nA
Open-loop voltage amplification at GSX
Unity-gain bandwidth at GSX
Input resistance at ANLG IN
5000
10
1
MHz
MΩ
–3 ≥ dBm0 input level ≥ –40 dBm0,
Ref level = –10 dBm0
±0.5
±25
1.19
–70
Gain-tracking error with sinusoidal input
(see Notes 5, 6, and 7)
dB
–40 > dBm0 input level ≥ –50 dBm0, Ref level = –10 dBm0
Transmit gain tolerance
Noise
V = 1.06 V,
I
f = 1.02 kHz
0.95
Vrms
dB
Ref max output level: 200 Hz to 3 kHz
Supply-voltage rejection ratio,
f = 0 Hz to 30-kHz (measured at PCM OUT) idle channel,
Supply signal = 200 mV peak to peak
–20
62
dB
dB
V
CC
to V
BB
Crosstalk attenuation, transmit to
receive (single ended)
ANLG IN = 0 dBm,
f = 1-kHz, unity gain,
Measured at PWRO+
PCM IN = lowest decode level,
0 dBm0 ≥ ANLG IN ≥ –30 dBm0
–30 dBm0 > ANLG IN ≥ –40 dBm0
–40 dBm0 > ANLG IN ≥ –45 dBm0
33
27
22
Signal-to-distortion ratio, sinusoidal
input (see Note 8)
dB
Fixed-data rate,
Input to ANLG IN = 1 kHz at 0 dB
f
= 2.048 MHz,
CLKX
Absolute delay time to PCM OUT
245
µs
†
All typical values are at V
= –5 V, V
= 5 V, and T = 25°C.
CC A
BB
NOTES: 5. Unless otherwise noted, the analog input is a 0-dBm0, 1020-Hz sine wave, where 0 dBm0 is defined as the zero-reference point
of the channel under test. This corresponds to an analog signal input of 1.064 Vrms or an output of 1.503 Vrms.
6. The input amplifier is set for unity gain. The digital input is a PCM bit stream generated by passing a 0-dBm0, 1020-Hz sine wave
through an ideal encoder.
7. The TCM29C18, TCM29C19, TCM129C18, and TCM129C19 are internally connected to set PWRO+ and PWRO– to 0 dBM. All
output levels are (sin x)/x corrected.
8. CCITT G.712 – Method 2
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996
receive side (D/A) characteristics (see Note 9)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
Output offset voltage PWRO+ and
PWRO– (single ended)
Relative to ANLG GND
±200
mV
Output resistance at PWRO+ and
PWRO–
1
2
Ω
–3 dBm0 ≥ input level ≥ –40 dBm0,
Ref level = –10 dBm0
±0.5
±25
1.69
–70
Gain-tracking error with sinusoidal
input (see Notes 5, 6, and 7)
dB
–40 dBm0 > input level ≥ –50 dBm0, Ref level = –10 dBm0
Receive gain tolerance
Noise
V = 1.06 V,
I
f = 1.02 kHz
1.34
Vrms
dB
Ref max output level: 200 Hz to 3 kHz
f = 0 Hz to 30-kHz,
Supply signal = 200 mV peak to peak, Narrow band,
Frequency at PWRO+
Idle channel,
Supply voltage rejection ratio,
–20
60
dB
dB
V
CC
to V
(single-ended)
BB
Crosstalk attenuation, receive to
transmit (single ended)
PCM IN = 0 dB,
Frequency = 1 kHz at PCM OUT
0 dBm0 ≥ ANLG IN ≥ –30 dBm0
–30 dBm0 > ANLG IN ≥ –40 dBm0
–40 dBm0 > ANLG IN ≥ –45 dBm0
33
27
22
Signal-to-distortion ratio, sinusoidal
input (see Note 8)
dB
Absolute delay time to PWRO+
Fixed data rate,
f
= 2.048 MHz
190
µs
CLKX
†
All typical values are at V
= –5 V, V
CC
= 5 V, and T = 25°C.
BB
A
NOTES: 5. Unless otherwise noted, the analog input is a 0-dBm0, 1020-Hz sine wave, where 0 dBm0 is defined as the zero-reference point
of the channel under test. This corresponds to an analog signal input of 1.064 Vrms or an output of 1.503 Vrms.
6. The input amplifier is set for unity gain. The digital input is a PCM bit stream generated by passing a 0-dBm0, 1020-Hz sine wave
through an ideal encoder.
7. The TCM29C18, TCM29C19, TCM129C18, and TCM129C19 are internally connected to set PWRO+ and PWRO– to 0 dBM. All
output levels are (sin x)/x corrected.
8. CCITT G.712 – Method 2
9. The receive side (D/A) characteristics are referenced to a 600-Ω termination.
timing requirements
clock timing requirements over recommended ranges of supply voltage and operating free-air temperature
(see Figures 3 and 4)
MIN NOM
MAX
UNIT
ns
t
Clock period for CLK (2.048-MHz systems)
Rise and fall times for CLK
488
5
c(CLK)
t , t
30
ns
r f
t
Pulse duration for CLK
220
220
ns
w(CLK)
t
Pulse duration, DCLK (f
DCLK
= 64 kHz to 2.048 MHz)
] for CLK
ns
w(DCLK)
Clock duty cycle, [t
/t
w(CLK) c(CLK)
45%
50%
55%
transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 3)
MIN
MAX
–100
c(CLK)
UNIT
t
Frame-sync delay time
100
t
ns
d(FSX)
receive timing requirements over recommended ranges of supply voltages and operating free-air
temperature, fixed-data-rate mode (see Figure 4)
MIN
MAX
–100
c(CLK)
UNIT
t
Frame-sync delay time
100
t
ns
d(FSR)
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996
transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-rate mode (see Figure 5)
MIN
140
100
488
MAX
–140
UNIT
ns
t
t
t
Delay time, time-slot from DCLKX (see Note 10)
Delay time, frame sync
t
d(DCLKX)
d(TSDX)
t
–100
c(CLK)
ns
d(FSX)
Pulse duration, DCLKX
15620
ns
c(DCLKX)
NOTE 10: t
FSLX
minimum requirement overrides the t maximum requirement for 64-kHz operation.
d(TSDX)
receive timing requirements over recommended ranges of supply voltages and operating free-air
temperature, variable-data-rate mode (see Figure 6)
MIN
140
100
10
MAX
UNIT
ns
t
t
t
t
t
t
Delay time, time slot from DCLKR (see Note 11)
Delay time, frame sync T
t
–140
d(TSDR)
w(DCLKR)
–100
t
ns
d(FSR)
C(CLK)
c(CLK)
Setup time before bit 7 falling edge
Hold time after bit 8 falling edge
Pulse duration, DCLKR
ns
su(PCM IN)
h(PCM IN)
w(DCLKR)
SER
60
ns
488
0
15620
ns
Time-slot end receive time
ns
NOTE 11: t
FSLR
minimum requirement overrides the t maximum requirement for 64-kHz operation.
c(TSDR)
64 k-bit operation over recommended ranges of supply voltage and operating free-air temperature,
variable-data-rate mode
MIN
488
MAX
UNIT
ns
t
t
t
Transmit frame sync, minimum down time
Receive frame sync, minimum down time
Pulse duration, data clock
FSX = TTL high for remainder of frame
FSR = TTL high for remainder of frame
FSLX
1952
ns
FSLR
10
µs
w(DCLK)
switching characteristics
propagation delay times over recommended ranges of operating conditions, fixed-data-rate mode
(see timing diagrams)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Delay time from rising edge of transmit clock to bit 1 data valid at PCM OUT
(data enable time on time-slot entry)
t
t
t
t
t
C
C
C
C
C
= 0 to 100 pF
= 0 to 100 pF
= 0
0
145
ns
pd1
pd2
pd3
pd4
pd5
L
L
L
L
L
Delay time from rising edge of transmit clock bit n to bit n data valid at PCM OUT
(data valid time)
0
60
0
145
215
145
190
ns
ns
ns
ns
Delay time from falling edge of transmit clock bit 8 to bit 8 Hi-Z at PCM OUT
(data float time on time-slot exit)
Delay time from rising edge of transmit clock bit 1 to TSX active (low)
(time-slot enable time)
= 0 to 100 pF
= 0
Delay time from falling edge of transmit clock bit 8 to TSX inactive (high)
(time-slot disable time)
60
propagation delay times over recommended ranges of operating conditions, variable-data-rate mode
PARAMETER
TEST CONDITIONS
MIN
0
MAX
100
50
UNIT
ns
t
t
t
t
Delay time from DCLKX
pd6
pd7
pd8
pd9
Delay time from time-slot enable to PCM OUT
Delay time from time-slot disable to PCM OUT
Delay time from FSX
C
= 0 to 100 pF
0
ns
L
0
80
ns
t
= 140 ns
0
140
ns
d(TSDX)
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996
PARAMETER MEASUREMENT INFORMATION
0.2 dB
3300 Hz
0.5 dB
300 Hz
0.5 dB
3000 Hz
0 dB
3400 Hz
0.2 dB
200 Hz
0
0
–0.5 dB
3000 Hz
–2 dB
–0.5 dB
300 Hz
3300 Hz
–3.5 dB
3400 Hz
Typical Filter
Transfer Function
–1
–1
–2.5 dB
200 Hz
0
–10
–20
–30
–40
0
–10
–20
–30
–40
–10 dB
4000 Hz
–13 dB
60 Hz
Typical Filter
Transfer Function
–25 dB
4600 Hz
–15 dB
60 Hz
–18 dB
16.67 Hz
–50
–60
–50
–60
10
50
100
1 k
10 k
f – Frequency – Hz
NOTE A: This is a typical transfer function of the receiver filter component.
Figure 1. Transmit Filter Transfer Characteristics
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996
PARAMETER MEASUREMENT INFORMATION
+2
2
+1
0
1
0.5 dB
3000 HZ
0.5 dB
200 Hz
0.5 dB
300 Hz
0.2 dB
3300 HZ
0
0 dB
3400 Hz
–0.5 dB
3000 Hz
–0.5 dB
300 Hz
–0.8 dB
200 Hz
–2 dB
3300 Hz
–3.5 dB
3400 Hz
–1
–1
0
–10
–20
–30
–40
–50
0
–10
–20
–30
–40
–50
–10 dB
4000 Hz
–25 dB
4800 Hz
100
1 k
10 k
f – Frequency – Hz
NOTE A: This is a typical transfer function of the receive filter component.
Figure 2. Receive Filter Transfer Characteristics
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996
PARAMETER MEASUREMENT INFORMATION
Time Slot 1
CLK
t
1
2
3
4
5
6
7
8
t
r
t
f
d(FSX)
t
d(FSX)
t
w(CLK)
t
FSX Input
c(CLK)
FRAME SYNCHRONIZATION TIMING
Time Slot N
1
2
3
4
5
6
7
8
CLK
t
t
t
pd3
pd1
pd2
PCM OUT
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
t
t
pd5
pd4
TSX Output
OUTPUT TIMING
NOTES: A. Inputs are driven from 0.45 V to 2.4 V. Time intervals are referenced to 2 V if the high level is indicated and 0.8 V if the low level is
indicated.
B. Bit 1 is the most significant bit (MSB) and is clocked in first on the PCM IN input or is clocked out first on the PCM OUT output.
Bit 8 is the least significant bit (LSB) and is clocked in last on the PCM IN input or is clocked out last on the PCM OUT output.
Figure 3. Transmit Timing (Fixed-Data Rate)
Time Slot 1
CLKR
1
2
3
4
5
6
7
8
t
t
r
t
f
t
d(FSR)
t
d(FSR)
w(CLK)
t
FSR Input
c(CLK)
FRAME SYNCHRONIZATION TIMING
Time Slot N
CLK
1
2
3
4
5
6
7
8
t
su(PCM IN)
t
h(PCM IN)
PCM IN
Bit 1
Valid
Bit 2
Valid
Bit 3
Valid
Bit 4
Valid
Bit 5
Valid
Bit 6
Valid
Bit 7
Valid
Bit 8
Valid
INPUT TIMING
NOTES: A. Inputs are driven from 0.45 V to 2.4 V. Time intervals are referenced to 2 V if the high level is indicated and 0.8 V if the low level is
indicated.
B. Bit 1 is the most significant bit (MSB) and is clocked in first on the PCM IN input or is clocked out first on the PCM OUT output.
Bit 8 is the least significant bit (LSB) and is clocked in last on the PCM IN input or is clocked out last on the PCM OUT output.
Figure 4. Receive Timing (Fixed-Data Rate)
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996
PARAMETER MEASUREMENT INFORMATION
Time Slot
FSX
t
d(TSDX)
1
2
3
4
5
6
7
8
DCLKX
CLKX
t
d(FSX)
t
pd7
t
t
t
pd9
pd8
pd6
PCM OUT
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
NOTES: A. Inputs are driven from 0.45 V to 2.4 V. Time intervals are referenced to 2 V if the high level is indicated and 0.8 V if the low level is
indicated.
B. Bit 1 is the most significant bit (MSB) and is clocked in first on the PCM IN input or is clocked out first on the PCM OUT output.
Bit 8 is the least significant bit (LSB) and is clocked in last on the PCM IN input or is clocked out last on the PCM OUT output.
C. All timing parameters referenced to V and V except t
IH IL
and t , which references the high-impedance state.
pd8
pd7
Figure 5. Transmit Timing (Variable-Data Rate)
FSR
t
d(TSDR)
1
2
3
4
5
6
7
8
DCLKR
CLKR
t
t
SER
d(FSR)
t
t
su(PCM IN)
h(PCM IN)
PCM IN
Don’t Care
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
NOTES: A. Inputs are driven from 0.45 V to 2.4 V. Time intervals are referenced to 2 V if the high level is indicated and 0.8 V if the low level is
indicated.
B. Bit 1 is the most significant bit (MSB) and is clocked in first on the PCM IN input or is clocked out first on the PCM OUT output.
Bit 8 is the least significant bit (LSB) and is clocked in last on the PCM IN input or is clocked out last on the PCM OUT output.
C. All timing parameters referenced to V and V except t
IH IL
and t , which references the high-impedance state.
pd8
pd7
Figure 6. Receive Timing (Variable-Data Rate)
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996
PRINCIPLES OF OPERATION
system reliability and design considerations
TCM29C18, TCM29C19, TCM129C18, and TCM129C19 system reliability and design considerations are
described in the following paragraphs.
latch-up
Latch-up is possible in all CMOS devices. It is caused by the firing of a parasitic SCR that is present due to the
inherent nature of CMOS. When a latch-up occurs, the device draws excessive amounts of current and will
continue to draw heavy current until power is removed. Latch-up can result in permanent damage to the device
if supply current to the device is not limited.
Even though these devices are heavily protected against latch-up, it is still possible to cause latch-up under
certainconditionsinwhichexcesscurrentisforcedintooroutofoneormoreterminals. Latch-upcanoccurwhen
the positive supply voltage drops momentarily below ground, when the negative supply voltage rises
momentarilyaboveground, orpossiblyifasignalisappliedtoaterminalafterpowerhasbeenappliedbutbefore
the ground is connected. This can happen if the device is hot-inserted into a card with the power applied, or
if the device is mounted on a card that has an edge connector and the card is hot-inserted into a system with
the power on.
To help ensure that latch-up does not occur, it is considered good design practice to connect a reverse-biased
Schottky diode (with a forward voltage drop of less than or equal to 0.4 V – 1N5711 or equivalent) between the
power supply and GND (see Figure 7). If it is possible that a TCM29C18-, TCM29C19-, TCM129C18-, or
TCM129C19-equipped card that has an edge connector could be hot-inserted into a powered-up system, it is
also important to ensure that the ground edge connector traces are longer than the power and signal traces so
that the card ground is always the first to make contact.
device power-up sequence
Latch-up can also occur if a signal source is connected without the device being properly grounded. A signal
applied to one terminal could then find a ground through another signal terminal on the device. To ensure proper
operation of the device and as a safeguard against this sort of latch-up, it is recommended that the following
power-up sequence always be used:
1. Ensure that no signals are applied to the device before the power-up sequence is complete.
2. Connect GND.
3. Apply V (most negative voltage).
BB
4. Apply V
(most positive voltage).
CC
5. Force a power down condition in the device.
6. Connect clocks.
7. Release the power down condition.
8. Apply FS synchronization pulses.
9. Apply the signal inputs.
When powering down the device, this procedure should be followed in the reverse order.
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996
PRINCIPLES OF OPERATION
V
CC
DGND
V
BB
Figure 7. Latch-Up Protection Diode Connection
internal sequencing
On the transmit channel, digital outputs PCM OUT and TSX are held in the high-impedance state for
approximately four frames (500µs) after power up or application of V . Afterthisdelay, PCMOUT, TSX,
V
BBor CC
and signaling are functional and occur in the proper time slot. The analog circuits on the transmit side require
approximately 60 ms to reach their equilibrium value due to the autozero circuit settling time. Thus valid digital
information, such as on/off hook detection, is available almost immediately while analog information is available
after some delay.
To further enhance system reliability, PCM OUT and TSX are placed in the high-impedance state approximately
20 µs after an interruption of CLKX. These interruptions could possibly occur with some kind of fault condition.
power-down and standby operations
To minimize power consumption, a power-down mode and three standby modes are provided.
For power down, an external low signal is applied to PDN. In the absence of a signal, PDN is internally pulled
up to a high logic level and the device remains active. In the power-down mode, the average power consumption
is reduced to 5 mW.
Three standby modes give the user the options of placing the entire device on standby, placing only the transmit
channel on standby, or placing only the receive channel on standby. To place the entire device on standby, both
FSX and FSR are held low. For transmit-only operation (receive channel on standby), FSX is high and FSR is
held low. For receive-only operation (transmit section on standby), FSR is high and FSX is held low. When the
entire device is in standby mode, power consumption is reduced to 12 mW. See Table 1 for power-down and
standby procedures.
Table 1. Power-Down and Standby Procedures
TYPICAL POWER
CONSUMPTION
DEVICE STATUS
Power down
PROCEDURE
PDN = TTL low
DIGITAL OUTPUT STATUS
5 mW
TSX and PCM OUT are in the high-impedance state
TSX and PCM OUT are in the high-impedance state
Entire device on standby
Only transmit on standby
FSX and FSR are TTL low
12 mW
FSX is TTL low,
FSR is TTL high
TSX and PCM OUT are placed in the high-impedance
state within 300 ns
70 mW
FSR is TTL low,
FSX is TTL high
Only receive on standby
110 mW
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996
PRINCIPLES OF OPERATION
fixed-data-rate timing (see Figures 3 and 4)
Fixed-data-rate timing is selected by connecting DCLKR to V
and uses master clock CLK, frame-
BB
synchronizer clocks FSX and FSR, and output TSX. FSX and FSR are 8-kHz inputs that set the sampling
frequency. Data is transmitted on PCM OUT on the first eight positive transitions of CLK following the rising edge
of FSX. Data is received on PCM IN on the first eight falling edges of CLK following FSX. A digital-to-analog
(D/A) conversion is performed on the received digital word and the resulting analog sample is held on an internal
sample-and-hold capacitor until transferred to the receive filter.
The TCM29C18 and TCM129C18 operate at 2.048 MHz only. The TCM29C19 and TCM129C19 operate at
1.536 MHz only.
variable-data-rate timing
Variable-data-rate timing is selected by connecting DCLKR to the bit clock for the receive PCM highway rather
than to V . It uses master clock CLK, bit clocks DCLKX and DCLKR, and frame-synchronization clocks FSX
BB
and FSR.
Variable-data-rate timing allows for a flexible data frequency. The frequency of the bit clocks can be varied from
64 kHz to 2.048 MHz. The bit clocks must be asynchronous; however, the master clock is restricted to
2.048 MHz.
When FSX/TSXE is high, PCM data is transmitted from PCM OUT onto the highway on the next eight
consecutive positive transitions of DCLKX. Similarly, while the FSR/TSRE input is high, the PCM word is
received from the highway by PCM IN on the next eight consecutive negative transitions of DCLKR.
ThetransmittedPCMwordisrepeatedinallremainingtimeslotsinthe125-µsframeaslongasDCLKXispulsed
and FSX is held high. This feature, which allows the PCM word to be transmitted to the PCM highway more than
once per frame if desired, is available only with variable-data-rate timing.
asynchronous operation
In either timing mode, the master clock, data clock, and time slot-strobe must be synchronized at the beginning
of each frame. Specifically, in the variable-rate mode, the falling edge of CLKX must occur within t
ns after
d(FSX)
the rise of FSX, and the falling edge of DCLKX must occur within t
ns after the rise of FSX. CLK and DCLKX
TSDX
are synchronized once per frame but may be of different frequencies. The receive channel operates in a similar
manner and is completely independent of the transmit timing (see Figure 6).
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996
PRINCIPLES OF OPERATION
transmit operation
transmit filter
The input section provides gain adjustment in the pass band by means of an on-chip uncommitted operational
amplifier. The load impedance to ground (ANLG GND) at the amplifier output (GSX) must be greater than
10 kΩ in parallel with less than 50 pF. The input signal on ANLG IN can be either ac or dc coupled.
A low-pass antialiasing filter section is included on the device. This section provides 35-dB attenuation at the
sampling frequency. No external components are required to provide the necessary antialiasing function for the
switched-capacitor section of the transmit filter.
The pass band section provides flatness and stopband attenuation that fulfills the AT&T D3/D4 channel bank
transmission specification and CCITT recommendation G.712. The device specifications meet or exceed digital
class 5 central office switching-systems requirements.
A high-pass section configuration was chosen to reject low-frequency noise from 50- and 60-Hz power lines,
17-Hz European electric railroads, ringing frequencies and their harmonics, and other low-frequency noise.
Even with the high rejection at these frequencies, the sharpness of the band edge gives low attenuation at
200 Hz. This feature allows the use of low-cost transformer hybrids without external components.
encoding
The encoder internally samples the output of the transmit filter and holds each sample on an internal sample-
and-hold capacitor. The encoder performs an analog-to-digital conversion on a switched-capacitor array. Digital
date representing the sample is transmitted on the first eight data clock bits of the next frame.
The autozero circuit corrects for dc offset on the input signal to the encoder. The autozero circuit uses the sign
bit averaging technique. The sign bit from the encoder output is long-term averaged and subtracted from the
input to the encoder. All dc offset is removed from the encoder input waveform.
The analog input is encoded into an 8-bit digital representation by using the µ-law encoding scheme
(CCITT G.711) that equates to 12 bits of resolution for low amplitude signals. Similarly, the decoding section
converts 8-bit PCM data into an analog signal with 12 bits of dynamic range. The filter characteristics (band
pass) for the encoder and decoder are determined by a single clock input (CLK). The filter roll off (–3 dB) is
derived by:
f
f
= k • f
= k • f
/256 for the TCM29C18 and TCM129C18
/192 for the TCM29C19 and TCM129C19
co
co
CLK
CLK
where k has a value of 0.44 for the high-frequency roll-off point and a value of 0.019 for the low-frequency roll-off
point.
The sampling rate of the ADC is determined by the transmit frame-sync clock (FSX); the sampling rate of the
DAC is determined by the receive frame-sync clock (FSR). Once a conversion is initiated by FSX or FSR, data
is clocked in or out on the next eight consecutive clock pulses in the fixed-rate-mode. Likewise, data may also
be transferred on the next eight consecutive clock pulses of the data clocks (DCLKX and DCLKR) in the
variable-data-rate mode. In the variable-data-rate mode, DCLKX and DCLKR are independent but must be in
the range from f
/32 to f
.
CLK
CLK
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021D –AUGUST 1987 –REVISED OCTOBER 1996
PRINCIPLES OF OPERATION
receive operation
decoding
The serial PCM word is received at PCM IN on the first eight data clock bits of the frame. Digital-to-analog
conversionisperformedandthecorrespondinganalogsampleisheldonaninternalsample-and-holdcapacitor.
This sample is transferred to the receive filter.
receive filter
The receive section of the filter provides pass band flatness and stop band rejection that fulfills both the AT&T
D3/D4 specification and CCITT recommendation G.712. The filter contains the required compensation for the
(sin x)/x response of such decoders.
receive output power amplifiers
A balanced-output amplifier is provided to allow maximum flexibility in output configuration. Either of the two
outputs can be used single ended (i.e., referenced to ANLG GND) to drive single-ended loads. Alternatively,
the differential output directly drives a bridged load. The output stage is capable of driving loads as low as 300 Ω
single ended to a level of 12 dBm or 600 Ω differentially to a level of 15 dBm.
Transmission levels are specified relative to the receive channel output under digital milliwatt conditions
(i.e., when the digital input at PCM IN is the eight-code sequence specified in CCITT recommendation G.711).
output gain
The devices are internally connected to set PWRO+ and PWRO– to 0 dBm.
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明