TCAN4550-Q1 [TI]
具有集成 CAN FD 控制器和收发器的汽车类系统基础芯片 (SBC);
| 型号： | TCAN4550-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成 CAN FD 控制器和收发器的汽车类系统基础芯片 (SBC) 控制器 |
| 文件： | 总154页 (文件大小：3939K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TCAN4550-Q1
ZHCSJK5D –JANUARY 2018 –REVISED JUNE 2022
TCAN4550-Q1 带有集成控制器和收发器的汽车控制器区域网灵活数据速率
(CAN FD) 系统基础芯片
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准
TCAN4550-Q1 是带有集成 CAN FD 收发器的 CAN
FD 控制器，支持高达 8Mbps 的数据速率。此 CAN
FD 控制器符合 ISO11898-1:2015 高速控制器局域网
(CAN) 数据链路层的规范，并满足 ISO11898–2:2016
高速CAN 规范的物理层要求。
– 温度等级1：–40°C 至125°C，TA
• 功能安全质量管理型
– 有助于进行功能安全系统设计的文档
• 带有集成CAN FD 收发器和串行外设接口(SPI) 的
CAN FD 控制器
• CAN FD 控制器支持ISO 11898-1:2015 和Bosch
M_CAN 修订版3.2.1.1
• 符合ISO 11898-2:2016 的要求
• 支持CAN FD 数据速率高达8Mbps，且SPI 时钟
速率高达18MHz
TCAN4550-Q1 通过串行外设接口 (SPI) 在 CAN 总线
和系统处理器之间提供了一个接口，同时支持经典
CAN 和 CAN FD，并为不支持 CAN FD 的处理器提供
端口扩展或 CAN 支持。TCAN4550-Q1 提供 CAN FD
收发器功能：传输到总线的差分传输能力和从总线接收
的差分接收能力。该器件支持通过本地唤醒 (LWU) 进
行唤醒以及使用实现 ISO11898-2:2016 唤醒模式
(WUP) 的CAN 总线进行总线唤醒。
• 向后兼容经典CAN
• 工作模式：正常、待机、睡眠和失效防护
• 为微处理器提供3.3V 至5V 输入/输出逻辑支持
• 在CAN 总线上具有宽工作范围
为了保证器件和 CAN 总线的稳健耐用性，此器件包括
很多保护特性。这些特性包括失效防护模式、内部显性
状态超时、宽总线工作范围和超时看门狗，等等。
– ±58V 总线故障保护
– ±12V 共模电压
• 集成的低压降稳压器为CAN 收发器提供5V 电压，
并为外部器件提供高达70mA 的电流
• 优化了未上电时的性能
器件信息
封装(1)
封装尺寸（标称值）
器件型号
TCAN4550-Q1
VQFN (20)
4.50mm x 3.50mm
– 总线和逻辑终端为高阻抗
（运行总线或应用上无负载）
– 上电和断电无干扰运行
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
• 车身电子装置和照明
• 信息娱乐系统与仪表组
• 工业运输
3
kΩ
3 kΩ
10 µF
10 µF
10 nF
10 nF
33 kΩ
33 kΩ
VBAT
VBAT
330 nF
10 µF
330 nF
10 µF
100 nF
100 nF
EN
EN
VIN
VIN
VSUP
VCCOUT
WAKE
VSUP
WAKE
FLTR
FLTR
VCCOUT
Voltage
Regulator
(e.g.
Voltage
Regulator
(e.g.
INH
INH
VINT
VLVRX
VINT
VLVRX
TPSxxxx)
TPSxxxx)
LDO(s)
LDO(s)
Filter
VOUT
VOUT
Filter
VIO
VIO
Under
Voltage
Under
Voltage
CNTL
POR
CNTL
POR
VIO
VIO
TCAN4550
TCAN4550
100 nF
100 nF
10 µF
10 µF
CANH
CANH
TXD_INT
RXD_INT
TXD_INT
RXD_INT
VINT
VINT
nWKRQ
VCC
nWKRQ
TX/RX Data
Buffer
GPIO3
TX/RX Data
Buffer
GPIO3
VCC
TX/RX CAN-FD
Controller with
Filters
TX/RX CAN-FD
Controller with
Filters
VIO
2-wire
CAN
bus
VIO
2-wire
CAN
bus
RST
SCLK
SDI
RST
SCLK
SDI
Reset
SCLK
CAN-FD
Transceiver
SPI
System
Controller
Reset
SCLK
CAN-FD
Transceiver
SPI
System
Controller
MOSI
MISO
MOSI
MISO
SDO
MCU
SDO
MCU
nCS
CANL
nCS
CANL
nCS
GPIO2
GPIO1
GPIO
nCS
GPIO2
GPIO1
GPIO
GPO2
nINT
GPIO1
GPO2
nINT
GPIO1
Optional:
Terminating
Node
Optional:
Terminating
Node
Optional:
Filtering,
Optional:
Filtering,
Transient and
ESD
GND
OSC1
OSC2
20 MHz
GND
Transient and
ESD
OSC1
OSC2
OSC1
OSC2
40 MHz
简化版原理图，CLKIN 来自MCU
简化版原理图，晶振
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSEZ5
TCAN4550-Q1
ZHCSJK5D –JANUARY 2018 –REVISED JUNE 2022
www.ti.com.cn
Table of Contents
8.3 Feature Description...................................................25
8.4 Device Functional Modes..........................................29
8.5 Programming............................................................ 42
8.6 Register Maps...........................................................47
9 Application and Implementation................................131
9.1 Application Design Consideration...........................131
9.2 Typical Application.................................................. 135
10 Power Supply Recommendations............................138
11 Layout.........................................................................139
11.1 Layout Guidelines................................................. 139
11.2 Layout Example.................................................... 140
12 Device and Documentation Support........................141
12.1 Documentation Support........................................ 141
12.2 接收文档更新通知................................................. 141
12.3 支持资源................................................................141
12.4 Trademarks...........................................................141
12.5 Electrostatic Discharge Caution............................141
12.6 术语表................................................................... 141
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specification.................................................................... 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings .............................................................. 5
6.3 ESD Ratings, IEC ESD and ISO Transient
Specification .................................................................5
6.4 Recommended Operating Conditions ........................6
6.5 Thermal Information ...................................................6
6.6 Supply Characteristics ............................................... 7
6.7 Electrical Characteristics ............................................8
6.8 Timing Requirements ............................................... 11
6.9 Switching Characteristics .........................................11
6.10 Typical Characteristics............................................13
7 Parameter Measurement Information..........................14
8 Detailed Description......................................................22
8.1 Overview...................................................................22
8.2 Functional Block Diagram.........................................23
Information.................................................................. 142
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision C (October 2020) to Revision D (June 2022)
Page
• 更改了数据表标题...............................................................................................................................................1
• 通篇将英文的“wake up”（唤醒）更改为“wake-up”（唤醒）..................................................................... 1
• Changed description of the OSCI (pin 1) and OSC2 (pin 2) in the Pin Functions table..................................... 4
• Added a second paragraph to the OSC1 and OSC2 Pins section................................................................... 27
• Changed register Timestamp Prescalar to: Timestamp Prescaler .................................................................. 56
• Changed bit 23 from: RSVD to: SMS in 图8-28 ..............................................................................................59
• Changed bit 9 description from: Transmission Completed to: Transmission Cancellation Finished................ 90
• Changed bit 32:24 to: 30:24 in 表8-56 ..........................................................................................................107
• Changed bullet: This is where the termination is split into two resistors, R5 and R6 To: This is where the
termination is split into two resistors, R4 and R5 in the Layout Guidelines ................................................... 139
• Added bullet for R8 in the Layout Guidelines ................................................................................................ 139
• Changed the Layout Example: added resistor R8 to Pin 1.............................................................................140
Changes from Revision B (November 2019) to Revision C (October 2020)
Page
• Changed UVSUP rising max from 5.9 to 5.7 and added min value of 5.2...........................................................7
• Added UVSUP falling max value of 5.0................................................................................................................7
• Changed bit 2:0 To: 3:0 in 表8-29 ...................................................................................................................73
Changes from Revision A (April 2019) to Revision B (November 2019)
Page
• 添加了“功能安全质量管理型”首页项目符号....................................................................................................1
• Changed VIO value IIL for SDI, SCK and nCS inputs in test conditions cell value from 0 V to 5.25 V................ 8
• Changed Power Up Timing diagram VSUP ramp voltage level for INH turn on and timing..............................14
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• Added INH Brownout Behavior section in Application section........................................................................134
Changes from Revision * (October 2017) to Revision A (April 2019) Page
• 将文档状态从预告信息更改为量产数据.............................................................................................................1
• Changed footnote Gauranteed to Specied throughout the electric table............................................................7
• Added VIO values for tSOV................................................................................................................................. 11
• Changed Power Up Timing diagram VSUP ramp voltage level for INH turn on and timing. ............................14
• Deleted CLKOUT from the GPIO1 circuit in 图8-2 ..........................................................................................23
• Deleted CLKOUT: Off from Sleep Mode section in 图8-14 ............................................................................. 35
• Deleted CLKOUT: Off From Sleep Mode section in 图8-15 ............................................................................35
• Deleted bits 15 and 14 from GPO1_CONFIG from in 表8-16 .........................................................................53
• Changed CLKOUT_GPIO1_CONFIG To: GPIO1_CONFIG for GPO1_CONFIG in 表8-16 ...........................53
• Changed the name of offset 1048 From: TDCE To: TDCR ..............................................................................64
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5 Pin Configuration and Functions
nWKRQ
GPIO1
SCLK
SDI
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
RST
FLTR
V
IO
Thermal
Pad
V
CCOUT
SDO
INH
nCS
V
SUP
nINT
GND
GPO2
WAKE
Not to scale
图5-1. RGY Package
20 Pin (VQFN)
(Top View)
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NO.
1
NAME
OSC1
nWKRQ
GPIO1
SCLK
SDI
I/O
DO
DI/O
DI
External crystal oscillator output or single-ended clock input
2
Wake request (active low)
3
Configurable input/output function pin through SPI
SPI clock input
4
5
DI
SPI target data input from controller output
SPI target data output to controller input
SPI chip select
6
SDO
DO
DI
7
nCS
8
nINT
DO
DO
Interrupt pin to MCU (active low)
Configurable output function pin through SPI
9
GPO2
CANL
CANH
WAKE
GND
10
11
12
13
14
15
16
17
18
19
20
HV Bus I/O Low level CAN bus line
HV Bus I/O High level CAN bus line
HVI
Wake input, high voltage input
Ground connection
GND
VSUP
HV Supply In Supply from battery
INH
HVO
Inhibit to control system voltage regulators and supplies (open drain)
VCCOUT
VIO
Supply Out 5 V regulated output
Supply In
Digital I/O voltage supply
FLTR
RST
Internal regulator filter, requires external capacitor to ground
Device reset
—
DI
I
OSC2
External crystal oscillator input; when using single-ended input clock to OSC1 this pin should be connected to ground.
(1) Note: DI = Digital Input; DO = Digital Output; HV = High Voltage; Thermal PAD and GND Pins must be soldered to GND
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6 Specification
6.1 Absolute Maximum Ratings
over operating free-air temperature range for –40 ℃≤TA ≤125 ℃(unless otherwise noted)(1)
MIN
MAX
42
6
UNIT
V
VSUP
VIO
Supply voltage
–0.3
–0.3
–0.3
–58
Supply voltage I/O level shifter
5 V output supply
V
VCCOUT
VBUS
VWAKE
VINH
6
V
CAN bus I/O voltage (CANH, CANL)
WAKE pin input voltage
58
42
42
6
V
V
–0.3
–0.3
–0.3
–0.5
Inhibit pin output voltage
Logic input terminal voltage
Digital output terminal voltage
Digital output current
V
VLogic_Input
VSO
V
6
V
IO(SO)
IO(INH)
IO(WAKE)
TJ
8
mA
mA
mA
°C
°C
Inhibit output current
4
3
Wake current if due to ground shift V(WAKE) ≤V(GND) –0.3 V
Junction temperature
150
150
–40
–65
Tstg
Storage temperature
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE UNIT
Human body model (HBM) classification level 3A per AEC Q100-002 All
V(ESD) Electrostatic discharge
V(ESD) Electrostatic discharge
V(ESD) Electrostatic discharge
terminal except for CANH and CANL. (1) WAKE terminals which are with
respect to ground only (2)
±4000
V
V
V
Human body model (HBM) classification level H2 for CANH and CANL (2) ±15000
Charged device model (CDM)
classification level C5, per AEC
Q100-011
All terminals
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) Terminals stressed with respect to GND
6.3 ESD Ratings, IEC ESD and ISO Transient Specification
VALUE
±8000
±15 000
±8000
±15 000
-100
UNIT
V
Contact discharge
Air discharge
Contact discharge
Air discharge
Pulse 1
Electrostatic discharge according to IBEE CAN
EMC (1)
V(ESD)
V
Electrostatic discharge according to
SAEJ2962-2 (2)
V(ESD)
V
Pulse 2
75
ISO7637 Transients according to IBEE CAN EMC test spec
CAN bus terminals (CANH and CANL), VSUP and WAKE (3)
Pulse 3a
-150
Pulse 3b
100
(1) IEC 61000-4-2 is a system-level ESD test. Results given here are specific to the IBEE LIN EMC Test specification conditions per IEC
TS 62228. Different system-level configurations may lead to different results
(2) SAEJ2962-2 Testing performed at 3rd party US3 approved EMC test facility, test report available upon request.
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(3) ISO7637 is a system-level transient test. Results given here are specific to the IBEE CAN EMC Test specification conditions. Different
system-level configurations may lead to different results.
6.4 Recommended Operating Conditions
over operating free-air temperature range for –40 ℃≤TA ≤125 ℃(unless otherwise noted)
MIN
TYP
MAX
30
UNIT
V
VSUP
Supply voltage
5.5
VIO
Logic pin supply voltage
3.135
–2
5.25
V
IOH(DO)
IOL(DO)
IO (INH)
C(FLTR)
C(VCCOUT)
CWAKE
TSDR
Digital terminal high-level output current
Digital terminal low-level output current
INH output current
mA
mA
mA
nF
µF
nF
℃
2
1
Filter pin capacitance See Power Supply Recommendations
VCCOUT supply capacitance See Power Supply Recommendations
External WAKE pin capacitance
Thermal shutdown rising
300
10
10
160
TSDF
Thermal shutdown falling
150
℃
TSD(HYS)
Thermal shutdown hysteresis
10
℃
6.5 Thermal Information
TCAN4550
THERMAL METRIC(1)
PKG DES (RGY)
UNIT
20 PINS
35.2
28.1
12.8
0.3
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ΨJT
12.7
1.1
ΨJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.6 Supply Characteristics
over operating free-air temperature range for –40 ℃≤TA ≤125 ℃(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
See 图7-3 RL = 60 Ω, CL =
open. typical bus load. VCCOUT
= no load
80 mA
Dominant
See 图7-3 RL = 50 Ω, CL =
90 mA
180 mA
15 mA
open, high bus load. VCCOUT
no load
=
Supply current, normal mode
See 图7-3 CANH = - 25 V, RL
= open, CL = open VCCOUT = no
load
Dominant with bus fault
Recessive
See 图7-3 RL = 60 Ω, CL =
ISUP
open, RCM = open, VCCOUT
no load
=
See 图7-3 RL = 60 Ω, CL =
open, -40°C < TA < 85°C,
VCCOUT = no load, CANH/L
terminated to 2.5 V
3.5 mA
3.4 mA
Supply current, standby mode
Supply current, sleep mode
See 图7-3 RL = 60 Ω, CL =
open, -40°C < TA < 85°C,
VCCOUT = no load CANH/L
terminated to GND ± 100 mV
SPI bus, OSC/CLKIN disabled:
-40°C < TA < 85°C, VIO = 0
ISUP
25
42 µA
CLKIN = 40 MHz, VIO = 5 V
Crystal = 40 MHz, VIO = 5 V
Sleep Mode VIO = 5 V; OSC1 =
800 µA
I/O supply current normal mode
dominant
IVIO
I/O supply current
3
mA
IVIO
I/O supply current, sleep mode I/O supply current
VCCOUT supply current
CLKIN = 0 V and OSC2 = GND
9
µA
(2)
Normal Mode: VCCOUT = 5 V;
-40°C < TA < 85°C See
Section VCCOUT Pin
IVCCOUT
70 mA
Under voltage detection on VSUP rising ramp for protected
mode
5.2
4.5
5.5
4.7
5.7
5.0
2.6
V
V
V
V
See Section Under-Voltage
Lockout (UVLO) and
Unpowered Device
UVSUP
Under voltage detection on VSUP falling ramp for protected
mode
Under voltage detection on VIO rising ramp for protected
mode
2.45
2.25
See Section Under-Voltage
Lockout (UVLO) and
Unpowered Device
UVIO
Under voltage detection on VIO falling ramp for protected
mode
2.1
Upon a UVIO event this timer
starts and provides time for VIO
input to return. See section
Thermal Shutdown for
description of thermal shut
down.
tUV/TSD
Under voltage filter time and thermal shutdown timer (1)
200
500 ms
(1) Specified by design
(2) When a crystal is used this current will be higher until the crystal's capacitors bleed off their energy. How much current and length of
time to bleed of the energy is system dependent and will not be specified.
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MAX UNIT
6.7 Electrical Characteristics
over operating free-air temperature range for –40 ℃≤TA ≤125 ℃(unless otherwise noted)
PARAMETER
TEST CONDITIONS (1)
MIN
TYP
CAN DRIVER ELECTRICAL CHARACTERISTICS
Bus output voltage (dominant) CANH
2.75
0.5
4.5
V
V
See 图7-3 and 图7-4, TXD_INT = 0 V,
EN = 0 V, 50 Ω ≤RL ≤65 Ω, CL =
open, RCM = open
VO(D)
Bus output voltage (dominant) CANL
2.25
See 图7-1 and 图7-4, TXD_INT = VIO
RL = open (no load), RCM = open
,
VO(R)
Bus output voltage (recessive)
2
–5.0
–0.1
2.5
3
10
V
V
V
V(DIFF)
Maximum differential voltage rating
See 图7-1 and 图7-4
Bus output voltage (Standby Mode)
CANH
0.1
Bus output voltage (Standby Mode)
CANL
See 图7-1 and 图7-4, TXD_INT = VIO
RL = open (no load), RCM = open
,
VO(STB)
0.1
0.2
V
V
–0.1
–0.2
Bus output voltage (Standby Mode)
CANH - CANL
See 图7-1 and 图7-4, TXD_INT = 0 V,
1.5
1.4
3
3
V
V
50 Ω≤RL ≤65 Ω, CL = open, RCM
open
=
See 图7-1 and 图7-4, TXD_INT = 0 V,
45 Ω≤RL ≤70 Ω, CL = open, RCM
VOD(D)
Differential output voltage (dominant)
=
open
See 图7-1 and 图7-4, TXD_INT = 0 V,
RL = 2.24 kΩ, CL = open, RCM = open
1.5
5
V
See 图7-1 and 图7-4, TXD_INT = VIO
RL = 60 Ω, CL = open, RCM = open
,
12
mV
–120
VOD(R)
Differential output voltage (recessive)
See 图7-1 and 图7-4, TXD_INT = VIO
,
50
mV
V/V
RL = open (no load), CL = open, RCM
open
=
–50
Output symmetry (dominant or
recessive)
See 图7-1 and 图7-4, RL = 60 Ω, CL =
open, RCM = open, C1 = 4.7 nF,
TXD_INT - 250 kHZ, 1 MHz
VSYM
0.9
1.1
( VO(CANH) + VO(CANL)) / VCC
Output symmetry (dominant or
recessive) (VCC –VO(CANH) –
VO(CANL)) with a frequency that
corresponds to the highest bit rate for
which the HS-PMA implementation is
intended, however, at most 1 MHz (2
Mbit/s)
See 图7-1 and 图7-4, RL = 60 Ω, CL =
open, RCM = open, C1 = 4.7 nF
VSYM_DC
300
mV
mA
–300
–100
See 图7-1 and 图7-8, -3.0 V ≤VCANH
≤18.0 V, CANL = open, TXD_INT = 0
V
Short-circuit steady-state output current,
dominant
IOS_DOM
IOS_REC
See 图7-1 and 图7-8, -3.0 V ≤VCANL
≤+18.0 V, CANH = open, TXD_INT = 0
V
100
5
mA
mA
Short-circuit steady-state output current, See 图7-1 and 图7-8, –27 V ≤VBUS
–5
recessive
≤32 V, VBUS = CANH = CANL
CAN RECEIVER ELECTRICAL CHARACTERISTICS
Receiver dominant state differential
VITdom
0.9
8
V
V
-12.0 V ≤VCANL ≤+12.0 V
-12.0 V ≤VCANH ≤+12.0 V See 图
7-5, 表8-3
input voltage range, bus biasing active
Receiver recessive state differential
VITrec
0.5
–3.0
input voltage range bus biasing active
Hysteresis voltage for input-threshold,
normal modes
VHYS
120
mV
See 图7-5, 表8-3
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6.7 Electrical Characteristics (continued)
over operating free-air temperature range for –40 ℃≤TA ≤125 ℃(unless otherwise noted)
PARAMETER
TEST CONDITIONS (1)
MIN
TYP
MAX UNIT
-12.0 V ≤VCANL ≤+12.0 V
-12.0 V ≤VCANH ≤+12.0 V See 图
7-5, 表8-3
Receiver dominant state differential
input voltage range, bus biasing inactive
(VDiff)
VIT(ENdom)
1.15
8
V
V
-12.0 V ≤VCANL ≤+12.0 V
-12.0 V ≤VCANH ≤+12.0 V See 图
7-5, 表8-3
Receiver recessive state differential
input voltage range, bus biasing inactive
(VDiff)
VIT(ENrec)
0.4
–3
VCM
Common mode range: normal
12
12
V
V
See 图7-5, 表8-3
See 图7-5, 表8-3
–12
–12
VCM(EN)
Common mode range: standby mode
VCANH = VCANL = 5 V, Vsup to GND via 0
Ω and 47 kΩresistor
Power-off (unpowered) bus input
leakage current
IIOFF(LKG)
5
µA
Input capacitance to ground (CANH or
CANL)
CI
25
14
pF
pF
CID
Differential input capacitance
TXD_INT = VCCINT, normal mode: -2.0 V
≤VCANH ≤+7.0 V; -2.0 V ≤VCANL ≤+
7.0 V
RID
Differential input resistance
60
100
kΩ
Single ended Input resistance (CANH or -2.0 V ≤VCANH ≤+7.0 V; -2.0 V
RIN
30
50
1
kΩ
CANL)
≤VCANL ≤+ 7.0 V
Input resistance matching: [1 –
(RIN(CANH) / (RIN(CANL))] × 100%
RIN(M)
VCANH = VCANL = 5.0 V
%
–1
VCCOUT SUPPLY TERMINAL
ICCOUT = -70 mA to 0 mA; VSUP = 5.5 V
to 18 V; -40°C < TA < 85°C
VCCOUT
5 V output supply
Drop out voltage
Line regulation
4.75
5
5.25
500
50
V
VCCOUT = 5 V, VSUP = 12 V, ICCOUT = 70
mA
VDROP
300
mV
mV
VSUP = 5.5 V to 30 V, ΔVCCOUT, ICCOUT
= 10 mA
ΔVCC(ΔVSUP)
VSUP = 14 V, ICCOUT = 1 mA to 70
mA, ΔVCCOUT, –40℃≤TA ≤125℃
ΔVCC(Δ
Load regulation
60
mV
V
VSUPL)
UVCCOUT
Under voltage threshold on VCCOUT
4.2
4.55
FLTR TERMINAL
VMEASURE Voltage measured at FLTR pin
C(FLTR) Filter pin capacitor
1.5
V
External filter capacitor
300
330
nF
INH OUTPUT TERMINAL (HIGH VOLTAGE OUTPUT)
High-level voltage drop INH with respect
to VSUP
IINH = - 0.5 mA
0.5
1
V
ΔVH
ILKG(INH)
Leakage current
INH = 0 V, Sleep Mode
0.7
µA
–0.5
SUP–2
–25
WAKE INPUT TERMINAL (HIGH VOLTAGE INPUT)
VIH
VIL
IIH
High-level input voltage
Low-level input voltage
High-level input current
Low-level input current
Standby mode, WAKE pin enabled
Standby mode, WAKE pin enabled
V
V
V
V
SUP–3
µA
µA
WAKE = VSUP–1 V
–15
IIL
WAKE = 1 V
15
25
Wake up filter time from a wake edge on
WAKE; standby, sleep mode
tWAKE
WAKE filter time
50
µs
SDI, SCK, GPIO1 INPUT TERMINALS
VIH
VIL
IIH
High-level input voltage
0.7
VIO
VIO
µA
Low-level input voltage
0.3
1
High-level input leakage current
Inputs = VIO = 5.25 V
–1
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MAX UNIT
6.7 Electrical Characteristics (continued)
over operating free-air temperature range for –40 ℃≤TA ≤125 ℃(unless otherwise noted)
PARAMETER
TEST CONDITIONS (1)
MIN
TYP
IIL
Low-level input leakage current
Input capacitance
Inputs = 0 V, VIO = 5.25 V
µA
pF
–100
–5
CIN
18 MHz
10
12
Unpowered leakage current (SDI and
SCK only)
ILKG(OFF)
Inputs = 5.25 V, VIO = VSUP = 0 V
1
µA
–1
nCS INPUT TERMINAL
VIH
High-level input voltage
0.7
VIO
VIO
µA
µA
µA
VIL
Low-level input voltage
0.3
1
IIH
High-level input leakage current
Low-level input leakage current
Unpowered leakage current
nCS = VIO = 5.25 V
–1
–50
–1
IIL
nCS = VIO = 5.25 V
–5
1
ILKG(OFF)
nCS = 5.25 V, VIO = VSUP = 0 V
RST INPUT TERMINAL
VIH
High-level input voltage
0.7
VIO
VIO
µA
µA
µA
µs
VIL
Low-level input voltage
0.3
10
1
IIH
High-level input leakage current
Low-level input leakage current
Unpowered leakage current
RST = VIO = 5.25 V
RST = 0 V
1
–1
IIL
ILKG(OFF)
RST = VIO, VSUP = 0 V
7.5
–7.5
30
tPULSE_WIDTH Width of the input pulse
SDO, GPIO1, GPO2 OUTPUT TERMINAL; nINT (OPEN DRAIIN) and nWKRQ (WHEN PROGRAMMED TO WORK OFF OF VIO AND IS
OPEN DRAIN)
VOH
VOL
High-level output voltage
Low-level output voltage
0.8
VIO
VIO
0.2
nWKRQ OUTPUT TERMINAL (DEFAULT INTERNAL VOLTAGE RAIL)
Default value when based upon internal
voltage rail
VOH
VOL
High-level output voltage
Low-level output voltage
2.8
3.6
0.7
V
V
Default value when based upon internal
voltage rail
OSC1 TERMINAL AND CRYSTAL SPECIFICATION
VIH
VIL
High-level input voltage
Low-level input voltage
0.85
1.10
0.3
VIO
VIO
Clock-In frequency tolerance , see
section Crystal and Clock Input
Requirements
FOSC1
20 MHz
40 MHz
0.5
0.5
%
%
–0.5
Clock-In frequency tolerance, see
section Crystal and Clock Input
Requirements
FOSC1
–0.5
tDC
Input duty cycle
45
55
60
%
ESR
Crystal ESR for load capacitance (2)
Ω
(1) All TXD_INT, RXD_INT and EN_INT references are for internal nodes that represent the same functions for a physical layer
transceiver.
(2) Specified by design
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6.8 Timing Requirements
over operating free-air temperature range for –40 ℃≤TA ≤125 ℃(unless otherwise noted)
MIN
TYP
MAX UNIT
MODE CHANGE TIMES (FULL DEVICE)
Standby to normal mode change time based upon SPI
write
tMODE_STBY_NOM
70
200
200
µs
µs
µs
SPI write to go to Sleep from Normal: INH and nWKRQ
turned off, See 图7-15
tMODE_NOM_SLP
tMODE_SLP_STBY
WUP or LWU event until INH and nWKRQ asserted, See
图7-14
tMODE_SLP_STBY_VCCOUT_ON
tMODE_NOM_STBY
1.5
ms
µs
WUP or LWU event until VCCOUT on, See 图7-14
200
SPI write to go to standby from normal mode, See 图7-16
6.9 Switching Characteristics
over operating free-air temperature range for –40 ℃≤TA ≤125 ℃(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SWITCHING CHARACTERISTICS (CAN TRANSCEIVER ONLY)
Propagation delay time, high TXD_INT
tpHR
50
35
85
75
110
100
ns
ns
to Driver Recessive (1)
See 图7-4, RST = 0 V. Typical
conditions: RL = 60 Ω, CL = 100 pF,
RCM = open
Propagation delay time, low TXD_INT to
driver dominant (1)
tpLD
tsk(p)
tR/F
30
55
40
75
ns
ns
Pulse skew (|tpHR –tpLD|)
Differential output signal rise time:
8
Propagation delay time, bus recessive
input to high RXD_INT output
tpRH
tpDL
35
55
55
90
90
ns
ns
See 图7-5, typical conditions: CANL =
1.5 V, CANH = 3.5 V.
Propagation delay time, bus dominant
input to RXD_INT low output
35
DEVICE SWITCHING CHARACTERISTICS
See 图7-6, RST = 0 V. typical
conditions: RL = 60 Ω, CL = 100 pF,
CRXD = 15 pF
tLOOP
Loop delay(3)(CAN transceiver only)
235
1.8
2.9
ns
µs
Bus time to meet filtered bus
requirements for wake up request
tWK_FILTER
0.5
0.5
See 图8-6, standby mode.
See 图8-6
Bus wake-up timeout: time that a WUP
must take place within to be considered
valid
tWK_TIMEOUT
ms
Timer is reset and restarted when bus
changes from dominant to recessive or
vice versa.
tSILENCE
Timeout for bus inactivity (6)
0.6
2
1.2
6
s
Time required for the processor to clear
wake flag or put the device into normal
mode upon power up, power on reset or
after wake event otherwise the device
will enter sleep mode (6)
tINACTIVE
4
min
Time from the start of a dominant-
recessive-dominant sequence
Each phase 6 µs until Vsym ≥0.1.
See 图7-10
tBias
250
250
5
µs
µs
(6)
tPower_Up
tTXD_INT_DTO
Power up time on VSUP
See 图7-13
Dominant time out(2) (CAN transceiver
only)(1)
1
ms
See 图8-7, RL = 60 Ω, CL = open
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MAX UNIT
6.9 Switching Characteristics (continued)
over operating free-air temperature range for –40 ℃≤TA ≤125 ℃(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
TRANSMITTER AND RECEIVER SWITCHING CHARACTERISTICS
Transmitted recessive bit width @ 2
Mbps
tBit(Bus)2M
tBit(Bus)5M
435
155
530
210
ns
ns
See 图7-5, RST = 0 V typical
conditions: RL = 60 Ω, CL = 100 pF,
CRXD = 15 pF
Transmitted recessive bit width @ 5
Mbps
See 图7-5, RST = 0 V typical
conditions: RL = 60 Ω, CL = 100 pF,
CRXD = 15 pF
Transmitted recessive bit width @ 8
Mbps
(5)
tBit(Bus)8M
80
135
ns
tBit(RXD)2M
tBit(RXD)5M
Received recessive bit width @ 2 Mbps
Received recessive bit width @ 5 Mbps
400
120
550
220
ns
ns
See 图7-5, RST = 0 V typical
conditions: RL = 60 Ω, CL = 100 pF,
CRXD = 15 pF,
See 图7-5, RST = 0 V typical
conditions: RL = 60 Ω, CL = 100 pF,
CRXD = 15 pF
(5)
tBit(RXD)8M
Received recessive bit width @ 8 Mbps
80
135
ns
Receiver Timing symmetry @ 2 Mbps
Receiver Timing symmetry @ 5 Mbps
30
5
40
15
ns
ns
See 图7-5, RST = 0 V typical
conditions: RL = 60 Ω, CL = 100 pF,
CRXD = 15 pF
–65
–45
(4)
ΔtRec
SPI SWITCHING CHARACTERISTICS
fSCK
tSCK
tRSCK
tFSCK
tSCKH
tSCKL
tCSS
tCSH
tCSD
tSISU
tSIH
SCK, SPI clock frequency (6)
SCK, SPI clock period (6)
SCK rise time (6)
18
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
56
See 图7-12
10
10
See 图7-11
SCK fall time (6)
See 图7-11
SCK, SPI clock high (6)
SCK, SPI clock low (6)
Chip select setup time (6)
Chip select hold time (6)
Chip select disable time (6)
Data in setup time (6)
Data in hold time (6)
Data out valid (6)
18
18
28
28
125
5
See 图7-12
See 图7-12
See 图7-11
See 图7-11
See 图7-11
See 图7-11
10
See 图7-11
tSOV
tRSO
tFSO
20
10
10
VIO = 3.135 V to 5.25 V, See 图7-12
See 图7-12
SO rise time (6)
SO fall time (6)
See 图7-12
(1) All TXD_INT, RXD_INT, EN_INT and CAN transceiver only references are for internal nodes that represent the same functions for a
stand-alone transceiver.
(2) The TXD_INT dominant time out (tTXD_INT_DTO) disables the driver of the transceiver once the TXD_INT has been dominant longer
than tTXD_INT_DTO, which releases the bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may
only transmit dominant again after TXD_INT has been returned HIGH (recessive). While this protects the bus from local faults, locking
the bus dominant, it limits the minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits
(on TXD_INT) for the worst case, where five successive dominant bits are followed immediately by an error frame. This, along with the
tTXD_INT_DTO minimum, limits the minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11/ tTXD_INT_DTO =
11 bits / 1.2 ms = 9.2 kbps.
(3) Time span from signal edge on TXD_INT input to next signal edge with same polarity on RXD output, the maximum of delay of both
signal edges is to be considered.
(4) ΔtRec = tBit(RXD) –tBit(Bus)
(5) Characterized but not 100% tested
(6) Specified by design
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6.10 Typical Characteristics
38
36
34
32
30
28
26
24
22
20
105
100
95
90
85
80
75
70
65
60
55
50
45
40
35
-40 °C
25 °C
55 °C
85 °C
100 °C
125 °C
-40 °C
25 °C
55 °C
85 °C
100 °C
125 °C
6
8
10
12
14
16
18
20
22
24
D001
6
8
10
12
14
16
18
20
22
24
D003
VSUP (V)
VSUP (V)
VCCOUT = 0 V
ICCOUT = 0 mA
VCCOUT = 5 V
ICCOUT = 70 mA
CAN Transceiver Off
CAN Bus Load = 60 Ω
图6-2. ISUP Current Across Temperature and VSUP
图6-1. ISUP vs VSUP Sleep Mode
LDO Output Only.
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7 Parameter Measurement Information
备注
All TXD_INT, RXD_INT and EN_INT references are for internal nodes that represent the same
functions for a physical layer transceiver. In test mode these can be brought out to pins to test the
transceiver or CAN FD controller.
Standby Mode (Low
Normal Mode
Power)
CANH
Vdiff
Vdiff
CANL
Recessive
Dominant
Recessive
Time, t
图7-1. Bus States (Physical Bit Representation)
CANH
VCC/2
A
RXD_INT
Bias
Unit
B
CANL
A. A: Selective Wake
B. B: Standby and Sleep Modes (Low Power)
图7-2. Simplified Recessive Common Mode Bias Unit and Receiver
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CANH
TXD_INT
RL
CL
CANL
图7-3. Supply Test Circuit
RCM
CANH
VCC
50%
50%
TXD_INT
TXD_INT
0 V
RL
CL
VOD
VCM
VO(CANH)
tpLD
tpHR
90%
10%
CANL
RCM
0.9 V
VO(CANL)
VOD
0.5 V
tR
tF
图7-4. Driver Test Circuit and Measurement
CANH
1.5 V
RXD_INT
IO
0.9 V
VID
0.5 V
0 V
VID
tpDL
tpRH
VOH
VO
CL_RXD_INT
CANL
90%
70%
VO(RXD_INT)
30%
10%
VOL
tF
tR
图7-5. Receiver Test Circuit and Measurement
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RCM
CANH
VI
TXD_INT
tLOOP
Falling
edge
VI
RL
CL
VCM
70%
TXD_INT
30%
30%
CANL
RCM
EN_INT
0 V
0 V
5 x tBIT(TXD_INT)
tBIT(TXD_INT)
RXD_INT
tBIT(Bus)
VO
CL_RXD_INT
900 mV
VDiff
500 mV
VOH
70%
RXD_INT
30%
VOL
tLOOP
rising
edge
tBIT(RXD_INT)
图7-6. Transmitter and Receiver Timing Behavior Test Circuit and Measurement
CANH
VIH
TXD_INT
30%
TXD_INT
RL
CL
VOD
0 V
VOD(D)
CANL
0.9 V
VOD
0.5 V
0 V
tTXD_INT_DTO
图7-7. TXD_INT Dominant Timeout Test Circuit and Measurement
200 ꢀs
IOS
CANH
TXD_INT
VBUS
IOS
CANL
VBUS
VBUS
0 V
or
0 V
VBUS
VBUS
图7-8. Driver Short-Circuit Current Test and Measurement
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VSUP
VSUP
VWAKE
VSUP - 2
VWAKE
VSUP - 3
VSUP
INH
0 V
CVSUP
tWAKE
TCAN4550
OR
tWAKE
VWAKE
INH = H
INH = H
INH
INH
VSUP -1 V
VSUP -1 V
图7-9. tWAKE While Monitoring INH Output
VDIFF
2.0 V
1.15 V
0.4 V
t > tWAKE_FILTER(MAX)
t > tWAKE_FILTER(MAX)
t > tWAKE_FILTER(MAX)
VSYM
0.1
tBias
图7-10. Test Signal Definition for Bias Reaction Time Measurement
tCSD
nCS
tCSH
tRSCK
tFSCK
tCSS
SCLK
tSISU
tSIH
SDI
MSB In
LSB
In
SDO
图7-11. SPI AC Characteristic Write
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nCS
tSCK
tSCKL
tSCKH
SCLK
tSOV
tRSO
tFSO
SDO
LSB
Out
MSB Out
SDI
图7-12. SPI AC Characteristic Read
14 V
~ 5.5 V
UVSUP
VSUP
1.67 V to
4.14 V
14 V
VSUP œ 1V
INH
tPower_Up
nWKRQ
VIO
VIO on and ramp time are system dependent and not specified
FLTR
VCCOUT
tMODE_SLP_STBY_VCCOUT_ON
UVCCOUT Cleared
CLKIN is dependent on external source
and timing will not be specified
tCRYSTAL
VIO required for Crystal/CLKIN to work.
This is the stable internal clock.
Crystal/CLKIN
STANDBY MODE
Transceiver Ready
nINT
图7-13. Power Up Timing
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14V
VSUP
Wake Event
WUP or LWU
14V
VSUP œ 1V
INH
tMODE_SLP_STBY
nWKRQ
VIO
VIO on and ramp time are system dependent and not specified
FLTR
VCCOUT
tMODE_SLP_STBY_VCCOUT_ON
UVCCOUT Cleared
VIO required for Crystal/CLKIN to work.
This is the stable internal clock.
CLKIN is dependent on external source
and timing will not be specified
tCRYSTAL
Crystal/CLKIN
nINT
STANDBY MODE
Transceiver Ready
图7-14. Sleep to Standby Timing
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14V
VSUP
SPI Mode
Change
Normal to
Sleep CMD
14V
VSUP œ 1V
INH
tMODE_NOM_SLP
nWKRQ
VIO
VIO off and ramp time are system dependent and not specified
FLTR
EN_VCCOUT_S
tSILENCE Expires
VCCOUT off ramp time is system dependent and not specified
VCCOUT
Crystal/CLKIN
VIO required for Crystal/CLKIN to work.
Mode
NOM:SLP
Sleep Mode
Normal Mode
图7-15. Normal to Sleep Timing
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14 V
VSUP
SPI Mode
Change
Normal to
Standby CMD
14 V
INH
nWKRQ
Low
High
VIO
FLTR
5 V
VCCOUT
Crystal/CLKIN
Mode
NOM:SLP
Standby Mode
Normal Mode
tMODE_NOM_STBY
Transceiver
图7-16. Normal to Standby Timing
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8 Detailed Description
8.1 Overview
The TCAN4550-Q1 is a CAN FD controller with an integrated CAN FD transceiver supporting data rates up to 8
Mbps. The CAN FD controller meets the specifications of the ISO 11898-1:2015 high speed Controller Area
Network (CAN) data link layer and meets the physical layer requirements of the ISO 11898-2:2016 High Speed
Controller Area Network (CAN) specification providing an interface between the CAN bus and the CAN protocol
controller supporting both classical CAN and CAN FD up to 5 megabits per second (Mbps). The TCAN4550-Q1
provides CAN FD transceiver functionality: differential transmit capability to the bus and differential receive
capability from the bus. The device includes many protection features providing device and CAN bus robustness.
The device can also wake-up via remote wake-up using CAN bus implementing the ISO 11898-2:2016 Wake-Up
Pattern (WUP). Input or Output support for 3.3 V and 5 V microprocessors using VIO pin for seamless interface.
The TCAN4550-Q1 has a Serial Peripheral Interface (SPI) that connects to a local microprocessor for the
device's configuration; transmission and reception of CAN frames. The SPI interface supports clock rates up to
18 MHz.
The CAN bus has two logical states during operation: recessive and dominant. See 图7-1 and 图7-2.
In the recessive bus state, the bus is biased to a common mode of 2.5 V via the high resistance internal input
resistors of the receiver of each node. Recessive is equivalent to logic high. The recessive state is also the idle
state.
In the dominant bus state, the bus is driven differentially by one or more drivers. Current flows through the
termination resistors and generates a differential voltage on the bus. Dominant is equivalent to logic low. A
dominant state overwrites the recessive state.
During arbitration, multiple CAN nodes may transmit a dominant bit at the same time. In this case, the differential
voltage of the bus is greater than the differential voltage of a single driver.
Transceivers with low power Standby Mode have a third bus state where the bus terminals are weakly biased to
ground via the high resistance internal resistors of the receiver. See 图 7-1 and 图 7-2. The TCAN4550-Q1
supports auto biasing, see 节9.1.3.1
The TCAN4550-Q1 has the ability to configure many of the pins for multiple purposes and are described in more
detail in 节 8.3 section. Much of the parametric data is based on internal links like the TXD/RXD_INT which
represent the TXD and RXD of a standalone CAN transceiver. The TCAN4550-Q1 has a test mode that maps
these signals to an external pin in order to perform compliance testing on the transceiver (TXD/RXD_INT_PHY)
and CAN core (TXD/RXD_INT_CAN) independently.
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8.2 Functional Block Diagram
VSUP
VCCOUT
FLTR
WAKE
INH
VINT
LDO(s)
VLVRX
Filter
VIO
Under
Voltage
CNTL
POR
TCAN4550
VIO
CANH
TXD_INT
RXD_INT
VINT
nWKRQ
TX/RX Data
Buffer
TX/RX CAN-FD
Controller with
Filters
VIO
RST
CAN-FD
SPI
SCLK
SDI
Transceiver
System
Controller
SDO
nCS
CANL
GPO2
nINT
GPIO1
GND
OSC2
OSC1
40 MHz
备注
• OSC1 pin is either a crystal or external clock input
• When OSC1 is used as an external clock input pin OSC2 must be connected directly to ground
• When using an external clock input on OSC1 the input voltage should be the same as the VIO
voltage rail
• The recommended crystal or clock rate to meet CAN FD 5 Mbps rates is 40 MHz
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VCCINT1
Transceiver Block Diagram
VSUP
TXD_INT_PHY
TXD_INT
TXD_INT
CANH
CANL
DOMINANT
TIME OUT
DRIVER
Communication Bus
OVER
TEMP
EN_INT
MODE AND CONTROL LOGIC
VSUP
WAKE
WAKE
WAKE
INH_CNTL
VSUP
VLVRX
UNDER
VOLTAGE
M
U
X
INH
WAKE UP LOGIC /
MONITOR
RXD_INT_PHY
RXD_INT
LOGIC
OUTPUT
Low Power Standby Bus
Receiver & Monitor
RXD_INT
图8-1. CAN Transceiver Block Diagram
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VIO
VIO
Chip
Reset
RST
VIO
SCLK
SCLK
SDI
VIO
SDI
VIO
SDO
SDO
nCS
VIO
GPI
VIO
RXD_INT_CAN
Test Mode
TXD_INT_PHY
GPI01
GPO
SPI & I/O
Controller
VIO
Test Mode
TXD_INT_CAN
GPO2
RXD_INT_PHY
GPO2 œ for all non test mode
VIO
Test Mode
EN_INT
nINT
3P6_SLEEP
WKRQ_3P6_SLEEP
WKRQ_VIO
nWKRQ
图8-2. SPI and Digital IO Block Diagram
8.3 Feature Description
8.3.1 VSUP Pin
This pin connects to the battery supply. It provides the supply to the internal regulators that support the digital
core, CAN transceiver and VCCOUT. This Pin requires a 100 nF capacitor at the pin. See 节 10 for more
information. Upon power-up, VSUP needs to rise above UVSUP rising threshold.
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8.3.2 VIO Pin
The VIO pin provides the digital IO voltage to match the microprocessor IO voltage thus avoiding the
requirements for a level shifter. VIO supports IO pins SPI IO, GPIO1 and GPO2. It also provides power to the
oscillator block supporting the crystal or CLKIN pins. It supports a range of 3.3 V to 5 V ± 5% nominal value
providing the widest range of controller support. This pin requires a 100 nF capacitor at the pin. See 节 10 for
more information.
8.3.3 VCCOUT Pin
An internal LDO provides power for the integrated CAN transceiver and the VCCOUT pin for a total available
current of 125 mA. The amount of current that can be sourced is dependent upon the CAN transceiver
requirements during normal operation. When a bus fault takes place that requires all the current from the LDO,
the device is not able to source current to external components. During sleep mode this regulator is disabled and
no current is provided. Once in the other active modes the regulator is enabled for normal operation. This pin
requires a 10 µF external capacitor as close to the pin as possible. See 节10 for more information.
8.3.4 GND
This pin is a ground pin as is the thermal pad. Both need to connect to a ground plane to support heat
dissipation.
8.3.5 INH Pin
The INH pin is a high voltage output pin that provides voltage from the VSUP minus a diode drop to enable an
external high voltage regulator. These regulators are usually used to support the microprocessor and VIO pin.
The INH function is on in all modes but sleep mode. In sleep mode the INH pin is turned off, going into a high Z
state. This allows the node to be placed into the lowest power state while in sleep mode. If this function is not
required it can be disabled by setting register 16'h0800[9] = 1 using the SPI interface. If not required in the end
application to initiate a system wake-up, INH can be left floating.
备注
This terminal should be considered a "high voltage logic" terminal. It is not a power output thus should
be used to drive the EN terminal of the system’s power management device. It should be not used
as a switch for power management supply itself. This terminal is not reverse battery protected and
thus should not be connected outside of the system module.
8.3.6 WAKE Pin
The WAKE pin is used for a high voltage device local wake-up (LWU). This function is explained further in 节
8.4.3.2 section. The pin is defaulted to bi-directional edge trigger, meaning it recognizes a LWU on either a rising
or falling edge of WAKE pin transition. This default value can be changed via a SPI command that disables the
function, make it a rising edge only or a falling edge only. This is done by using register 16'h0800[31:30]. Pin
requires a 10 nF capacitor to ground for improved transient immunity in applications that route WAKE externally.
If local wake-up functionality is not needed in the end application, WAKE can be tied directly to VSUP or GND.
8.3.7 FLTR Pin
This pin is used to provide filtering for the internal digital core regulator. Pin requires 300 nF of capacitance to
ground. See 节10 for more information.
8.3.8 RST Pin
The RST pin is a device reset pin. It has a weak internal pull-down resistor for normal operation. If
communication has stopped with the TCAN4550-Q1, the RST pin can be pulsed high and then back low for
greater than tPULSE_WIDTH to perform a power on reset to the device. This resets the device to the default settings
and puts the device into standby mode. If the device was in normal or standby mode the INH and nWKRQ pins
remain active (on) and do not toggle; see 图 8-3. If the device is in sleep mode and reset is toggled the device
enters standby mode and at that time INH and nWKRQ turns on; see 图8-4.
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After a RST has taken place, a wait time of ≥ 700 µs should be used before reading or writing to the
TCAN4550-Q1.
14V
VSUP
tPULSE_WIDTH
RST
14V
INH
nWKRQ
Low
High
VIO
≥ 700 µs
Device ready to be
read and written to
Device SPI
Access
Standby Mode
Normal
or
Standby
Mode
图8-3. Timing for RST Pin in Normal and Standby Modes
14V
VSUP
tPULSE_WIDTH
RST
14V
≥ 250 µs
INH
Low
Float
nWKRQ
Low
High
VIO
≥ 700 µs
Device ready to be
read and written to
Device SPI
Access
Standby Mode
Sleep Mode
图8-4. Timing for RST Pin in Sleep Mode
8.3.9 OSC1 and OSC2 Pins
These pins are used for a crystal oscillator. The OSC1 pin can also be used as a single-ended clock input from
the microprocessor or some other clock source. See 节 9.1 section for further information on the functions of
these pins. It is recommended to provide a 40 MHz crystal or CLKIN to support CAN FD data rates.
If using a crystal oscillator rather than a single-ended clock, much care must be taken when choosing the correct
load capacitance and dampening resistor values. Please see the TCAN455x Clock Optimization and Design
Guidelines application note for a full, detailed design procedure on the crystal oscillator choice and component
decisions.
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8.3.10 nWKRQ Pin
This pin is a dedicated wake-up request pin from a bus wake (WUP) request, local wake (LWU) request and
power on (PWRON). The nWKRQ pin is defaulted to a wake enable based upon a wake event. In this
configuration the output is pulled low and latched to serve as an enable for a regulator that does not use the INH
pin to control voltage level. The nWKRQ pin can be configured by setting 16'h0800[8] = 1 as an interrupt pin that
pulls the output low, but once the wake interrupt flag is cleared it releases the output back to a high. This pin
defaults to an internal 3.6 V rail that is active during sleep mode. In this configuration, if a wake event takes
place, the nWKRQ pin switches from high to low. This output can be configured to be powered from the VIO rail
through SPI programming, 16'h0800[19]. When powered off of the VIO pin, the device does not insert an interrupt
until the VIO rail is stable. When configured for VIO, this pin is an open drain output and requires an external pull-
up resistor to VIO rail. This configuration bit is saved for all modes of operation and does not reset in sleep mode.
As some external regulators or power management chips may need a digital logic pin for a wake-up request, this
pin can be used.
备注
• This pin is active low and is logical OR of CANINT, LWU and WKERR register 16'h0820 that are
not masked
• If a pull-up resistor is placed on this pin it must be configured for power from the VIO rail
8.3.11 nINT Interrupt Pin
The nINT is a dedicated open drain global interrupt output pin. This pin needs an external pull-up resistor to VIO
to function properly. All interrupt requests are reflected by this pin when pulled low.
In test mode, this pin is used as an EN pin input for testing the CAN transceiver and is shown as EN_INT
throughout the document. When this pin is high, the device is in normal mode and when low it is in standby
mode. This is accomplished by writing 0 to register 16'h0800[0].
备注
This pin is an active low and is the logical OR of all faults in registers 16'h0820 and 16'h0824 that are
not masked.
8.3.12 GPIO1 Pin
This pin defaults out as the M_CAN_INT 1 (active low) interrupt. The functionality of the pin can be changed to a
configurable output function pin by setting register 16'h0800[15:14] = 00. The GPO function is further configured
by using register 16'h0800[11:10]. To configure the pin to support a watchdog input timer reset pin use SPI
register 16'h0800[15:14] = 10.
When in test mode the GPIO1 pin is used to provide the input signal for the transceiver (TXD_INT_PHY) or the
input to the M_CAN core (RXD_INT_CAN). This is accomplished by first putting the device into test mode using
register 16'h0800[21] = 1 and then selecting which part of the device is to be tested by setting register
16'h0800[0]
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8.3.13 GPO2 Pin
The GPO2 pin is an open drain configurable output function pin that provides selected interrupts. This pin needs
an external pull-up resistor to VIO to function properly. The output function can be changed by using register
16'h0800[23:22] and can be configured as a watchdog output reset pin.
In test mode, this pin becomes the RXD_INT_PHY transceiver output or TXD_INT_CAN CAN Controller output
pin.
8.3.14 CANH and CANL Bus Pins
These are the CAN high and CAN low differential bus pins. These pins are connected to the CAN transceiver
and the low voltage WUP CAN receiver. The functionality of these is explained throughout the document. See
section 节9.1.3.1 for can bus biasing.
8.4 Device Functional Modes
The TCAN4550-Q1 has several operating modes: normal, standby, and sleep modes and two protected modes.
The first three mode selections are made by the SPI register. The two protected modes are modified standby
modes used to protect the device or bus. The TCAN4550-Q1 automatically goes from sleep to standby mode
when receiving a WUP or LWU event. See 表 8-1 for the various modes and what parts of the device are active
during each mode.
The TCAN4550-Q1 state diagram figure, see 图 8-5, shows the biasing of the CAN bus in each of the modes of
operation.
表8-1. Mode Overview
Low
Power
CAN RX
WAKE
Pin
CAN TX/
RX
Memory &
Configuration
Mode
RST Pin
nINT
nWKRQ
INH
GPO2
WD
SPI
GPIO1
OSC
VCCOUT
Normal
L
L
On
On
On
On
On
On
On
On
Off
On
Off
On
On
On
On
On
On
On
On
On
On
Off
On
Saved
Saved
Standby
On/
TSD
Protected
L
On
On
On
On
On
On
On
On
On
On
Off
Off
Saved
UVIO
Protected
Mode
Dependent
L
L
Off
Off
On
On
Off
Off
Off
Off
On
On
On
On
Off
Off
Off
Off
Off
Off
Off
Off
On
Off
Saved
Sleep
Off
Partial Saved
备注
• In test mode the watchdog (WD) function can be used for Mode 01 CAN FD. The pin function for
WD is used by other pins in this mode but WD_ACTION reg16'h0800[17:16] = 00 and 01 are
available and WD_BIT reg16'h0800[18] is how the timer would be reset.
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RST Pin: Set high to
reset device. Once
finished set back low
UVLO VSUP
Continued decrease below UVSUP
low the device will reset and clear
everything and come back on as if
a power up sequence has taken
place entering standby mode
Resets Sleep
Core
Power On
Start Up
Normal Mode
TSD = 1
Power Off
TSD Protected
Standby Mode
Normal Mode
SPI Write
MO = 01
RST: L
Wake Sources: WAKE
INH: H
Wake Pin: Active
All GPIO: Active
SPI: Active
RST: L
Wake Sources: CAN, WAKE
INH: H
RST: L
INH: H
SPI Write
MO = 10
Wake Pin: Active
All GPIO: Active
SPI: Active
Wake Pin: Active
All GPIO: Active
SPI: Active
SPI Write
MO = 00
Sleep Mode
RST: L
Wake Sources: CAN, WAKE
INH: floating
TSD = 1
OSC: Active
VCCOUT: Off
Timer Start
OSC: Active
VCCOUT: Enabled
OSC: Active
VCCOUT: Enabled
SWE timer
times out
Wake Pin: Active
nINT Pin: Off
nWKRQ Pin: Active
Other GPIO: Off
SPI: Off
TSD = 1 &
Timer Expires
TSD = 0 &
Timer Expires
TSD State
TSD Timer
Wake-up Event:
CAN bus
or
SPI Write
MO = 00
OSC: Off
VCCOUT: Off
WAKE Pin
UVIO = 1
NOTE: Upon a wake event the device will
transition into Standby mode and must be
reconfigured using SPI
UVIO Protected
UVIO = 0
RST: L
Wake Sources: CAN, WAKE
INH: H
Normal Mode
UVIO = 1
UVIO State
UVIO Timer
UVIO = 1 &
Timer Expires
Wake Pin: Active
All GPIO: Off
SPI: Off
Note:
ñ
OSC: Off
VCCOUT: On
Timer Start
UVIO Protected status will lose the CLKIN/Crystal. During this time the digital core will reset and the M_CAN will have to be
reprogrammed. If timer times out and UVIO = 1 the device goes to sleep at which time all are cleared.
If a Thermal Shutdown and UVIO event take place at the same time the device will enter sleep mode until the faults are rectified
ñ
图8-5. Device State Diagram
8.4.1 Normal Mode
This is the normal operating mode of the device. The CAN driver and receiver are fully operational and CAN
communication is bi-directional. The driver translates a digital input on the internal TXD_INT signal from the CAN
FD controller to a differential output on CANH and CANL. The receiver translates the differential signal from
CANH and CANL to a digital output on the internal RXD_INT signal to the CAN FD controller. Normal mode is
enabled or disabled via the SPI interface.
备注
If an under-voltage event has taken place and cleared, the interrupt flags have to be cleared before
the device can enter normal mode.
8.4.2 Standby Mode
In standby mode, the bus transmitter does not send data nor will the normal mode receiver accept data. There
are several blocks that are active in this mode. The low power CAN receiver is active, monitoring the bus for the
wake-up pattern (WUP). The wake pin monitor is active. The SPI interface is active so that the microprocessor
can read and write registers in the memory for status and configuration. The INH pin is active in order to supply
an enable to the VIO controller if this function is used. The nWKRQ pin is low in this mode in the default
configuration and can also be used as a digital enable pin to an external regulator or power management
integrated circuit (PMIC). All other blocks are put into the lowest power state possible. This is the only mode that
the TCAN4550-Q1 automatically switches to without a SPI transaction. The device goes from sleep mode to
standby mode automatically upon a bus WUP event or a local wake-up from the wake pin. Upon entry to
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Standby Mode, only one wake interrupt is given (either LWU or CANINT). New wake interrupts are not given in
standby mode unless the device changes to normal or sleep mode and then back to standby. This prevents CAN
traffic from spamming the processor with interrupts while in standby, and it gives the processor the first wake
interrupt that was issued.
Upon power up, a power on reset or wake event from sleep mode the TCAN4550-Q1 enters standby mode. This
starts a four-minute timer, tINACTIVE, that requires the processor to either reset the interrupt flags or configure the
device to normal mode. This feature makes sure the node is in the lowest power mode if the processor does not
come up properly. This automatic mode change also takes place when the device has been put into sleep mode
and receives a wake event, WUP or LWU. To disable this feature for sleep events, register 16'h0800[1]
(SWE_DIS) must be set to one. This will not disable the feature when powering up or when a power on reset
takes place.
8.4.3 Sleep Mode
Sleep mode is similar to the standby mode except the SPI interface and INH is disabled. As the low power CAN
receiver is powered off of VSUP the implementer can turn off VIO. The nWKRQ pin is powered off the VSUP supply
internal logic level regulator. This allows the TCAN4550-Q1 to provide an interrupt to the MCU when a wake
event takes place without requiring VIO to be up. When the device goes into sleep mode, the power to the
registers and memory is removed to conserve power. This requires the device to be re-configured prior to being
put into normal mode. As the SPI interface is turned off, the only ways to exit sleep mode is by a wake-up event,
RST pin toggle or power cycle. A sleep mode status flag is provided to determine if the device entered sleep
mode through normal operation or if a fault caused the mode change. Register 16'h0820[23] provides the status.
If a fault causes the device to enter sleep mode, this flag is set to a one.
备注
Difference between sleep and standby mode
• Sleep mode reduces whole node power by shutting off INH/nWKRQ to MCU VREG and shuts off
SPI.
• Standby mode reduces TCAN4550-Q1 power as INH and nWKRQ is enabled turning on node
MCU VREG and SPI interface is active.
备注
When entering sleep mode, it is possible for the TCAN4550-Q1 to assert an interrupt due to UVCCOUT
event as the LDO is powering down. This interrupt should be ignored or can be masked out by using
16'h830[22] before initiating the go to sleep command.
8.4.3.1 Bus Wake via RXD_INT Request (BWRR) in Sleep Mode
The TCAN4550-Q1 supports low power sleep mode, and uses a wake-up from the CAN bus mechanism called
bus wake via RXD_INT Request (BWRR). Once this pattern is received, the TCAN4550-Q1 automatically
switches to standby mode and inserts an interrupt onto the nINT and nWKRQ pins to indicate to a host
microprocessor that the bus is active, and it should wake-up and service the TCAN4550-Q1. The low power
receiver and bus monitor are enabled in sleep mode to allow for RXD_INT Wake Requests via the CAN bus. A
wake-up request is output to the internal RXD_INT (driven low) as shown in 图 8-7. The wake logic monitors
RXD_INT for transitions (high to low) and reactivate the device to standby mode based on the RXD_INT Wake
Request. The CAN bus terminals are weakly pulled to GND during this mode, see 图7-2.
These devices use the wake-up pattern (WUP) from ISO 11898-2:2016 to qualify bus traffic into a request to
wake the host microprocessor. The bus wake request is signaled to the integrated CAN FD controller by a falling
edge and low corresponding to a “filtered”bus dominant on the RXD_INT terminal (BWRR).
The wake-up pattern (WUP) consists of
• A filtered dominant bus of at least tWK_FILTER followed by
• A filtered recessive bus time of at least tWK_FILTER followed by
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• A second filtered dominant bus time of at least tWK_FILTER
Once the WUP is detected, the device starts issuing wake-up requests (BWRR) on the RXD_INT signal every
time a filtered dominant time is received from the bus. The first filtered dominant initiates the WUP and the bus
monitor is now waiting on a filtered recessive, other bus traffic does not reset the bus monitor. Once a filtered
recessive is received, the bus monitor is now waiting on a filtered dominant and again, other bus traffic does not
reset the bus monitor. Immediately upon receiving the second filtered dominant and verification of receiving a
WUP, the device transitions the bus monitor into BWRR mode. This indicates all filtered dominant bus times on
the RXD_INT internal signal by driving it low for the dominant bus time that is in excess of tWK_FILTER. The
RXD_INT output during BWRR matches the classical 8-pin CAN devices that used the single, filtered dominant
on the bus as the wake-up request mechanism from ISO 11898-2:2016.
For a dominant or recessive to be considered “filtered”, the bus must be in that state for more than tWK_FILTER
time. Due to variability in the tWK_FILTER the following scenarios are applicable.
• Bus state times less than tWK_FILTER(MIN) are never detected as part of a WUP, and thus no BWRR is
generated.
• Bus state times between tWK_FILTER(MIN) and tWK_FILTER(MAX) may be detected as part of a WUP and a BWRR
may be generated.
• Bus state times more than tWK_FILTER(MAX) is always detected as part of a WUP, and thus, a BWRR is always
be generated.
See 图8-6 for the timing diagram of the WUP.
The pattern and tWK_FILTER time used for the WUP and BWRR prevents noise and bus stuck dominant faults
from causing false wake requests while allowing any CAN or CAN FD message to initiate a BWRR. If the device
is switched to normal mode or an under-voltage event occurs on VCC, the BWRR is lost. The WUP pattern must
take place within the tWK_TIMEOUT time; otherwise. the device is in a state waiting for the next recessive and then
a valid WUP pattern.
Bus Wake via RXD
Request
Wake Up Pattern (WUP) where t ≤ tWK_TIMEOUT
Filtered
Dominant
Filtered
Dominant
Filtered
Recessive
Waiting for
Filtered
Dominant
Waiting for
Filtered
Recessive
Bus
Bus VDiff
≥ tWK_FILTER
≥ tWK_FILTER
≥ tWK_FILTER
≥ tWK_FILTER
Filtered Dominant RXD Output
Bus Wake Via RXD Requests
RXD_INT
tMODE_SLP_STBY
INH
nWKRQ
图8-6. Wake-Up Pattern (WUP) and Bus Wake via RXD_INT Request (BWRR)
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Fault is repaired & transmission capability
restored
TXD fault stuck dominant: example PCB failure or bad software
tTXD_DTO
TXD_INT (driver)
Driver disabled freeing bus for other nodes
Normal CAN communication
Bus would be —stuck dominant“ blocking communication for the whole network but TXD DTO
prevents this and frees the bus for communication after the time tTXD_DTO
.
CAN Bus
Signal
tTXD_DTO
Communication from other
bus node(s)
Communication from repaired
node
RXD_INT
(receiver)
Communication from other
bus node(s)
Communication from repaired
local node
Communication from local
node
图8-7. Example timing diagram with TXD_INT DTO
8.4.3.2 Local Wake-Up (LWU) via WAKE Input Terminal
The WAKE terminal is a high voltage input terminal which can be used for local wake-up (LWU) request via a
voltage transition. The terminal triggers a LWU event on either a low to high or high to low transition as it has bi-
directional input thresholds. This terminal may be used with a switch to VSUP or ground. If the terminal is not
used, it should be pulled to ground or VSUP to avoid unwanted wake-up events.
The LWU circuitry is active in sleep mode and standby mode. If a valid LWU event occurs, the device transitions
to standby mode. The LWU circuitry is not active in normal mode. To minimize system level current consumption,
the internal bias voltages of the terminal follows the state on the terminal. The wake filter time for a valid wake to
avoid glitches on wake pin is provided by filter value of tWAKE(MIN). A constant high level on WAKE has an
internal pull-up to VSUP and a constant low level on WAKE has an internal pull-down to GND. On power-up, this
may look like a LWU event and could be flagged as such.
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Wake
Threshold
Not Crossed
t ≤ tWAKE
No Wake
UP
t ≥ tWAKE
Wake UP
Wake
Local Wake Request
INH
RXD_INT
*
Mode
Sleep Mode
Standby Mode
图8-8. Local Wake-Up: Rising Edge
Wake
Threshold
Not Crossed
t ≤ tWAKE
No Wake
UP
t ≥ tWAKE
Wake UP
Wake
Local Wake Request
INH
*
RXD_INT
Mode
Sleep Mode
Standby Mode
图8-9. Local Wake-Up: Falling Edge
备注
RXD_INT is an internal signal and can be seen in Transceiver test mode when VIO is present.
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8.4.4 Test Mode
The TCAN4550-Q1 includes a test mode that has four configurations. Two are enabled by the SPI interface
using the configuration register by setting register bit 16'h0800[21] = 1. In this mode the transceiver
TXD_INT_PHY or CAN core RXD_INT_CAN can be mapped to the GPIO1 pin and RXD_INT_PHY or
TXD_INT_CAN can be mapped to the GPO2 pin. EN_INT pin is mapped to the nINT pin, see 图 8-10 and 图
8-11. This is accomplished by setting register 16'h0800[0] to 0 for transceiver testing or 1 for M_CAN core
testing. This mapping is only valid when in test mode. There are two M_CAN core specific test modes entered
using SPI but written to the M_CAN core registers directly, see 图8-12 and 图8-13.
EN_INT
nINT
GPIO1
TXD_INT_PHY
CANH
CANL
SCLK
SDI
TX
RX
SPI
System
Controller
MCAN
Core
SDO
nCS
RXD_INT_PHY
GPO2
图8-10. Transceiver Test Mode
GPIO1
RXD_INT_CAN
V
CANH
CANL
SCLK
SDI
TX
SPI
MCAN
System
Core
SDO
nCS
Controller
RX
TXD_INT_CAN
GPO2
图8-11. SPI and M_CAN Core Test Mode
V
CANH
CANL
SCLK
SDI
= 1
TX
RX
SPI
System
Controller
MCAN
Core
SDO
nCS
图8-12. M_CAN Internal Loop Back Test Mode
CANH
CANL
SCLK
SDI
TX
RX
SPI
System
Controller
MCAN
Core
SDO
nCS
图8-13. M_CAN External Loop Back Test Mode
8.4.5 Failsafe Feature
The TCAN4550-Q1 has three methods the failsafe feature is used in order to reduce node power consumption
for a node system issue. Failsafe is the method the device uses to enter sleep mode from various other modes
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when specific issues arise. This feature uses the Sleep Wake Error (SWE) timer to determine if the node
processor can communicate to the TCAN4550-Q1. The SWE timer is default enabled through the SWE_DIS;
16'h0800[1] = 0 but can be disabled by writing a one to this bit. Even when the timer is disabled, a power on
reset re-enables the timer and thus be active. Failsafe Feature is default disabled but can be enabled by writing
a one to 16'h0800[13], FAILSAFE_EN.
Upon power up, the SWE timer starts, tINACTIVE, the processor has typically four minutes to configure the
TCAN4550-Q1, clear the PWRON flag or configure the device for normal mode; see 图8-14. This feature cannot
be disabled. If the device has not had the PWRON flag cleared or been placed into normal mode, it enters sleep
mode. The device wakes up if the CAN bus provides a WUP or a local wake event takes place, thus entering
standby mode. Once in standby mode, tSILENCE and tINACTIVE timers starts. If tINACTIVE expires, the device re-
enters sleep mode.
The second failure mechanism that causes the device to use the failsafe feature, if enabled, is when the device
receives a CANINT, CAN bus wake (WUP) or WAKE pin (LWU), while in sleep mode such that the device leaves
sleep mode and enters standby mode. The processor has four minutes to clear the flags and place the device
into normal mode. If this does not happen the device enters sleep mode.
The third failure mechanism that causes the device to use the failsafe feature is when in standby or normal mode
and the CANSLNT flag persists for tINACTIVE, the device enters sleep mode. Examples of events that could
create this are CLKIN or Crystal stops working, processor is no longer working and not able to exercise the SPI
bus, a go-to-sleep command comes in and the processor is not able to receive it or is not able to respond. See
state diagram 图8-15.
Standby Mode
Power On
Start Up
SWE Timer
tINACTIVE
No &
Cleared
Does timer
Expire and PWRON
flag cleared?
Stays in STBY mode
or switches to Normal
mode if programmed
Timed out
Sleep Mode
RST: L
Wake Sources: CAN, WAKE
INH: floating
Wake Pin: Active
nINT Pin: Off
nWKRQ Pin: Active
Other GPIO: Off
SPI: Off
OSC: Off
VCCOUT: Off
图8-14. Power On Failsafe Feature
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Normal Mode
0800[13] = 1
Fail Safe Mode En
Bus Inactivity
tSILENCE timer
expires
Standby Mode
0800[13] = 1
setting CANSLNT
flag
Fail Safe Mode En
Bus Inactivity
SWE Timer
tINACTIVE
Monitoring CAN
No &
Cleared
Activity detected
leaving device in
current mode or
placing in selected
mode
Does timer
Expire and required
flags cleared?
Timed out
Sleep Mode
RST: L
Wake Sources: CAN, WAKE
INH: floating
Wake Pin: Active
nINT Pin: Off
nWKRQ Pin: Active
Other GPIO: Off
SPI: Off
OSC: Off
VCCOUT: Off
图8-15. Normal and Standby Failsafe Feature
8.4.6 Protection Features
The TCAN4550-Q1 has several protection features that are described as follows.
8.4.6.1 Watchdog Function
The TCAN4550-Q1 contains a watchdog (WD) timeout function. When using the WD timeout function, the WD
runs continuously. The WD is default enabled and can be configured with four different timer values. WD is
active in normal and standby modes and off in sleep mode. Once the device enters standby or normal mode, the
timer does not start until the first input trigger event. This event can be either writing a one to register
16'h0800[18] or if selected, by changing the voltage level on the GPIO1 pin either high or low when configured
for watchdog input. If the first trigger is not set, the watchdog is disabled. The first trigger can happen in standby
mode or normal mode. This is system implementation specific. While the timer is running, a SPI command
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writing a one to 16'h0800[18] resets the WD_TIMER timer or if configured for pin control the GPIO1 behaves as
the watchdog input bit.
The TCAN4550-Q1 has two ways of setting the trigger bit: via a SPI command and, if selected, through a GPI
(GPIO1 configured as GPI). When a GPI pin is used any rising or falling edge resets the timer. A watchdog event
can be conveyed back to the microprocessor in two methods: interrupt on nINT pin or, if selected, the GPO2 pin
can be programmed to toggle upon a WD timeout. A timeout can initiate one of three actions by the TCAN4550-
Q1: interrupt, INH toggle plus putting the device into standby mode or toggle watchdog output reset pin if
enabled. The input CLKIN or crystal values needs to be entered into reg 16'h0800[27] and is either 20 MHz or 40
MHz. See 表8-2 for the register settings for the watchdog function.
备注
• If the device enters UVIO protected mode, the watchdog timer is held in reset. When the device
returns to standby mode, the timer resumes counting.
• Once the command to enter sleep mode takes place, the WD timer is turned off and does not
trigger a watchdog event.
• If the any of the watchdog registers needs to be changed, the watchdog must be disabled and the
change made and then re-enabled.
表8-2. Watchdog Registers and Descriptions
Address
BIT(S)
Field
Type
Reset
DESCRIPTION
WD_TIMER: Watchdog timer
00 = 60 ms
01 = 600 ms
10 = 3 s
29:28
WD_TIMER
R/W
2'b00
11 = 6 s
CLK_REF: CLKIN/Crystal frequency reference
0 = 20 MHz
27
CLK_REF
R/W
R/W
1'b1
1 = 40 MHz
GPO2_CONFIG: GPO2 configuration
00 = No action
GPO2_CONFI
G
01 = M_CAN_INT 0 interrupt (active low)
10 = Watchdog output
23:22
2'b00
11 = Mirrors nINT pin
16'h0800
WD_BIT_SET: write a 1 to reset timer: if times out; this bit is set and then
the selected action from register 16'h0800[17:16] takes place.
Note: This is a self-clearing bit. Writing a 1 resets the timer and then the bit
clears.
18
WD_BIT_SET
WD_ACTION
W1C
R/W
1'b0
WD_ACTION: Selected action when WD_TIMER times out
00 = Set interrupt flag and if a pin is configured to reflect WD output as an
interrupt the pin shows a low.
01 = Pulse INH pin and place device into standby mode –high - low - high
≈300ms
17:16
2'b00
10 = Pulse watchdog output pin if enabled –high - low - high ≈300ms
11 = Reserved
Note: Interrupt flag is always set for a WD timeout event.
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表8-2. Watchdog Registers and Descriptions (continued)
Address
BIT(S)
Field
Type
Reset
DESCRIPTION
GPIO1_CONFIG: GPIO1 Pin Function Select
00 = GPO
GPIO1_CONFI
G
01 = Reserved
15:14
RW
2'b01
10 = GPI –Automatically becomes a WD input trigger pin.
16'h0800
11 = Reserved
WD_EN - Watchdog Enable
0 = Disable
3
WD_EN
RXU
1'b1
1 = Enabled
8.4.6.2 Driver and Receiver Function
The TXD_INT and RXD_INT are internal signal paths that behave like the TXD and RXD pins for a physical layer
transceiver. During normal operation they are not accessible to external pins. The TCAN4550-Q1 provides a test
mode that maps these signals to external pins see 节 8.4.4. The digital logic input and output levels for these
devices are CMOS levels with respect to VIO for compatibility with protocol controllers having 3.3 V to 5 V logic
or I/O. 表8-3 and 表8-4 provides the states of the CAN driver and CAN receiver in each mode.
表8-3. Driver Function Table
BUS OUTPUTS
DEVICE MODE
TXD_INT INPUT
DRIVEN BUS STATE
Dominant
CANH
CANL
L
H
Z
Z
Z
L
Z
Z
Z
Normal
H or Open
Biased Recessive
Weak Pull to GND
Weak Pull to GND
Standby
Sleep
X
X
表8-4. Receiver Function Table Normal and Standby Modes
CAN DIFFERENTIAL INPUTS
DEVICE MODE
BUS STATE
RXD_INT TERMINAL
VID = VCANH –VCANL
Dominant
Undefined
Recessive
Dominant
Undefined
Recessive
Open
L
VID ≥0.9 V
Normal
0.5 V < VID < 0.9 V
VID ≤0.5 V
Undefined
H
VID ≥1.15 V
Standby/Sleep
Any
0.4 V < VID < 1.15 V
VID ≤0.4 V
See 图8-6
H
Open (VID ≈0 V)
8.4.6.3 Floating Terminals
There are internal pull-ups and pull-downs on critical terminals to place the device into known states if the
terminal floats. See 表8-5 for details on terminal bias conditions.
表8-5. Terminal Bias
TERMINAL
SCLK
SDI
PULL-UP or PULL-DOWN
COMMENT
Pull-up
Pull-up
Pull-up
Weakly biases input
Weakly biases input
nCS
Weakly biases input so the device is not selected
Weakly biases output when using internal voltage rail. When using
open-drain configuration, an external pull-up is needed.
nWKRQ
RST
Pull-up
Pull-down
Weakly biases RST terminal towards normal operation mode
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备注
The internal bias should not be relied upon as only termination, especially in noisy environments but
should be considered a failsafe protection. Special care needs to be taken when the device is used
with MCUs utilizing open drain outputs.
8.4.6.4 TXD_INT Dominant Timeout (DTO)
The TCAN4550-Q1 supports dominant state timeout. This is an internal function based upon the TXD_INT path.
The transceiver can be tested for this by placing the device into test mode and putting a dominant on the GPIO1
pin and monitor the GPO2 for RXD_INT_PHY. The TXD_INT DTO circuit prevents the local node from blocking
network communication in the event of a hardware or software failure where TXD_INT is held dominant (low)
longer than the timeout period tTXD_INT_DTO. The TXD_INT DTO circuit is triggered by a falling edge on TXD_INT.
If no rising edge is seen before the timeout constant of the circuit, tTXD_INT_DTO, the CAN driver is disabled. This
frees the bus for communication between other nodes on the network. The CAN driver is re-activated when a
recessive signal (high) is seen on TXD_INT terminal, thus clearing the dominant timeout. The receiver remains
active and the RXD_INT terminal reflects the activity on the CAN bus and the bus terminals is biased to
recessive level during a TXD_INT DTO fault.
备注
The minimum dominant TXD_INT time allowed by the TXD_INT DTO circuit limits the minimum
possible transmitted data rate of the device. The CAN protocol allows a maximum of eleven
successive dominant bits (on TXD_INT) for the worst case, where five successive dominant bits are
followed immediately by an error frame.
8.4.6.5 CAN Bus Short Circuit Current Limiting
This device has several protection features that limit the short circuit current when a CAN bus line is shorted.
These include CAN driver current limiting. The device has TXD_INT dominant timeout which prevents
permanently having the higher short circuit current of dominant state in case of a system fault. During CAN
communication the bus switches between dominant and recessive states, thus the short circuit current may be
viewed either as the current during each bus state or as a DC average current. For system current and power
considerations in the termination resistors and common mode choke ratings the average short circuit current
should be used. The percentage dominant is limited by the TXD_INT dominant timeout and CAN protocol which
has forced state changes and recessive bits such as bit stuffing, control fields, and inter frame space. These
ensure there is a minimum recessive amount of time on the bus even if the data field contains a high percentage
of dominant bits.
备注
The short circuit current of the bus depends on the ratio of recessive to dominant bits and their
respective short circuit currents. The average short circuit current may be calculated using 方程式1.
IOS(AVG) = %Transmit x [(%REC_Bits x IOS(SS)_REC) + (%DOM_Bits x IOS(SS)_DOM)] + [%Receive x IOS(SS)_REC] (1)
Where
• IOS(AVG) is the average short circuit current.
• %Transmit is the percentage the node is transmitting CAN messages.
• %Receive is the percentage the node is receiving CAN messages.
• %REC_Bits is the percentage of recessive bits in the transmitted CAN messages.
• %DOM_Bits is the percentage of dominant bits in the transmitted CAN messages.
• IOS(SS)_REC is the recessive steady state short circuit current and IOS(SS)_DOM is the dominant steady
state short circuit current.
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备注
The short circuit current and possible fault cases of the network should be taken into consideration
when sizing the power ratings of the termination resistance, other network components, and the power
supply used to generate VSUP
.
8.4.6.6 Thermal Shutdown
This is a device preservation event. If the junction temperature of the device exceeds the thermal shut down
threshold, the device turns off the internal 5 V LDO for the CAN transceiver thus blocking the signal to bus
transmission path as well as turning of the ability to source current and voltage to the VCCOUT pin. A thermal shut
down interrupt flag is set and an interrupt is inserted so that the microprocessor is informed. If this event
happens, other interrupt flags may be set as an example a bus fault where the CAN bus is shorted to Vbat. When
this happens the digital core and SPI interface are still active. After a time of ≈ 300 ms the device checks the
temperature of the junction. The thermal shutdown (TSD) timer starts when TSD fault event starts and exits to
standby mode when a TSD fault is not present when the TSD timer is expired. While in thermal shut down
protected mode a SPI write to change the device to either Normal or Standby mode is ignored while writes to
change to sleep mode is accepted.
备注
If a thermal shut down event happens while the device is experiencing a VIO under voltage event the
device enters sleep mode.
8.4.6.7 Under-Voltage Lockout (UVLO) and Unpowered Device
The TCAN4550-Q1 monitors the VSUP , VIO and VCCOUT pin for under-voltage events. These voltage rails have
under-voltage detection circuitry which places the device into a protected state if an under voltage fault occurs
for UVSUP and UVIO. This protects the bus during an under-voltage event on these terminals. If VSUP is in under
voltage, the device loses the source needed to keep the internal regulators active. This causes the device to go
into a state where communication between the microprocessor and the TCAN4550-Q1 is disabled. The
TCAN4550-Q1 is not able to receive information from the bus, and thus does not pass any signals from the bus,
including any Bus Wake via BWRR signals to the microprocessor. See 表8-6.
8.4.6.7.1 UVSUP and UVCCOUT
When VSUP drops to UVSUP level, the VCC CAN transceiver regulator loses the ability to maintain 5 V output. At
this point, the UVCCOUT interrupt flag is set and the TCAN4550-Q1 turns off the regulator and place the CAN
transceiver into a standby state. If VSUP returns to minimum levels the device enters standby mode. If VSUP
continues to decrease to the power on reset level, the TCAN4550-Q1 shuts everything down. When VSUP
returns to acceptable levels the device will come up the same as initial power on. All registers are cleared and
the device has to be reconfigured.
8.4.6.7.2 UVIO
If VIO drops below UVIO under the voltage detection threshold, several functions are disabled. The transceiver
switches off until VIO has recovered. The input clock or crystal circuits are disabled and the IO between the
TCAN4550-Q1 and microprocessor is not active. When UVIO triggers, the tUV timer starts. If the timer times out
and the UVIO is still there, the device enters sleep mode, see 图 8-5. Once in sleep mode, a wake event is
required to place the TCAN4550-Q1 into standby mode and enables the INH pin. As registers are cleared in
sleep mode the UVIO interrupt flag is lost. If the UVIO event is still in place, the cycle repeats. If during a thermal
shut down event a UVIO event happens, the device automatically enters sleep mode.
The device is designed to be an "ideal passive" or “no load” to the CAN bus if the device is unpowered. The
bus terminals (CANH, CANL) have extremely low leakage currents when the device is unpowered so it does not
load the bus. This is critical if some nodes of the network are unpowered while the rest of the of network remains
operational. Logic terminals also have extremely low leakage currents when the device is unpowered, so they do
not load other circuits which may remain powered.
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The UVLO circuit monitors both rising and falling edge of a power rail when ramping and declining.
表8-6. Under Voltage Lockout I and O Level Shifting Devices
VSUP
VIO
VCCOUT
> UVCCOUT
< UVCCOUT
NA
DEVICE STATE
BUS
RXD_INT
> UVSUP
> UVSUP
< UVSUP
> UVSUP
< UVSUP
> UVVIO
> UVVIO
> UVVIO
< UVVIO
< UVVIO
Normal
Per TXD_INT
High Impedance
High Impedance
Recessive
Mirrors Bus
Protected
Protected
Protected
Protected
High (Recessive)
High (Recessive)
High Impedance
High Impedance
> UVCCOUT
NA
High Impedance
备注
Once an under-voltage condition and interrupt flags are cleared and the VSUP supply has returned to
valid level, the device typically needs tMODE_CHANGE to transition to normal operation. The host
processor should not attempt to send or receive messages until this transition time has expired. If EN
is low and VSUP has an under-voltage event, the device goes into a protected mode which disables
the wake-up receiver and places the RXD_INT output into a high impedance state.
8.4.6.7.3 Fault and M_CAN Core Behavior:
During a UVIO, UVCCOUT or TSD fault the TCAN4550-Q1 automatically does the following to keep the M_CAN
core in a known state. A write of 1 to CCCR.INIT will be issued anytime there is a transition from Normal →
Standby. Any currently pending TX or RX processing is halted. Once the device re-enters Normal mode, a write
of 0 to CCCR.INIT is issued, and any pending messages (TXBRP active bits) is automatically transmitted.
8.4.7 CAN FD
The TCAN4550-Q1 performs CAN communication according to ISO 11898-1:2015 and Bosch CAN protocol
specification 3.2.1.1.
8.5 Programming
The TCAN4550-Q1 uses 32-bit accesses. The TCAN4550-Q1 provides 2K bytes of MRAM that is fully
configurable for TX/RX buffer/FIFO as needed based upon the system needs. To avoid ECC errors right after
initialization, the MRAM should be zeroed out during the initialization, power up, power on reset and wake
events, a process thus ensuring ECC is properly calculated.
备注
At power up, MRAM values are unknown and thus ECC values is not valid. It is important that at least
2 words (8 bytes) of payload data be written into any TX buffer element, even if the DLC is less than 8.
Failure to do this results in a M_CAN BEU error, which puts the TCAN4550-Q1 device into
initialization mode, and require user intervention before CAN communication can continue. One way
to avoid this, the MRAM should be zeroed out after power up, a power on reset or coming out of sleep
mode.
MRAM does not refer to Magnetoresistive Random Access Memory, it refers to Message RAM as
defined the Bosch MCAN definition.
8.5.1 SPI Communication
The SPI communication uses a standard SPI interface. Physically the digital interface pins are nCS (Chip Select
Not), SDI (Slave Data In), SDO (Slave Data Out) and SCLK (SPI Clock). Each SPI transaction is a 32-bit word
containing a command byte followed by two address bytes and length bytes. The data shifted out on the SDO
pin for the transaction always starts with the Global Status Register (byte). This register provides the high-level
status information about the device status. The two data bytes which are the ‘response’to the command byte
are shifted out next. Data bytes shifted out during a write command is content of the registers prior to the new
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data being written and updating the registers. Data bytes shifted out during a read command are the current
content of the registers and the registers will not be updated.
The SPI input data on SDI is sampled on the low to high edge of the SCLK. The SPI output data on SDO is
changed on the high to low edge of the SCLK.
8.5.1.1 Chip Select Not (nCS):
This input pin is used to select the device for a SPI transaction. The pin is active low, so while nCS is high the
SDO pin of the device is high impedance allowing a SPI bus to be designed. When nCS is low the SDO driver is
activated and communication may be started. The nCS pin is held low for a SPI transaction. A special feature on
this device allows the SDO pin to immediately show the Global Fault Flag on a falling edge of nCS.
8.5.1.2 SPI Clock Input (SCLK):
This input pin is used to input the clock for the SPI to synchronize the input and output serial data bit streams.
The SPI Data Input is sampled on the rising edge of SCLK and the SPI Data Output is changed on the falling
edge of the SCLK.
SPI CLOCKING
ACTIONs: C = data capture, S = data shift,
L = load data out, P = process captured data
MODE 0 (CPOL = 0, CPHA = 0)
SCLK
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SDI. SDO
ACTION
L
C
S
C
S
C
S
C
S
C
S
C
S
C
S
C
L
C
S
C
S
C
S
C
S
C
S
C
S
C
S
C
P
P
INTERNAL
CLK
INTERNAL_CLK = !CS xor CLK
图8-16. SPI Clocking
8.5.1.3 SPI Data Input (SDI):
This input pin is used to shift data into the device. Once the SPI is enabled by a low on nCS the SDI samples,
the input shifted data on each rising edge of the SCLK. The data is shifted into a 32-bit shift register. If the
command code was a write, the new data is written into the addressed register only after exactly 32 bits have
been shifted in by SCLK and the nCS has a rising edge to deselect the device. If there are not exactly a multiple
of 32 bits shifted in to the device, the during one SPI transaction (nCS low) the last word of the transfer is
ignored, the SPIERR flag is set.
备注
Due to needing multiples of 32 bits on each SPI transaction, the device should be wired for parallel
operation of the SPI as a bus with control to the device via nCS and not as a daisy chain of shift
registers.
8.5.1.4 SPI Data Output (SDO):
This pin is high impedance until the SPI output is enabled via nCS. Once the SPI is enabled by a low on nCS,
the SDO is immediately driven high or low showing the Global Fault Flag status which is also the first bit (bit 32)
to be shifted out if the SPI is clocked. Once SCLK begins, on the first low to high edge of the clock, the SDO
retains the Global Fault Flag which is the first bit (bit 31) shifted out. On the first falling edge of SCLK, the shifting
out of the data continues with each falling edge on SCLK until all 32 bits have been shifted out the shift register.
8.5.2 Register Descriptions
The Addresses for each area of the device are as follows:
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• Register 16'h0000 through 16'h000C are Device ID and SPI Registers
• Register 16'h0800 through 16'h083C are device configuration registers and Interrupt Flags
• Register 16'h1000 through 16'h10FC are for M_CAN
• Register 16'h8000 through 16'h87FF is for MRAM.
The start address must be word aligned (32-bit). Any time the registers are accessed, bits [1:0] of the address
are ignored as the addresses are always word (32-bit/4-byte) aligned. As an example for accessing the M_CAN
registers, for the register 0x1004, give the SPI address 1004, 1005, 1006 or 1007, and access register 1004.
The registers are 32-bit and only 1004 is valid in this example.
When entering the MRAM start address, the 0x8000 prefix is not necessary. For example, if the desired start
address is 0x8634, then bits SA[15:0] is 0x0634.
表8-7 provides programming op Codes.
表8-7. Access Commands
NAME
OP CODE
DESCRIPTION
USAGE
< WRITE_B_FL > <2 address bytes>
<1 length byte>
WRITE_B_FL (burst: one
SPI transfer Length: fixed)
Write one or more
addresses
8'h61
<length words of write data>
< READ_B_FL > <2 address bytes>
<1 length byte>
READ_B_FL (burst: one
SPI transfer Length: fixed)
Read one or more internal
SPI addresses
8'h41
<length words of read data>
Notes:
• The two low order address bits is ignored
• A length of 8’h00 indicates 256 words to be transferred
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WRITE_B_FL
nCS
SCLK
SDI
LENGTH[7:0]
=8'H02
CMD: WRITE_B_FL = 8'h61
ADDRESS [15:8]
ADDRESS [7:0]
SDO
Reg0820[7:0]
nCS
SCLK
SDI
DATA_0[31:24]
DATA_0[23:16]
DATA_0[15:8]
DATA_0[7:0]
SDO
nCS
SCLK
SDI
DATA_1[31:24]
DATA_1[23:16]
DATA_1[15:8]
DATA_1[7:0]
SDO
图8-17. Write
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READ_B_FL
nCS
SCLK
SDI
CMD: READ_B_FL
= 8'h41
LENGTH[7:0]
=8'H02
ADDRESS [15:8]
ADDRESS [7:0]
SDO
Reg0820[7:0]
nCS
SCLK
SDI
SDO
DATA_0[31:24]
DATA_0[23:16]
DATA_0[15:8]
DATA_0[7:0]
nCS
SCLK
SDI
SDO
DATA_1[31:24]
DATA_1[23:16]
DATA_1[15:8]
DATA_1[7:0]
图8-18. Read (Command OpCode 8h41)
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8.6 Register Maps
The TCAN4550-Q1 has a comprehensive register set with 32-bit addressing. The register is broken down into
several sections:
• 节8.6.1.
• 节8.6.2.
• 节8.6.3.
• 节8.6.4.
备注
All addresses are the lower order 16 address bit within the defined 32-bit address space.
Upper 16 address bits are ignored.
8.6.1 Device ID and Interrupt/Diagnostic Flag Registers: 16'h0000 to 16'h002F
This register block provided the device name and revision level. It provides all the interrupt flags as well.
表8-8. Device ID and Interrupt/Diagnostic Flag Registers
TCAN4550
VALUE
ADDRESS
REGISTER
ACCESS
DEVICE_ID[7:0] "T"
54
R
R
R
R
R
R
R
R
DEVICE_ID[15:8] "C"
DEVICE_ID[23:16] "A"
DEVICE_ID[31:24] "N"
DEVICE_ID[39:32] "4"
DEVICE_ID[47:40] "5"
DEVICE_ID[55:48] "5"
DEVICE_ID[63:56] "0"
43
‘h0000
41
4E
34
35
‘h0004
35
30
SPI_2_revision, 8’h00 (Reserved), REV_ID Major, REV_ID Minor REV_ID
Major
00
00
R
R
‘h0008
‘h000C
Status
表8-9. Device Configuration Access Type Codes
Access Type
Code
Description
Read Type
R
R
Read
Write Type
W
W
W
Write
Write
WC
Reset or Default Value
-n
Value after reset or the default value
Undefined
U
U
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8.6.1.1 DEVICE_ID1[31:0] (address = h0000) [reset = h4E414354]
图8-19. Device ID1
31
23
15
7
30
22
14
6
29
21
13
5
28
27
26
18
10
2
25
17
9
24
16
8
DEVICE_ID1[31:24]
RO
20
19
DEVICE_ID1[23:16]
RO
12
11
DEVICE_ID1[15:8]
RO
4
3
1
0
DEVICE_ID1[7:0]
RO
表8-10. Device ID Field Descriptions
Bit
31:0
Field
DEVICE_ID1[31:0]
Type
Reset
Description
RO
h4E414354
DEVICE_ID1[31:0]
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8.6.1.2 DEVICE_ID2[31:0] (address = h0004) [reset = h30353534]
图8-20. Device ID2
31
23
15
7
30
22
14
6
29
21
13
5
28
27
26
18
10
2
25
17
9
24
16
8
DEVICE_ID2[31:24]
RO
20
19
DEVICE_ID2[23:16]
RO
12
11
DEVICE_ID2[15:8]
RO
4
3
1
0
DEVICE_ID2[7:0]
RO
表8-11. Device ID Field Descriptions
Bit
31:0
Field
DEVICE_ID2[31:0]
Type
Reset
Description
RO
h30353534
DEVICE_ID2[63:32]
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8.6.1.3 Revision (address = h0008) [reset = h00110201]
图8-21. Revision
31
23
15
7
30
22
14
6
29
21
13
5
28
27
26
18
10
2
25
17
9
24
16
8
SPI_2_REVISION
RO
20
12
19
11
RSVD
RO
REV_ID MAJOR
RO
4
3
1
0
REV_ID MINOR
RO
表8-12. Revision Field Descriptions
Bit
Field
Type
Reset
Description
31:24
23:16
15:8
7:0
SPI_2_REVISION
RSVD
RO
h00
Revision version of the SPI module
Reserved
RO
h11
REV_ID MAJOR
REV_ID MINOR
RO
h02
Device REV_ID Major
Device REV_ID Minor
RO
h01
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8.6.1.4 Status (address = h000C) [reset = h0000000U]
图8-22. Status
31
30
29
28
27
26
25
24
RSVD
RO
Internal_read_e Internal_write_e Internal_error_l Read_fifo_unde Read_fifo_empt Write_fifo_overfl
rror
W1C
21
rror
W1C
20
og_write
W1C
19
rflow
W1C
18
y
ow
W1C
16
W1C
17
23
22
RSVD
RO
SPI_end_error Invalid_comma Write_overflow write_underflow Read_overflow read_underflow
nd
W1C
13
W1C
12
W1C
11
W1C
10
W1C
9
W1C
8
15
7
14
6
RSVD
RO
5
4
3
2
1
0
RSVD
RO
Write_fifo_avail Read_fifo_avail Internal_access Internal_error_i SPI_error_interr
Interrupt
able
able
_active
nterrupt
upt
RO
RO
RO
RO
RO
RO
表8-13. Status Field Descriptions
Bit
Field
RSVD
Type
Reset
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
Description
31:30
29
RO
Reserved
Internal_read_error
Internal_write_error
Internal_error_log_write
Read_fifo_underflow
Read_fifo_empty
Write_fifo_overflow
RSVD
W1C
W1C
W1C
W1C
W1C
W1C
RO
Internal read received an error response
Internal write received an error response
Entry written to the Internal error log
28
27
26
Read FIFO underflow after 1 or more read data words returned
Read FIFO empty for first read data word to return
Write/command FIFO overflow
25
24
23:22
21
Reserved
SPI_end_error
W1C
W1C
W1C
SPI transfer did not end on a byte boundary
Invalid SPI command received
20
Invalid_command
Write_overflow
19
SPI write sequence had continue requests after the data transfer
was completed
18
17
16
write_underflow
Read_overflow
read_underflow
W1C
W1C
W1C
SPI write sequence ended with less data transferred then
requested
1’b0
1’b0
1’b0
SPI read sequence had continue requests after the data transfer
was completed
SPI read sequence ended with less data transferred then
requested
15:8
7:6
5
RSVD
RO
RO
RO
Reserved
Reserved
8’h00
1’b0
1’b0
RSVD
Write_fifo_available
write fifo empty entries is greater than or equal to the
write_fifo_threshold
4
Read_fifo_available
RO
Read fifo entries is greater than or equal to the
read_fifo_threshold
1’b0
3
2
1
0
Internal_access_active
Internal_error_interrupt
SPI_error_interrupt
Interrupt
RO
RO
RO
RO
U
Internal Multiple transfer mode access in progress
Unmasked Internal error set
1’b0
1’b0
U
Unmasked SPI error set
Value of interrupt input level (active high)
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8.6.1.5 SPI Error status mask (address = h0010) [reset = h00000000]
图8-23. SPI Error status mask
31
30
29
28
27
26
25
24
RSVD
RO
Mask_Internal_r Mask_Internal_ Mask_Internal_ Mask_Read_fifo Mask_Read_fifo Mask_Write_fifo
ead_error
write_error
error_log_write
_underflow
_empty
_overflow
23
22
21
20
19
18
17
16
RSVD
RO
Mask_SPI_end Mask_Invalid_c Mask_Write_ov Mask_write_un Mask_Read_ov Mask_read_und
_error
ommand
erflow
derflow
erflow
erflow
15
7
14
6
13
12
11
10
9
8
RSVD
RO
5
4
3
2
1
0
RSVD
RO
表8-14. SPI Error status mask Field Descriptions
Bit
Field
RSVD
Type
RO
RW
RW
RW
RW
RW
RW
RO
RW
RW
RW
RW
RW
RW
RO
RO
Reset
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
8’h00
8’h00
Description
31:30
29
Reserved
Mask_Internal_read_error
Mask_Internal_write_error
Mask_Internal_error_log_write
Mask_Read_fifo_underflow
Mask_Read_fifo_empty
Mask_Write_fifo_overflow
RSVD
When set the corresponding error bit will be masked
When set the corresponding error bit will be masked
When set the corresponding error bit will be masked
When set the corresponding error bit will be masked
When set the corresponding error bit will be masked
When set the corresponding error bit will be masked
Reserved
28
27
26
25
24
23:22
21
Mask_SPI_end_error
Mask_Invalid_command
Mask_Write_overflow
Mask_write_underflow
Mask_Read_overflow
Mask_read_underflow
RSVD
When set the corresponding error bit will be masked
When set the corresponding error bit will be masked
When set the corresponding error bit will be masked
When set the corresponding error bit will be masked
When set the corresponding error bit will be masked
When set the corresponding error bit will be masked
Reserved
20
19
18
17
16
15:8
7:0
RSVD
Reserved
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8.6.2 Device Configuration Registers: 16'h0800 to 16'h08FF
Registers not listed are reserved and return h’00.
表8-15. Device Configuration Registers
ADDRESS
0800
REGISTER
VALUE
ACCESS
R/W/U
R/W
R/W
R/W/U
R
Modes of Operation and Pin Configurations
Timestamp Prescaler
Read and Write Test Registers
ECC and TDR Registers
Reserved
h'C8000468
h’00000002
h’00000000
h'00000000
h'00000000
h'00000000
h’00000000
h'00000000
0804
0808
080C –0810
0814 -081C
0820
Interrupt Flags
R
0824
MCAN Interrupt Flags
Reserved
R
R
0829 –082F
0830
Interrupt Enable
R/W
R
h’FFFFFFFF
Reserved
h'00000000
0834 –083F
备注
The following bits are being saved when entering sleep mode and will show up bold in register maps.
• 16'h0800 bits 0, 1, 8, 9, 10, 11, 13, 14, 15, 19, 21, 22, 23, 30 and 31.
• 16'h0820 bits 18, 19 and 21
• 16'h0830 bits 14 and 15
8.6.2.1 Modes of Operation and Pin Configuration Registers (address = h0800) [reset = hC8000468]
图8-24. Modes of Operation and Pin Configuration Registers
31
WAKE_CONFIG
R/W
30
29
28
27
CLK_REF
R/W
26
RSVD
R
25
RSVD
R
24
RSVD
R
WD_TIMER
R/W
23
22
21
20
19
18
17
16
GPO2_CONFIG
TEST_MODE_
EN
RSVD
nWKRQ_VOLT WD_BIT_SET
WD_ACTION
R/W
AGE
R/W
R/W
R
12
R/W
R/W
15
14
13
11
10
9
8
GPIO1_CONFIG
FAIL_SAFE_E
N
RSVD
GPIO1_GPO_CONFIG
INH_DIS
nWKRQ_CONF
IG
R/W
R/W
5
R
4
R/W
R/W
1
R/W
7
6
3
2
0
MODE_SEL
R/W/U
RSVD
RSVD
WD_EN
DEVICE_RESE
T
SWE_DIS
TEST_MODE_
CONFIG
R
R
R/W/U
R/W/U
R/W
R/W
表8-16. Modes of Operation and Pin Configuration Registers Field Descriptions
Bit
Field
Type
Reset
Description
WAKE_CONFIG: Wake pin configuration
00 = Disabled
01 = Rising edge
31:30
WAKE_CONFIG
R/W
2’b11
10 = Falling edge
11 = Bi-Directional –either edge
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表8-16. Modes of Operation and Pin Configuration Registers Field Descriptions (continued)
Bit
Field
Type
Reset
Description
WD_TIMER: Watchdog timer
00 = 60 ms
29:28
WD_TIMER
R/W
01 = 600 ms
2’b00
10 = 3 s
11 = 6 s
CLK_REF: CLKIN/Crystal Frequency Reference
27
CLK_REF
RSVD
R/W
R
1'b1
0 = 20 MHz
1 = 40 MHz
26:24
3'b000
Reserved
GPO2_CONFIG: GPO2 Pin GPO Configuration
00 = No Action
01 = MCAN_INT 0 interrupt (Active low)
10 = Watchdog output
23:22
GPO2_CONFIG
R/W
2’b00
11 = Mirrors nINT pin (Active low)
See NOTE section
TEST_MODE_EN: Test mode enable. When set device is in test
mode
0 = Disabled
1 = Enabled
21
20
19
TEST_MODE_EN
RSVD
R/W
R
1'b0
1'b0
Reserved
nWKRQ_VOLTAGE: nWKRQ Pin GPO buffer voltage rail
configuration:
0 = Internal voltage rail
nWKRQ_VOLTAGE
R/W
1’b0
1 = VIO voltage rail
WD_BIT_SET: Write a 1 to reset timer: if times out, this bit will
set and then the selected action from 0800[17:16] will take
place. (TCAN4x50 Only otherwise reserved) This is a self-
clearing bit. Writing a 1 resets the timer and then the bit clears
18
WD_BIT_SET
WD_ACTION
R/W
R/W
1’b0
WD_ACTION: Selected action when WD_TIMER times out
00 = Set interrupt flag, and if a pin is configure to reflect WD
output as an interrupt the pin will show a low.
01 = Pulse INH pin and places the device into standby mode –
high to low to high ≈300 ms
17:16
2’b00
10 = Pulse watchdog output pin if enabled –high to low to high
≈300 ms
11 = Reserved
NOTE: Interrupt flag is always set for a WD timeout event.
GPIO1_CONFIG: GPIO1 Pin Function Select
00 = GPO
01 = Reserved
15:14
GPIO1_CONFIG
R/W
2’b00
10 = GPI –Automatically becomes a WD input trigger pin.
11 = Reserved
FAIL_SAFE_EN: Fail safe mode enable:
0 = Disabled
1 = Enabled
13
FAIL_SAFE_EN
R/W
R
1'b0
1'b0
NOTE: Excludes power up fail safe.
12
RSVD
Reserved
GPIO1_GPO_CONFIG: GPIO1 pin GPO1 function select
00 = SPI fault Interrupt (Active low)
11:10
GPIO1_GPO_CONFIG
R/W
01 = MCAN_INT 1 (Active low)
2’b01
10 = Under voltage or thermal event interrupt (Active low)
11 = Reserved
INH_DIS: INH Pin Disable
0 = Pin enabled
1 = Pin disabled
9
8
INH_DIS
R/W
R/W
1'b0
1'b0
nWKRQ_CONFIG: nWKRQ Pin Function
0 = Mirrors INH function
nWKRQ_CONFIG
1 = Wake request interrupt
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表8-16. Modes of Operation and Pin Configuration Registers Field Descriptions (continued)
Bit
Field
Type
Reset
Description
MODE_SEL: Mode of operation select
00 = Sleep
01 = Standby
10 = Normal
7:6
MODE_SEL
R/W
2'b01
11 = Reserved
See NOTE section
5
4
RSVD
RSVD
R
R
1'b1
1'b0
If this bit is written to it must be a 1
Reserved
WD_EN: Watchdog Enable
0 = Disabled
1 = Enabled
3
2
WD_EN
R/X/U
R/WC
1’b1
DEVICE_RESET: Device Reset
0 = Current configuration
1 = Device resets to default
NOTE: Same function as RST pin
DEVICE_RESET
1'b0
SWE_DIS: Sleep Wake Error Disable:
0 = Enabled
1 = Disabled
NOTE: This disables the device from starting the four-minute
timer when coming out of sleep mode on a wake event. If this is
enabled, a SPI read or write must take place within this four
minute window or the device will go back to sleep. This does not
disable the function for initial power on or in case of a power on
reset.
1
0
SWE_DIS
R/W
R/W
1'b0
1'b0
Test Mode Configuration
0 = Phy Test with TXD/RXD_INT_PHY and EN_INT are mapped
to external pins
TEST_MODE_CONFIG
1 = CAN Controller test with TXD/RXD_INT_CAN mapped to
external pins
备注
• The Mode of Operation changes the mode, but will read back the current mode of the device.
• When the device is changing, the device to normal mode a write of 0 to CCCR.INIT is
automatically issued. When changing from normal mode to standby or sleep modes, a write of 1 to
CCCR.INIT is automatically issued.
• When GPIO1 is configured as a GPO for interrupts, the interrupts list represent the following and
are active low:
– 00: SPI Fault Interrupt. Matches SPIERR if not masked
– 01: MCAN_INT:1 m_can_int1.
– 10: Under-Voltage or Thermal Event Interrupt: Logical OR of UVCCOUT, UVSUP , UVVIO, TSD
faults that are not masked.
• When GPIO1 is configured as a GPO for interrupts, the interrupts list represent the following and
are active low:
– 00: SPI Fault Interrupt. Matches SPIERR if not masked
– 01: MCAN_INT:1 m_can_int1.
– 10: Under Voltage or Thermal Event Interrupt: Logical OR of UVCCOUT, UVSUP , UVVIO, TSD
faults that are not masked.
• nWKRQ pin defaults to a push-pull active low configuration based off an internal voltage rail. When
configuring this to work off of VIO, the pin becomes and open drain output and a external pull-up
resistor to the VIO rail is required.
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8.6.2.2 Timestamp Prescaler (address = h0804) [reset = h00000002]
图8-25. Timestamp Prescaler
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
RSVD
R
RSVD
R
RSVD
R
1
0
Timestamp Prescaler
R/W
表8-17. EMC Enhancement and Timestamp Prescaler Field Descriptions
Bit
Field
Type
Reset
Description
Reserved
Reserved
Reserved
31:24
23:16
15:8
RSVD
RSVD
RSVD
R
8’h00
8’h00
8’h00
R
R
Writing to this register resets the internal timestamp counter to 0
and will set the internal CAN clock divider used for MCAN
Timestamp generation to (Timestamp Prescaler x 8)
7:0
Timestamp Prescaler
R/W
8'h02
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8.6.2.3 Test Register and Scratch Pad (address = h0808) [reset = h00000000]
Saved in sleep mode
图8-26. Test and Scratch Pad Register
31
23
15
7
30
22
14
6
29
21
13
5
28
27
26
18
10
2
25
17
9
24
16
8
Test Read and Write
R/W
20
19
Test Read and Write
R/W
12
11
Scratch Pad 1
R/W
4
3
1
0
Scratch Pad 2
R/W
表8-18. Test and Scratch Pad Register Field Descriptions
Bit
Field
Type
Reset
Description
31:24
23:16
15:8
7:0
Test Read and Write
Test Read and Write
Scratch Pad 1
RW
Test Read and Write Register
Test Read and Write Register
8’h00
8’h00
8’h00
8’h00
R/W
R/W
R/W
Bits 15:8 are saved when device is configured for sleep mode
Bits 7:0 are saved when device is configured for sleep mode
Scratch Pad 2
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8.6.2.4 Test Register (address = h080C) [reset = h00000000]
图8-27. Test Register
31
30
29
21
28
20
12
27
26
18
25
17
24
16
RSVD
R
23
RSVD
R
22
RSVD
R
19
ECC_ERR_FORCE_BIT_SEL
R/W
15
14
13
11
10
9
8
RSVD
R
RSVD
ECC_ERR_FO ECC_ERR_CH
RSVD
RSVD
RSVD
RCE
R/W
4
ECK
R/W
3
R
5
R
2
R
1
R
0
7
6
RSVD
R
表8-19. Test Register Field Descriptions
Bit
Field
Type
Reset
8’h00
2'b00
Description
Reserved
Reserved
31:24
23:22
RSVD
RSVD
R
R
ECC_ERR_FORCE_BIT_SEL
000000 = Bit 0
000001 = Bit 1
....
6’
b000000
21:16
ECC_ERR_FORCE_BIT_SEL
R/W
100110 = Bit 38
All other bit combinations are Reserved
15:13
12
RSVD
R
Reserved
3’b000
1’b0
ECC_ERR_FORCE
0 = No Force
ECC_ERR_FORCE
R/W
1 = Force a single bit ECC error
ECC_ERR_CHECK
11
ECC_ERR_CHECK
R/W
0 = No Single Bit ECC error detected
1 = Single Bit ECC error detected
1’b0
10
RSVD
RSVD
R
R
1b'0
Reserved
10'b000 Reserved
0000000
9:0
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8.6.3 Interrupt/Diagnostic Flag and Enable Flag Registers: 16'h0820/0824 and 16'h0830
This register block provides all the interrupt flags for the device. As the M-CAN interrupt flags 16'h0824 are
described in 16'h1050 MCAN register description section and will be shown here but need to go to 16'h1050 for
description. 16h’0830 is Interrupt enable to trigger an interrupt for 16'h0820.
8.6.3.1 Interrupts (address = h0820) [reset = h00100000]
图8-28. Interrupts
31
30
RSVD
R
29
RSVD
R
28
RSVD
R
27
RSVD
R
26
RSVD
R
25
24
RSVD
R
CANBUSNOM
RSVD
RU
R
23
22
21
20
19
18
17
16
SMS
UVSUP
R/WC
14
UVIO
R/WC
13
PWRON
R/WC/U
12
TSD
R/WC
11
WDTO
RU/WC
10
RSVD
ECCERR
R/WC
8
R
R
15
9
CANINT
LWU
R/WC
6
WKERR
R/WC
5
RSVD
R
RSVD
R
CANSLNT
R/WC
2
RSVD
CANDOM
R/WC
0
R/WC
R
7
GLOBALERR
R
4
3
1
M_CAN_INT
R
nWKRQ
R
CANERR
R
RSVD
R
SPIERR
R
RSVD
R
VTWD
R
表8-20. Interrupts Field Descriptions
Bit
31
Field
CANBUSNOM
Type
Reset Description
CAN Bus normal (Flag and Not Interrupt)
RU
1'b0
Will change to 1 when in normal mode after first Dom to Rec
transition
30:24
23
RSVD
SMS
R
7b'0000 Reserved
000
R/WC
1'b0
Sleep Mode Status (Flag & Not an interrupt) Only sets when
sleep mode is entered by a WKERR, UVIO timeout, or
UVIO+TSD fault
22
21
20
19
18
17
16
15
14
13
12
11
10
9
UVSUP
UVIO
R/WC
R/WC
1'b0
1'b0
Under-Voltage VSUP and UVCCOUT
Under-Voltage VIO
Power ON
PWRON
TSD
R/WC/U 1'b1
R/WC 1'b0
RU/WC 1'b0
Thermal Shutdown
Watchdog Time Out
Reserved
WDTO
RSVD
R
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
ECCERR
CANINT
LWU
R/WC
R/WC
R/WC
R/WC
R
Uncorrectable ECC error detected
Can Bus Wake-Up Interrupt
Local Wake-Up
Wake Error
WKERR
RSVD
Reserved
RSVD
R
Reserved
CANSLNT
RSVD
R/WC
R
CAN Silent
Reserved
8
CANDOM
GLOBALERR
WKRQ
R/WC
R
CAN Stuck Dominant
Global Error (Any Fault)
Wake Request
7
6
R
5
CANERR
RSVD
R
CAN Error
4
R
RSVD
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表8-20. Interrupts Field Descriptions (continued)
Bit
3
Field
Type
Reset Description
SPIERR
RSVD
R
1'b0
1'b0
1'b0
1'b0
SPI Error
2
R
Reserved
1
M_CAN_INT
VTWD
R
M_CAN global INT
Global Voltage, Temp or WDTO
0
R
GLOBALERR: Logical OR of all faults in registers 0x0820-0824.
WKRQ: Logical OR of CANINT, LWU and WKERR.
CANBUSNOM is not an interrupt but a flag. In normal mode after the first dominant-recessive transition it will set.
It will reset to 0 when entering Standby or Sleep modes or when a bus fault condition takes place in normal
mode.
CANERR: Logical OR of CANSLNT and CANDOM faults.
SPIERR: Will be set if any of the SPI status register 16'h000C[30:16] is set.
• In the event of a SPI underflow, the error is not detected/alerted until the start of the next SPI transaction.
• 16'h0010[30:16] are the mask for these errors
VTWD: Logical or of UVCCOUT, UVSUP, UVVIO, TSD, WDTO (Watchdog time out) and ECCERR.
CANINT: Indicates a WUP has occurred; Once a CANINT flag is set, LWU events will be ignored. Flag can be
cleared by changing to Normal or Sleep modes.
LWU: Indicates a local wake event, from toggling the WAKE pin, has occurred. Once a LWU flag is set, CANINT
events will be ignored. Flag can be cleared by changing to Normal or Sleep modes.
WKERR: If the device receives a wake-up request WUP and does not transition to Normal mode or clear the
PWRON or Wake flag before tINACTIVE, the device will transition to Sleep Mode. After the wake event, a Wake
Error (WKERR) will be reported and the SMS flag will be set to 1.
备注
PWRON Flag is cleared by either writing a 1 or by going to sleep mode or normal mode from standby
mode.
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8.6.3.2 MCAN Interrupts (address = h0824) [reset = h00000000]
图8-29. MCAN Interrupts
31
30
29
ARA
R
28
PED
R
27
PEA
R
26
WDI
R
25
BO
R
24
EW
R
RSVD
R
23
EP
R
22
ELO
R
21
20
19
18
17
16
BEU
R
BEC
R
DRX
R
TOO
R
MRAF
R
TSW
R
15
14
13
12
11
10
9
8
TEFL
R
TEFF
R
TEFW
R
TEFN
R
TFE
R
TCF
R
TC
R
HPM
R
7
6
5
4
3
2
1
0
RF1L
R
RF1F
R
RF1W
R
RF1N
R
RF0L
R
RF0F
R
RF0W
R
RF0N
R
表8-21. MCAN Interrupts Field Descriptions
Bit
Field
Type
Reset
Description
31:30
29
RSVD
ARA
PED
PEA
R
1'b0
Reserved
R
1'b0
ARA: Access to Reserved Address
28
R
1'b0
PED: Protocol Error in Data Phase (Data Bit Time is used)
27
R
PEA: Protocol Error in Arbitration Phase (Nominal Bit Time is
used)
1’b0
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
WDI
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1’b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1’b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1’b0
1'b0
WDI: Watchdog Interrupt
BO
BO: Bus_Off Status
EW
EW: Warning Status
EP
EP: Error Passive
ELO
BEU
BEC
DRX
TOO
MRAF
TSW
TEFL
TEFF
TEFW
TEFN
TFE
ELO: Error Logging Overflow
BEU: Bit Error Uncorrected
BEC: Bit Error Corrected
DRX: Message stored to Dedicated Rx Buffer
TOO: Timeout Occurred
MRAF: Message RAM Access Failure
TSW: Timestamp Wraparound
TEFL: Tx Event FIFO Element Lost
TEFF: Tx Event FIFO Full
TEFW: Tx Event FIFO Watermark Reached
TEFN: Tx Event FIFO New Entry
TFE: Tx FIFO Empty
TCF
TCF: Transmission Cancellation Finished
TC: Transmission Completed
HPM: High Priority Message
RF1L: Rx FIFO 1 Message Lost
RF1F: Rx FIFO 1 Full
TC
8
HPM
RF1L
RF1F
RF1W
RF1N
RF0L
RF0F
7
6
5
RF1W: Rx FIFO 1 Watermark Reached
RF1N: Rx FIFO 1 New Message
RF0L: Rx FIFO 0 Message Lost
RF0F: Rx FIFO 0 Full
4
3
2
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表8-21. MCAN Interrupts Field Descriptions (continued)
Bit
1
Field
Type
Reset
Description
RF0W
RF0N
R
1'b0
RF0W: Rx FIFO 0 Watermark Reached
RF0N: Rx FIFO 0 New Message
0
R
1'b0
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8.6.3.3 Interrupt Enables (address = h0830 ) [reset = hFFFFFFFF]
图8-30. 32-bit, 4 Rows
31
RSVD
R
30
RSVD
R
29
RSVD
R
28
RSVD
R
27
RSVD
R
26
25
RSVD
R
24
RSVD
RSVD
R
R
23
22
21
20
19
18
RSVD
R
17
16
RSVD
R
UVSUP
R/W
14
UVIO
R/W
13
RSVD
R
TSD
R/W
11
RSVD
R
ECCERR
R/W
15
12
10
9
8
CANINT
R/W
7
LWU
R/W
6
RSVD
R
RSVD
R
RSVD
R
CANSLNT
R/W
2
RSVD
R
CANDOM
R
0
5
4
3
1
RSVD
R
表8-22. Interrupt Enables Field Descriptions
Bit
31:24
23
22
21
20
19
18
17
16
15
14
13
12
11
Field
Type
Reset
8'hFF
1'b1
1'b1
1'b1
1'b1
1'b1
1'b1
1'b1
1'b1
1'b1
1'b1
1'b1
1'b1
1'b1
1'b1
1'b1
1'b1
8’hFF
Description
RSVD
RSVD
UVSUP
UVIO
R
Reserved
R
Reserved
R/W
R/W
R
Under-Voltage VSUP and UVCC
Under-Voltage VIO
Reserved
RSVD
TSD
R/W
R
Thermal Shutdown
Reserved
RSVD
RSVD
ECCERR
CANINT
LWU
R
Reserved
R/W
R/W
R/W
R
Uncorrectable ECC error detected
Can Bus Wake-Up Interrupt
Local Wake-Up
Reserved
RSVD
RSVD
RSVD
R
Reserved
R
Reserved
10
9
CANSLNT
RSVD
R/W
R
CAN Silent
Reserved
8
CANDOM
RSVD
R/W
R
CAN Stuck Dominant
Reserved
7:0
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8.6.4 CAN FD Register Set: 16'h1000 to 16'h10FF
The following tables provide the CAN FD programming register sets starting at 16'h1000.
The MRAM and start address for the following registers has special consideration:
• SIDFC (0x1084)
• XIDFC (0x1088)
• RXF0C (0x10A0)
• RXF1C (0x10B0)
• TXBC (0x10C0)
• TXEFC (0x10F0)
The start address must be word aligned (32-bit) in the MRAM. The 2 least significant bits are ignored on a write
to ensure this behavior.
When entering the MRAM start address, the 0x8000 prefix is NOT necessary. For example, if the desired start
address is 0x8634, then bits SA[15:0] will be 0x0634.
表8-23. Legend
Code
Description
R
C
d
Read
Clear on Write
date
n
Value after Reset
Protected Set
Protected Write
Release
p
P
r
S
t
Set on Read
Test Value
Undefined
Write
U
W
X
Reset on Read
表8-24. CAN FD Register Set
ADDRESS
1000
1004
1008
100C
1010
1014
1018
101C
1020
1024
1028
102C
1030
1034
1038
103C
1040
SYMBOL
CREL
ENDN
CUST
DBTP
TEST
RWD
NAME
RESET
ACC
R
Core Release Register
rrrd dddd
Endian Register
8765 4321
0000 0000
0000 0A33
0000 0000
0000 0000
0000 0019
0600 0A03
0000 0000
0000 0000
FFFF 0000
0000 FFFF
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
R
Customer Register
R
Data Bit Timing & Prescaler Register
Test Register
RP
RP
RP
RWPp
RP
RP
RC
RP
RC
R
RAM Watchdog
CCCR
NBTP
TSCC
TSCV
TOCC
TOCV
RSVD
RSVD
RSVD
RSVD
ECR
CC Control Register
Nominal Bit Timing & Prescaler Register
Timestamp Counter Configuration
Timestamp Counter Value
Timeout Counter Configuration
Timeout Counter Value
Reserved
Reserved
R
Reserved
R
Reserved
R
Error Counter Register
RX
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表8-24. CAN FD Register Set (continued)
ADDRESS
1044
1048
104C
1050
1054
1058
105C
1060
1064
1068
106C
1070
1074
1078
107C
1080
1084
1088
108C
1090
1094
1098
109C
10A0
10A4
10A8
10AC
10B0
10B4
10B8
10BC
10C0
10C4
10C8
10CC
10D0
10D4
10D8
10DC
10E0
10E4
10E8
10EC
10F0
10F4
SYMBOL
PSR
NAME
RESET
ACC
RXS
RP
R
Protocol Status Register
0000 0707
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
1FFF FFFF
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
TDCR
RSVD
IR
Transmitter Delay Compensation Register
Reserved
Interrupt Register
RW
RW
RW
RW
R
IE
Interrupt Enable
ILS
Interrupt Line Select
Interrupt Line Enable
Reserved
ILE
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
GFC
Reserved
R
Reserved
R
Reserved
R
Reserved
R
Reserved
R
Reserved
R
Reserved
R
Global Filter Configuration
Standard ID Filter Configuration
Extended ID Filter Configuration
Reserved
RP
RP
RP
R
SIDFC
XIDFC
RSVD
XIDAM
HPMS
NDAT1
NDAT2
RXF0C
RXF0S
RXF0A
RXBC
RXF1C
RXF1S
RXF1A
RXESC
TXBC
TXFQS
TXESC
TXBRP
TXBAR
TXBCR
TXBTO
TXBCF
TXBTIE
TXBCIE
RSVD
RSVD
TXEFC
TXEFS
Extended ID and MASK
High Priority Message Status
New Data 1
RP
R
RW
RW
RP
R
New Data 2
Rx FIFO 0 Configuration
Rx FIFO 0 Status
Rx FIFO 0 Acknowledge
Rx Buffer Configuration
Rx FIFO 1 Configuration
Rx FIFO 1 Status
RW
RP
RP
R
Rx FIFO 1 Acknowledge
Rx Buffer/FIFO Element Size Configuration
Tx Buffer Configuration
Tx FIFO/Queue Status
Tx Buffer Element Size Configuration
Tx Buffer Request Pending
Tx Buffer Add Request
Tx Buffer Cancellation Request
Tx Buffer Transmission Occurred
Tx Buffer Cancellation Finished
Tx Buffer Transmission Interrupt Enable
Tx Buffer Cancellation Finished Interrupt Enable
Reserved
RW
RP
RP
R
RP
R
RW
RW
R
R
RW
RW
R
Reserved
R
Tx Event FIFO Configuration
Tx Event FIFO Status
RP
R
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表8-24. CAN FD Register Set (continued)
ADDRESS
10F8
SYMBOL
TXEFA
RSVD
NAME
RESET
ACC
RW
R
Tx Event FIFO Acknowledge
0000 0000
0000 0000
10FC
Reserved
表8-25. CAN FD Register Set Description
MSB
Offset
Name
Bit Pos.
7:0
LSB
Access
Day[7:0] (two digit, BCD-Coded)
R
R
R
R
R
R
R
R
15:8
23:16
31:24
7:0
Month[15:8] (two digit, BCD-Coded)
1000
CREL
ENDN
CUST
DBTP
TEST
RWD
SUBSTEP[7:4] (One digit, BCD-Coded)
REL[7:4] (One digit, BCD-Coded)
Year[3:0] (one digit, BCD-Coded)
STEP[3:0] (one digit, BCD-Coded)
ETV[7:0] (Endianness Test Value)
15:8
23:16
31:24
7:0
ETV[15:8] (Endianness Test Value)
ETV[23:16] (Endianness Test Value)
ETV[31:24] (Endianness Test Value)
1004
1008
100C
1010
1014
1018
101C
1020
1024
1028
15:8
23:16
31:24
7:0
DTSEG2(Data Time Seg before Sample Point)
Reserved
Reserved
DSJW (Data (Re)Synchronization Jump Width)
RP
RP
RP
R
15:8
23:16
31:24
7:0
DTSEG1(Data Time Seg before Sample Point)
DBRP (Data Bit Rate Prescaler)
TDC
Reserved
RX
TX
LBCK
Reserved
RP-U
R
15:8
23:16
31:24
7:0
Reserved
Reserved
Reserved
R
R
WDC (Watchdog Configuration)
WDV (Watchdog Counter Value)
Reserved
RP
R
15:8
23:16
31:24
7:0
R
Reserved
R
TEST
NISO
DAR
TXP
MON
EFBI
CSR
CSA
ASM
CCE
INIT
RWp
RP
R
15:8
23:16
31:24
7:0
PXHD
Reserved
BRSE
FDOE
CCCR
NBTP
TSCC
TSCV
TOCC
Reserved
Reserved
R
Reserved
NTSEG2 (Nominal time Segment After Sample Point)
RP
RP
RP
15:8
23:16
31:24
7:0
NTSEG1 (Nominal Time Segment Before Sample Point)
NBRP[7:0] (Nominal Bit Rate Prescaler)
NSJW[6;0] (Nominal (RE)Synchronization Jump Width)
NBRP[8]
TSS[1:0] Timestamp Select
RP
RP
R
Reserved
Reserved
15:8
23:16
31:24
7:0
Reserved
TCP (Timestamp Counter Prescaler)
RP
R
Reserved
RC
RC
R
TSC[15:0] (Timestamp Counter)
15:8
23:16
31:24
7:0
Reserved
Reserved
R
Reserved
TOS (Timeout SEL)
ETOC
RP
R
15:8
23:16
31:24
7:0
Reserved
RP
RP
RC
RC
R
TOP[15:0] (Timeout Period)
TOC[15:0] (Timeout Counter)
15:8
23:16
31:24
31:0
102C
TOCV
RSVD
Reserved
Reserved
Reserved
R
R
1030 –103C
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表8-25. CAN FD Register Set Description (continued)
Offset
Name
Bit Pos.
7:0
MSB
LSB
Access
R
TEC (Transmit Error Counter)
REC (Receive Error Counter)
CEL (CAN Error Logging)
Reserved
15:8
23:16
31:24
7:0
R
1040
ECR
X
R
BO
EW
EP
ACT (Activity)
LEC (Last Error Code)
DLEC (Data Phase Last Error Code)
RS
RSX
R
15:8
23:16
31:24
7:0
Reserved
Reserved
PXE
RFDF
RBRS
RESI
1044
PSR
TDCV[6:0] (Transmitter Delay Compensation Value)
Reserved
R
Reserved
Reserved
TDCF (Transmitter Delay Compensation Filter Window Length)
RP
RP
R
15:8
23:16
31:24
31:0
7:0
TDCO (Transmitter Delay Compensation Offset)
1048
104C
1050
TDCR
RSVD
IR
Reserved
Reserved
Reserved
R
R
RF1L
TEFL
EP
RF1F
TEFF
ELO
RF1W
TEFW
BEU
RF1N
TEFN
BEC
RF0L
TFE
RF0F
TCF
RF0W
TC
RF0N
HPM
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
15:8
23:16
31:24
7:0
DRX
TOO
MRAF
BO
TSW
Reserved
ARA
PED
PEA
WDI
EW
RF1LE
TEFLE
EPE
RF1FE
TEFFE
ELOE
RF1WE
TEFWE
BEUE
ARAE
RF1WL
TEFWL
BEUL
RF1NE
TEFNE
BECE
PEDE
RF1NL
TEFNL
BECL
PEDL
RF0LE
TFEE
DRXE
PEAE
RF0LL
TFEL
DRXL
PEAL
RF0FE
TCFE
TOOE
WDIE
RF0FL
TCFL
TOOL
WDIL
RF0WE
TCE
RF0NE
HPME
TSWE
EWE
15:8
23:16
31:24
7:0
1054
1058
IE
MRAFE
BOE
Reserved
RF1LL
TEFLL
EPL
RF1FL
TEFFL
ELOL
RF0WL
TCL
RF0NL
HPML
TSWL
EWL
15:8
23:16
31:24
7:0
ILS
MRAFL
BOL
Reserved
ARAL
Reserved
EINT1
EINT0
15:8
23:16
31:24
31:0
7:0
Reserved
105C
1060 –107C
1080
ILE
RSVD
GFC
Reserved
Reserved
Reserved
R
R
R
Reserved
ANFS
ANFE
RRFS
RRFE
RP
R
15:8
23:16
31:24
7:0
Reserved
Reserved
Reserved
R
R
FLSS[7:2] (Filter List Standard Start Address)
Reserved
RP
RP
RP
R
15:8
23:16
31:24
7:0
FLSS[15:8] (Filter List Standard Start Address)
LSS (List Size Standard)
Reserved
1084
SIDFC
FLESA[7:2] (Filter List Extended Start Address)
Reserved
RP
RP
RP
R
15:8
23:16
31:24
31:0
7:0
FLESA[15:8] (Filter List Extended Start Address)
LSE (List Size Extended)
1088
108C
1090
XIDFC
RSVD
XIDAM
Reserved
Reserved
Reserved
R
EIDM[7:0] (Extended ID AND MASK)
EIDM[15:8] (Extended ID AND MASK)
EIDM[23:16] (Extended ID AND MASK)
RP
RP
RP
RP
15:8
23:16
31:24
Reserved
EIDM[28:24] (Extended ID AND MASK)
BIDX (Buffer Index)
MSI (Message Storage
Index)
7:0
R
15:8
23:16
31:24
FLST
FIDX (Filter Index)
Reserved
R
R
R
1094
HPMS
Reserved
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表8-25. CAN FD Register Set Description (continued)
Offset
Name
Bit Pos.
7:0
MSB
LSB
ND0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RP
RP
RP
RP
R
ND7
ND6
ND5
ND4
ND3
ND2
ND1
ND9
15:8
23:16
31:24
7:0
ND15
ND23
ND31
ND39
ND47
ND55
ND63
ND14
ND22
ND30
ND38
ND46
ND54
ND62
ND13
ND21
ND29
ND37
ND45
ND53
ND61
ND12
ND20
ND28
ND36
ND44
ND52
ND60
ND11
ND19
ND27
ND35
ND43
ND51
ND59
ND10
ND18
ND26
ND34
ND42
ND50
ND58
ND8
1098
NDAT1
ND17
ND25
ND33
ND41
ND49
ND57
ND16
ND24
ND32
ND40
ND48
ND56
15:8
23:16
31:24
7:0
109C
10A0
10A4
10A8
10AC
10B0
10B4
10B8
10BC
10C0
10C4
10C8
NDAT2
RXF0C
RXF0S
RXF0A
RXBC
F0SA[7:2] (RX FIFO 0 Start Address)
Reserved
15:8
23:16
31:24
7:0
F0SA[15:8] (RX FIFO 0 Start Address)
F0S (RX FIFO 0 Size)
Reserved
F0OM
F0WM (RX FIFO 0 Watermark)
Reserved
15:8
23:16
31:24
7:0
Reserved
R
Reserved
Reserved
R
Reserved
R
F0A (RX FIFO 0 Acknowledge Index)
R/W
R
15:8
23:16
31:24
7:0
Reserved
Reserved
Reserved
R
R
RBSA[7:2] (RX Buffer Configuration)
RBSA[15:8] (RX Buffer Configuration)
Reserved
Reserved
RP
RP
R
15:8
23:16
31:24
7:0
Reserved
Reserved
R
F1SA[7:2] (RX FIFO 1 Start Address)
RP
RP
RP
RP
R
15:8
23:16
31:24
7:0
F1SA[15:8] (RX FIFO 1 Start Address)
RXF1C
RXF1S
RXF1A
RXESC
TXBC
Reserved
F1S (RX FIFO 1 Size)
F1WM (RX FIFO 1 Watermark)
F1FL (RX FIFO 1 Fill Level)
F1GI (RX FIFO 1 Get Index)
F1PI (RX FIFO 1 Put Index)
Reserved
F1OM
Reserved
15:8
23:16
31:24
7:0
Reserved
Reserved
R
R
DMS (Data Message Status)
Reserved
RF1L
F1F
R
F1AI (RX FIFO 1 Acknowledge Index)
Reserved
R/W
R
15:8
23:16
31:24
7:0
Reserved
R
Reserved
R
Reserved
F1DS (RX FIFO 1 Data Field Size)
Reserved
Reserved
F0DS (RX FIFO 0 Data Field Size)
RBDS (RX Buffer Data Field Size)
RP
RP
R
15:8
23:16
31:24
7:0
Reserved
Reserved
TBSA[7:2] (TX Buffer Start Address)
TBSA[15:8] (TX Buffer Start Address)
NDTB (Number of Dedicated Transmit Buffers)
R
Reserved
RP
RP
RP
RP
R
15:8
23:16
31:24
7:0
Reserved
Reserved TFQM
Reserved
Reserved
Reserved
TFQS (Transmit FIFO/Queue Size)
TFFL (TX FIFO Free Level)
15:8
23:16
31:24
7:0
TFGI (TX FIFO Get Index)
R
TXQFS
TXESC
TFQF
TFQP (TX FIFO/Queue Put Index)
R
Reserved
R
Reserved
TBDS (TX Buffer Data Field Size)
RP
R
15:8
23:16
31:24
Reserved
Reserved
Reserved
R
R
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表8-25. CAN FD Register Set Description (continued)
Offset
Name
Bit Pos.
7:0
MSB
TRP7
TRP15
TRP23
TRP31
AR7
LSB
TRP0
TRP8
TRP16
TRP24
AR0
Access
R
TRP6
TRP14
TRP22
TRP30
AR6
TRP5
TRP13
TRP21
TRP29
AR5
TRP4
TRP12
TRP20
TRP28
AR4
TRP3
TRP11
TRP19
TRP27
AR3
TRP2
TRP10
TRP18
TRP26
AR2
TRP1
TRP9
TRP17
TRP25
AR1
15:8
23:16
31:24
7:0
R
10CC
TXBRP
R
R
R/W
R/W
R/W
R/W
RW
RW
RW
RW
R
15:8
23:16
31:24
7:0
AR15
AR23
AR31
CR7
AR14
AR22
AR30
CR6
AR13
AR21
AR29
CR5
AR12
AR20
AR28
CR4
AR11
AR19
AR27
CR3
AR10
AR18
AR26
CR2
AR9
AR8
10D0
10D4
10D8
10DC
TXBAR
TXBCR
TXBTO
TXBCF
AR17
AR25
CR1
AR16
AR24
CR0
15:8
23:16
31:24
7:0
CR15
CR23
CR31
TO7
CR14
CR22
CR30
TO6
CR13
CR21
CR29
TO5
CR12
CR20
CR28
TO4
CR11
CR19
CR27
TO3
CR10
CR18
CR26
TO2
CR9
CR8
CR17
CR25
TO1
CR16
CR24
TO0
15:8
23:16
31:24
7:0
TO15
TO23
TO31
CF7
TO14
TO22
TO30
CF6
TO13
TO21
TO29
CF5
TO12
TO20
TO28
CF4
TO11
TO19
TO27
CF3
TO10
TO18
TO26
CF2
TO9
TO8
R
TO17
TO25
CF1
TO16
TO24
CF0
R
R
R
15:8
23:16
31:24
7:0
CF15
CF23
CF31
TIE7
CF14
CF22
CF30
TIE6
CF13
CF21
CF29
TIE5
CF12
CF20
CF28
TIE4
CF11
CF19
CF27
TIE3
CF10
CF18
CF26
TIE2
CF9
CF8
R
CF17
CF25
TIE1
CF16
CF24
TIE0
R
R
RW
RW
RW
RW
RW
RW
RW
RW
R
15:8
23:16
31:24
7:0
TIE15
TIE23
TIE31
CFIE7
CFIE15
CFIE23
CFIE31
TIE14
TIE22
TIE30
CFIE6
CFIE14
CFIE22
CFIE30
TIE13
TIE21
TIE29
CFIE5
CFIE13
CFIE21
CFIE29
TIE12
TIE20
TIE28
CFIE4
CFIE12
CFIE20
CFIE28
TIE11
TIE19
TIE27
CFIE3
CFIE11
CFIE19
CFIE27
TIE10
TIE18
TIE26
CFIE2
CFIE10
CFIE18
CFIE26
TIE9
TIE8
10E0
TXBTIE
TIE17
TIE25
CFIE1
CFIE9
CFIE17
CFIE25
TIE16
TIE24
CFIE0
CFIE8
CFIE16
CFIE24
15:8
23:16
31:24
31:0
7:0
10E4
10E8 - 10EC
10F0
TXBCIE
RSVD
Reserved
EFSA[7:2] (Event FIFO Start Address)
EFSA[15:8] (Event FIFO Start Address)
Reserved
RP
RP
RP
RP
15:8
23:16
31:24
7:0
TXEFC
Reserved
EFS (Event FIFO Size)
EFWM (Event FIFO Watermark)
EFFL (Event FIFO Fill Level)
Reserved
Reserved
15:8
23:16
31:24
7:0
Reserved
EFGI (Event FIFO Get Index)
EFPI (Event FIFO Put Index)
10F4
TXEFS
Reserved
Reserved
Reserved
TEFL
EFA (Event FIFO Acknowledge Index)
EFF
R
RW
R
15:8
23:16
31:24
31:0
Reserved
Reserved
Reserved
Reserved
10F8
10FC
TXEFA
RSVD
R
R
R
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8.6.4.1 Core Release Register (address = h1000) [reset = hrrrddddd]
图8-31. Core Release Register
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
REL[3:0]
R
STEP[3:0]
R
SUBSTEP[3:0]
R
YEAR[3:0]
R
MONTH[7:0]
R
1
0
DAY[7:0]
R
表8-26. Core Release Register Field Descriptions
Bit
Field
Type
Reset
Description
31:28
27:24
23:20
19:16
15:8
REL[3:0]
STEP[3:0]
R
r
one digit, BCD-coded
one digit, BCD-coded
one digit, BCD-coded
one digit, BCD-coded
two digit, BCD-coded
two digit, BCD-coded
R
r
SUBSTEP[3:0]
YEAR[3:0]
R
r
R
d
d
d
MONTH[7:0]
DAY[7:0]
R
7:0
R
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8.6.4.2 Endian Register (address = h1004) [reset = h87654321]
图8-32. Endian Register
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
ETV[31:24]
R
ETV[23:16]
R
ETV[15:8]
R
1
0
ETV[7:0]
R
表8-27. Endian Register Field Descriptions
Bit
Field
Type
Reset
0x87
0x65
0x43
0x21
Description
31:24
23:16
15:8
7:0
ETV[31:24]
ETV[23:16]
ETV[15:8]
ETV[7:0]
R
Endianness Test Value
Endianness Test Value
Endianness Test Value
Endianness Test Value
R
R
R
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8.6.4.3 Customer Register (address = h1008) [reset = h00000000]
图8-33. Customer Register
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
RSVD
R
RSVD
R
RSVD
R
1
0
RSVD
R
表8-28. Customer Register Field Descriptions
Bit
31:0
Field
Type
Reset
Description
RSVD
R
h00000000 Reserved
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8.6.4.4 Data Bit Timing & Prescaler (address = h100C) [reset = h0000A33]
图8-34. Data Bit Timing & Prescaler
31
30
22
29
21
13
5
28
20
12
4
27
19
11
3
26
25
17
9
24
16
8
RSVD
R
23
TDC
n
18
RSVD
R
DBRP[4:0]
RP
15
14
RSVD
R
10
DTSEG1[4:0]
RP
2
7
6
1
0
DTSEG2[3:0]
RP
DSJW[3:0]
RP
表8-29. Data Bit Timing & Prescaler Field Descriptions
Bit
Field
Type
Reset
Description
31:24
RSVD
R
0x0
Reserved
Transmitter Delay Compensation
0 –TDC Disabled
23
TDC
RP
0x0
1 –TDC Enabled
22:21
20:16
15:13
12:8
7:4
RSVD
R
0x0
0x0
0x0
0xA
0x3
0x3
Reserved
DBRP[4:0]
RSVD
RP
R
Data Bit Rate Prescaler
Reserved
DTSEG1[4:0]
DTSEG2[3:0]
DSJW[3:0]
RP
RP
RP
Data time Segment before sample point
Data time Segment before sample point
Data (Re)Synchronization Jump Width
3:0
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8.6.4.5 Test Register (address = h1010 ) [reset = h00000000]
图8-35. Test Register
31
23
15
30
22
14
6
29
21
13
5
28
20
12
27
19
11
3
26
18
10
2
25
17
9
24
16
8
RSVD
R
RSVD
R
RSVD
R
7
RX
R
4
1
0
TX[1:0]
RP
LBCK
RP
RSVD
R
表8-30. Test Register Field Descriptions
Bit
Field
Type
Reset
Description
Reserved
Reserved
Reserved
31:24
23:16
15:8
RSVD
RSVD
RSVD
R
0x0
R
0x0
R
0x0
Receive Pin (m_can_rx)
7
RX
R
U
0 –CAN Bus is Dominant
1 –CAN Bus is Recessive
Control of Transmit Pin (m_can_tx)
00 –Reset Value, updated at the end of the CAN bit time
01 –Sample Point can be monitored at PIN m_can_tx
10 –Dominant (‘0’) level at pin
6:5
TX[1:0]
RP
0x0
11 –Recessive (‘1’) level at pin
LBCK: Loop Back Mode
4
LBCK
RSVD
RP
R
0
0 –Reset Value, Loop Back Mode is Disabled
1 –Loop Back Mode is Enabled
3:0
0x0
Reserved
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8.6.4.6 RAM Watchdog (address = h1014) [reset = h00000000]
图8-36. RAM Watchdog
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
RSVD
R
RSVD
R
WDV[7:0]
R
1
0
WDC[7:0]
RP
表8-31. RAM Watchdog Field Descriptions
Bit
Field
Type
Reset
Description
31:24
23:16
15:8
7:0
RSVD
R
0x0
Reserved
RSVD
R
0x0
Reserved
WDV[7:0]
WDC[7:0]
R
0x0
Watchdog Counter Value
Watchdog Configuration
RP
0x0
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8.6.4.7 Control Register (address = h1018) [reset = 0000 0019]
图8-37. Control Register
31
23
30
22
29
21
28
27
19
11
26
18
10
25
17
24
16
RSVD
R
20
RSVD
R
15
NISO
RP
14
TXP
RP
6
13
EFBI
RP
12
PXHD
RP
9
BRSE
RP
8
FDOE
RP
RSVD
R
7
5
4
3
CSA
R
2
1
0
TEST
Rp
DAR
RP
MON
Rp
CSR
R/W
ASM
Rp
CCE
RP
INIT
R/W
表8-32. Control Register Field Descriptions
Bit
Field
Type
Reset
Description
31:24
23:16
RSVD
RSVD
R
0x0
Reserved
R
0x0
Reserved
Non-ISO Operation
0 –CAN FD Frame format according to ISO 11898-1:2015
1 –CAN FD Frame format according to Bosch CAN FD
Specification V1.0
15
14
13
NISO
TXP
RP
RP
RP
0
0
0
Transmitter Pause
0 –Transmitter Pause Disabled
1 –Transmitter Pause Enabled
Edge Filtering during Bus Integration
0 –Edge Filtering Disabled
1 –Two Consecutive Dominant tq required to detect an edge
for hard synchronization
EFBI
Protocol Exception Handling Disable
12
11:10
9
PXHD
RSVD
BRSE
RP
R
0
0 –Protocol Exception Handling Enabled
1 –Protocol Exception Handling Disabled
0x0
0
Reserved
Bit Rate Switch Enable
0 –Bit Rate Switching for Transmission Disabled
1 –Bit Rate Switching for Transmission Enabled
RP
FD Operation Enable
8
7
FDOE
TEST
RP
Rp
0
0
0 –FD Operation Disabled
1 –FD Operation Enabled
Test Mode Enable
0 –Normal Mode of Operation, Register TEST Holds Reset
Value
1 –Test Mode, Write Access to Register TEST Enabled
Disable Automatic Retransmission
0 –Automatic Retransmission of Messages not Transmitted
Successfully Enabled
1 –Automatic Retransmission Disabled
6
5
DAR
RP
Rp
0
0
Bus Monitoring Mode is Disabled
0 –Bus Monitoring Mode is Disabled
1 –Bus Monitoring Mode is Enabled
MON
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表8-32. Control Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
Clock Stop Request
0 –No clock Stop is requested
1 –Clock Stop Requested. When requested first INIT and then
CSA will be set after all pending transfer request have
completed and the CAN bus reached idle
See NOTE section
4
CSR
R/W
1
Clock Stop Acknowledge
0 –No Clock Stop Requested
1 –m_can may be set in power down by stopping m_can-hclk
and m_can_cclk
3
2
CSA
ASM
R
1
0
Restricted Operation Mode
0 –Normal CAN Operation
Rp
1 –Restricted Operation Mode Active
Configuration Change Enable
0 –CPU has no write access to the protected configuration
registers
1 –CPU has write access to the protected configuration
registers (While CCCR.INIT =1)
1
0
CCE
INIT
RP
0
1
Initialization
0 –Normal Operation
1 –Initialization has started
R/W
备注
The TCAN4550-Q1 handles stop request through hardware. The means that a 1 should not be written
to CCCR.CSR (Clock Stop Request) as this will interfere with normal operation. If a Read-Modify-
Write operation is performed in Standby mode a CSR = 1 will be read back but a 0 should be written
to it.
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8.6.4.8 Nominal Bit Timing & Prescaler Register (address = h101C) [reset = h06000A03]
图8-38. Nominal Bit Timing & Prescaler Register
31
23
15
30
22
14
6
29
21
13
5
28
NSJW[6:0]
RP
27
19
11
3
26
18
10
2
25
17
9
24
NBRP[8]
RP
20
16
NBRP[7:0]
RP
12
4
8
0
NTSEG1[7:0]
RP
7
RSVD
R
1
NTSEG2[6:0]
RP
表8-33. Nominal Bit Timing & Prescaler Register Field Descriptions
Bit
Field
Type
Reset
Description
Nominal (RE)Synchronization Jump Width
0x00 - 0x7F –Valid values are 0 to 127 - The actual
interpretation by the hardware of this value is such that one
more than the value programmed here is used.
31:25
24:16
NSJW[6:0]
RP
0x3
Nominal Bit Rate Prescaler
0x000 - 0x1FF –Value by which the oscillator frequency is
divided for generating the bit time quanta. Valid values are 0 to
511. - The actual interpretation by the hardware of this value is
such that one more than the value programmed here is used.
NBRP[8:0]
RP
0x0
Nominal Time Segment Before Sample Point)
0x01-0xFF –Valid values are 1 to 255 - The actual
interpretation by the hardware of this value is such that one
more than the value programmed here is used.
15:8
7
NTSEG1[7:0]
RSVD
RP
R
0xA
0
Reserved
Nominal Time Segment After Sample Point
0x01-0x7F –Valid values are 1 to 127 - The actual
interpretation by the hardware of this value is such that one
more than the value programmed here is used.
6:0
NTSEG2[6:0]
RP
0x3
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8.6.4.9 Timestamp Counter Configuration (address = h1020) [reset = h00000000]
图8-39. Timestamp Counter Configuration
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
RSVD
R
RSVD
R
TCP[3:0]
RP
RSVD
R
1
0
RSVD
R
TSS[1:0]
RP
表8-34. Timestamp Counter Configuration Descriptions
Bit
Field
Type
Reset
Description
31:24
23:20
RSVD
RSVD
R
0x0
Reserved
R
0x0
Reserved
Timestamp Counter Prescaler
19:16
TCP[3:0]
RP
0x0
0x0 - 0xF –Configures timestamp and timeout counters time
unit in multiples of CAN bit times [1…16]
15:8
7:2
RSVD
RSVD
R
R
0x0
0x0
Reserved
Reserved
Timestamp Select
00 –Timestamp counter value always 0x0000
01 –Timestamp counter value incremented according to TCP
10 –External timestamp counter value used
11 –Same as "00"
1:0
TSS[1:0]
RP
0x0
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8.6.4.10 Timestamp Counter Value (address = h1024) [reset = h00000000]
图8-40. Timestamp Counter Value
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
RSVD
R
RSVD
R
TSC[15:8]
RC
1
0
TSC[7:0]
RC
表8-35. Timestamp Counter Value Field Descriptions
Bit
Field
Type
Reset
Description
31:24
23:20
15:8
RSVD
RSVD
R
0x0
Reserved
R
0x0
Reserved
Timestamp Counter
The internal/external Timestamp Counter value is captured on
start of frame (both Rx and Tx). When TSCC.TSS = “01”, the
Timestamp Counter is incremented in multiples of CAN bit times
[1…16] depending on the configuration of TSCC.TCP. A wrap
around sets interrupt flag IR.TSW. Write access resets the
counter to zero. When TSCC.TSS = “10”, TSC reflects the
external
TSC[7:0]
RC
0x0
Timestamp Counter value. A write access has no impact.
7:0
Timestamp Counter
The internal/external Timestamp Counter value is captured on
start of frame (both Rx and Tx). When TSCC.TSS = “01”, the
Timestamp Counter is incremented in multiples of CAN bit times
[1…16] depending on the configuration of TSCC.TCP. A wrap
around sets interrupt flag IR.TSW. Write access resets the
counter to zero. When TSCC.TSS = “10”, TSC reflects the
external
TSC[7:0]
RC
0x0
Timestamp Counter value. A write access has no impact.
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8.6.4.11 Timeout Counter Configuration (address = h1028) [reset = hFFFF0000]
图8-41. Timeout Counter Configuration
31
23
15
7
30
22
14
6
29
21
13
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
TOP[15:8]
R
TOP[7:0]
R
RSVD
R
5
RSVD
R
1
0
TOS[1:0]
RP
ETOC
RP
表8-36. Timeout Counter Configuration Field Descriptions
Bit
Field
Type
Reset
Description
Timeout Period
31:24
23:16
TOP[15:8]
RP
0xFF
Start value of the timeout counter (down-counter). Configures
the timeout period
Timeout Period
TOP[7:0]
RP
0xFF
Start value of the timeout counter (down-counter). Configures
the timeout period
15:8
7:3
RSVD
RSVD
R
R
0x0
0x0
Reserved
Reserved
Timeout Select
When operating in Continuous mode, a write to TOCV presets
the counter to the value configured by TOCC.TOP and
continues down-counting. When the Timeout Counter is
controlled by one of the FIFOs, an empty FIFO presets the
counter to the value configured by TOCC.TOP. Down-counting is
started when the first FIFO element is stored
00 –Continuous Operation
01 –Timeout controlled by TX Event FIFO
10 –Timeout controlled by Rx FIFO 0
11 –Timeout controlled by Rx FIFO 1
2:1
TOS[1:0]
RP
RP
0x0
Enable Timeout Counter
0 –Timeout counter disabled
1 –Timeout counter enabled
0
ETOC
0
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8.6.4.12 Timeout Counter Value (address = h102C) [reset = h0000FFFF]
图8-42. Timeout Counter Value
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
RSVD
R
RSVD
R
TOC[15:8]
RC
1
0
TOC[7:0]
RC
表8-37. Timeout Counter Value Field Descriptions
Bit
Field
Type
Reset
Description
31:24
23:16
RSVD
RSVD
R
0x0
Reserved
R
0x0
Reserved
Timeout Counter
The Timeout Counter is decremented in multiples of CAN bit
times [1…16] depending on the configuration of TSCC.TCP.
When decremented to zero, interrupt flag IR.TOO is set and the
Timeout Counter is stopped. Start and reset/restart conditions
are configured via TOCC.TOS
15:8
7:0
TOC[15:8]
TOC[7:0]
RC
RC
0xFF
0xFF
Timeout Counter
The Timeout Counter is decremented in multiples of CAN bit
times [1…16] depending on the configuration of TSCC.TCP.
When decremented to zero, interrupt flag IR.TOO is set and the
Timeout Counter is stopped. Start and reset/restart conditions
are configured via TOCC.TOS
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8.6.4.13 Reserved (address = h1030 - h103C) [reset = h00000000]
图8-43. Reserved
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
RSVD
R
RSVD
R
RSVD
R
1
0
RSVD
R
表8-38. Reserved Field Descriptions
Bit
31:0
Field
Type
Reset
Description
RSVD
R
0
Reserved
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8.6.4.14 Error Counter Register (address = h1040) [reset = h00000000]
图8-44. Error Counter Register
31
23
30
22
14
6
29
21
13
5
28
20
12
4
27
26
18
10
2
25
17
9
24
16
8
RSVD
R
19
CEL[7:0]
X
15
RP
R
11
REC[6:0]
R
3
7
1
0
TEC[7:0]
R
表8-39. Error Counter Register Field Descriptions
Bit
Field
Type
Reset
Description
31:24
RSVD
R
0x0
Reserved
CAN Error Logging
The counter is incremented each time when a CAN protocol
error causes the Transmit Error Counter or the Receive Error
Counter to be incremented. It is reset by read access to CEL.
The counter stops at 0xFF; the next increment of TEC or REC
sets interrupt flag IR.ELO
23:16
CEL[7:0]
X
R
0x0
0 –The Receive Error Counter is below the error passive level
of 128
1 –The Receive Error Counter has reached the error passive
15
RP
0
level of 128
Actual state of the Receive Error Counter, values between 0 and
127
14:8
7:0
REC[6:0]
TEC[7:0]
R
R
0x0
0x0
Actual state of the Transmit Error Counter, values between 0
and 255
备注
When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN
protocol error is detected, but CEL is still incremented.
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8.6.4.15 Protocol Status Register (address = h1044) [reset = h00000707]
图8-45. Protocol Status Register
31
30
22
29
21
28
27
26
18
10
2
25
17
24
16
8
RSVD
R
23
RSVD
R
20
19
TDCV[6:0]
R
11
15
14
PXE
X
13
RFDF
X
12
RBRS
X
9
RSVD
R
RESI
X
DLEC[2:0]
S
7
6
5
4
3
1
LEC[2:0]
S
0
BO
R
EW
R
EP
R
ACT[1:0]
R
表8-40. Protocol Status Register Field Descriptions
Bit
Field
Type
Reset
Description
Reserved
Reserved
31:24
23
RSVD
RSVD
R
0x0
R
0x0
Transmitter Delay Compensation Value
0x00-0x7F –Position of the secondary sample point, defined
by the sum of the measured delay from m_can_tx to m_can_rx
and TDCR.TDCO. The SSP position is, in the data phase, the
number of mtq between the start of the transmitted bit and the
secondary sample point. Valid values are 0 to 127 mtq.
22:16
TDCV[6:0]
R
0x0
15
14
RSVD
PXE
R
X
0
0
Reserved
Protocol Exception Event
0 –No protocol exception event occurred since last read
access
1 –Protocol exception event occurred
Received a CAN FD Message
This bit is set independent of acceptance filtering
0 –Since this bit was reset by the CPU, no CAN FD message
has been received
1 –Message in CAN FD format with FDF flag set has been
received
13
12
RFDF
X
X
X
X
0
BRS flag of last received CAN FD Message
This bit is set together with RFDF, independent of acceptance
filtering.
0 –Last received CAN FD message did not have its BRS flag
set
RBRS
0
1 –Last received CAN FD message had its BRS flag set
ESI flag of last received CAN FD Message
This bit is set together with RFDF, independent of acceptance
filtering.
0 –Last received CAN FD message did not have its ESI flag
set
11
RESI
0
1 –Last received CAN FD message had its ESI flag set
Data Phase Last Error Code
Type of last error that occurred in the data phase of a CAN FD
format frame with its BRS flag set. Coding is the same as for
LEC. This field will be cleared to zero when a CAN FD format
frame with its BRS flag set has been transferred (reception or
transmission) without error.
10:8
DLEC[2:0]
0x7
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表8-40. Protocol Status Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
Bus_Off Status
7
BO
R
0
0 –The M_CAN is not Bus_Off
1 –The M_CAN is in Bus_Off state
Warning Status
0 –Both error counters are below the Error_Warning limit of 96
1 –At least one of error counter has reached the
Error_Warning limit of 96
6
5
EW
EP
R
R
0
0
Error Passive
0 –The M_CAN is in the Error_Active state. It normally takes
part in bus communication and sends an active error flag when
an error has been detected
1 –The M_CAN is in the Error_Passive state
Activity
Monitors the module’s CAN communication state.
00 –Synchronizing - node is synchronizing on CAN
communication
4:3
ACT[1:0]
R
0x0
01 –Idle - node is neither receiver nor transmitter
10 –Receiver - node is operating as receiver
11 –Transmitter - node is operating as transmitter
Last Error Code
The LEC indicates the type of the last error to occur on the CAN
bus. This field will be cleared to ‘0’when a message has
been transferred (reception or transmission) without error.
0 –No Error: No error occurred since LEC has been reset by
successful reception or transmission
1 –Stuff Error: More than 5 equal bits in a sequence have
occurred in a part of a received message where this is not
allowed.
2 –Form Error: A fixed format part of a received frame has the
wrong format.
3 –AckError: The message transmitted by the M_CAN was not
acknowledged by another node.
4 –Bit1Error: During the transmission of a message (with the
exception of the arbitration field), the device wanted to send a
recessive level (bit of logical value ‘1’), but the monitored bus
value was dominant.
2:0
LEC[2:0]
S
0x7
5 –Bit0Error: During the transmission of a message (or
acknowledge bit, or active error flag, or overload flag), the
device wanted to send a dominant level (data or identifier bit
logical value ‘0’), but the monitored bus value was recessive.
During Bus_Off recovery this status is set each time a sequence
of 11 recessive bits has been monitored. This enables the CPU
to monitor the proceeding of the Bus_Off recovery sequence
(indicating the bus is not stuck at dominant or continuously
disturbed).
6 –CRCError: The CRC check sum of a received message
was incorrect. The CRC of an incoming message does not
match with the CRC calculated from the received data.
7 –NoChange: Any read access to the Protocol Status
Register re-initializes the LEC to ‘7’. When the LEC shows
the value ‘7’, no CAN bus event was detected since the last
CPU read access to the Protocol Status Register.
备注
When a frame in CAN FD format has reached the data phase with BRS flag set, the next CAN event
(error or valid frame) will be shown in DLEC instead of LEC. An error in a fixed stuff bit of a CAN FD
CRC sequence will be shown as a Form Error, not Stuff Error
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备注
The Bus_Off recovery sequence (see ISO 11898-1:2015) cannot be shortened by setting or resetting
CCCR.INIT. If the device goes Bus_Off, it will set CCCR.INIT of its own accord, stopping all bus
activities. Once CCCR.INIT has been cleared by the CPU, the device will then wait for 129
occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming normal operation. At
the end of the Bus_Off recovery sequence, the Error Management Counters will be reset. During the
waiting time after the resetting of CCCR.INIT, each time a sequence of 11 recessive bits has been
monitored, a Bit0Error code is written to PSR.LEC, enabling the CPU to readily checkup whether the
CAN bus is stuck at dominant or continuously disturbed and to monitor the Bus_Off recovery
sequence. ECR.REC is used to count these sequences.
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8.6.4.16 Transmitter Delay Compensation Register (address = h1048) [reset = h00000000]
图8-46. Transmitter Delay Compensation Register
31
23
30
22
14
6
29
21
13
5
28
20
12
4
27
26
18
10
2
25
17
9
24
16
8
RSVD
R
19
RSVD
R
15
RSVD
R
11
TDCO[6:0]
RP
7
3
1
0
RSVD
R
TDCF[6:0]
RP
表8-41. Transmitter Delay Compensation Register Field Descriptions
Bit
Field
Type
Reset
0x0
0x0
0
Description
31:24
23:16
15
RSVD
RSVD
RSVD
R
Reserved
R
Reserved
R
Reserved
Transmitter Delay Compensation Offset
0x00-0x7F - Offset value defining the distance between the
measured delay from m_can_tx to m_can_rx and the secondary
sample point. Valid values are 0 to 127 mtq.
14:8
7
TDCO[6:0]
RSVD
RP
R
0x0
0
Reserved
Transmitter Delay Compensation Filter Window Length
0x00-0x7F - Defines the minimum value of the SSP position,
dominant edges on m_can_rx that would result in an earlier SSP
position are ignored for transmitter delay measurement. The
feature is enabled when TDCF is configured to a value greater
than TDCO. Valid values are 0 to 127 mtq.
6:0
TDCF[6:0]
RP
0x0
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8.6.4.17 Reserved (address = h104C) [reset = h00000000]
图8-47. Reserved
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
RSVD
R
RSVD
R
RSVD
R
1
0
RSVD
R
表8-42. Reserved Field Descriptions
Bit
31:0
Field
Type
Reset
Description
RSVD
R
0
Reserved
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8.6.4.18 Interrupt Register (address = h1050) [reset = h00000000]
图8-48. Interrupt Register
31
30
29
ARA
R/W
21
28
PED
R/W
20
27
PEA
R/W
19
26
WDI
R/W
18
25
BO
24
EW
R/W
16
RSVD
R
R/W
17
23
EP
22
ELO
R/W
14
BEU
R/W
13
BEC
R/W
12
DRX
R/W
11
TOO
R/W
10
MRF
R/W
9
TSW
R/W
8
R/W
15
TEFL
R/W
7
TEFF
R/W
6
TEFW
R/W
5
TEFN
R/W
4
TFE
R/W
3
TCF
R/W
2
TC
HPM
R/W
0
R/W
1
RF1L
R/W
RF1F
R/W
RF1W
R/W
RF1N
R/W
RF0L
R/W
RF0F
R/W
RF0W
R/W
RF0N
R/W
表8-43. Interrupt Register Field Descriptions
Bit
Field
Type
Reset
Description
31:30
RSVD
R
0x0
Reserved
Access to Reserved Address
29
ARA
R/W
R/W
0
0
0 –No access to reserved address occurred
1 –Access to reserved address occurred
Protocol Error in Data Phase (Data Bit Time is used)
0 –No protocol error in data phase
1 –Protocol error in data phase detected (PSR.DLEC ≠0,7)
28
27
PED
PEA
Protocol Error in Arbitration Phase (Nominal Bit Time is used)
0 –No protocol error in arbitration phase
1 –Protocol error in arbitration phase detected (PSR.LEC ≠
0,7)
R/W
0
Watchdog Interrupt
26
25
24
23
22
WDI
BO
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0 –No Message RAM Watchdog event occurred
1 –Message RAM Watchdog event due to missing READY
Bus_Off Status
0 –Bus_Off status unchanged
1 –Bus_Off status changed
Warning Status
0 –Error_Warning status unchanged
1 –Error_Warning status changed
EW
EP
Error Passive
0 –Error_Passive status unchanged
1 –Error_Passive status changed
ELO: Error Logging Overflow
0 –CAN Error Logging Counter did not overflow
1 –Overflow of CAN Error Logging Counter occurred
ELO
Bit Error Uncorrected
Message RAM bit error detected, uncorrected. Controlled by
input signal m_can_aeim_berr[1] generated by an optional
external parity / ECC logic attached to the Message RAM. An
uncorrected Message RAM bit error sets CCCR.INIT to ‘1’.
This is done to avoid transmission of corrupted data.
0 –No bit error detected when reading from Message RAM
1 –Bit error detected, uncorrected (e.g. parity logic)
21
BEU
R/W
0
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表8-43. Interrupt Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
Bit Error Corrected
Message RAM bit error detected and corrected. Controlled by
input signal m_can_aeim_berr[0] generated by an optional
external parity / ECC logic attached to the Message RAM.
0 –No bit error detected when reading from Message RAM
1 –Bit error detected and corrected (e.g. ECC)
20
BEC
R/W
0
Message stored to Dedicated Rx Buffer
The flag is set whenever a received message has been stored
into a dedicated Rx Buffer.
0 –No Rx Buffer updated
1 –At least one received message stored into an Rx Buffer
19
18
DRX
TOO
R/W
R/W
0
0
Timeout Occurred
0 –No timeout
1 –Timeout reached
Message RAM Access Failure
The flag is set, when the Rx Handler
•
has not completed acceptance filtering or storage of an
accepted message until the arbitration field of the following
message has been received. In this case acceptance
filtering or message storage is aborted and the Rx Handler
start processing of the following message
•
was not able to write a message to the Message RAM. In
this case message storage is aborted.
17
MRF
R/W
0
In both cases the FIFO put index is not updated resp. the New
Data flag for a dedicated Rx Buffer is not set, a partly stored
message is overwritten when the next message is stored to this
location. The flag is also set when the Tx Handler was not able
to read a message from the Message RAM in time. In this case
message transmission is aborted. In case of a Tx Handler
access failure the M_CAN is switched into Restricted Operation
Mode. To leave restricted Operation Mode, the Host CPU has to
reset CCCR.ASM.
0 –No Message RAM access failure occurred
1 –Message RAM access failure occurred
Timestamp Wraparound
16
15
TSW
R/W
R/W
0
0
0 –No timestamp counter wrap-around
1 –Timestamp counter wrapped around
Tx Event FIFO Element Lost
0 –No Tx Event FIFO element lost
1 –Tx Event FIFO element lost, also set after write attempt to
Tx Event FIFO of size zero
TEFL
Tx Event FIFO Full
14
13
12
11
10
TEFF
TEFW
TEFN
TFE
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0 –Tx Event FIFO not full
1 –Tx Event FIFO full
Tx Event FIFO Watermark Reached
0 –Tx Event FIFO fill level below watermark
1 –Tx Event FIFO fill level reached watermark
Tx Event FIFO New Entry
0 –Tx Event FIFO unchanged
1 –Tx Handler wrote Tx Event FIFO element
Tx FIFO Empty
0 –Tx FIFO non-empty
1 –Tx FIFO empty
Transmission Cancellation Finished
0 –No transmission cancellation finished
1 –Transmission cancellation finished
TCF
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表8-43. Interrupt Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
Transmission Cancellation Finished
0 –No transmission completed
1 –Transmission completed
9
TC
R/W
0
High Priority Message
8
7
HPM
R/W
R/W
0
0
0 –No high priority message received
1 –High priority message received
Rx FIFO 1 Message Lost
0 –No Rx FIFO 1 message lost
1 –Rx FIFO 1 message lost, also set after write attempt to Rx
RF1L
FIFO 1 of size zero
Rx FIFO 1 Full
6
5
4
RF1F
RF1W
RF1N
R/W
R/W
R/W
0
0
0
0 –Rx FIFO 1 not full
1 –Rx FIFO 1 full
Rx FIFO 1 Watermark Reached
0 –Rx FIFO 1 fill level below watermark
1 –Rx FIFO 1 fill level reached watermark
Rx FIFO 1 New Message
0 –No new message written to Rx FIFO
1 –New message written to Rx FIFO 1
Rx FIFO 0 Message Lost
0 –No Rx FIFO 0 message lost
1 –Rx FIFO 0 message lost, also set after write attempt to Rx
FIFO 0 of size zero
3
RF0L
R/W
0
Rx FIFO 0 Full
2
1
0
RF0F
RF0W
RF0N
R/W
R/W
R/W
0
0
0
0 –Rx FIFO 0 not full
1 –Rx FIFO 0 full
Rx FIFO 0 Watermark Reached
0 –Rx FIFO 0 fill level below watermark
1 –Rx FIFO 0 fill level reached watermark
Rx FIFO 0 New Message
0 –No new message written to Rx FIFO 0
1 –New message written to Rx FIFO 0
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8.6.4.19 Interrupt Enable (address = h1054) [reset = h00000000]
The settings in the Interrupt Enable register determine which status changes in the Interrupt Register will be
signaled on an interrupt line.
• 0 –Interrupt disabled
• 1 –Interrupt enabled
图8-49. Interrupt Enable Register
31
30
29
ARAE
R/W
21
28
PEDE
R/W
20
27
PEAE
R/W
19
26
WDIE
R/W
18
25
BOE
R/W
17
24
EWE
R/W
16
RSVD
R
23
EPE
R/W
15
22
ELOE
R/W
14
BEUE
R/W
13
BECE
R/W
12
DRXE
R/W
11
TOOE
R/W
10
MRAFE
R/W
9
TSWE
R/W
8
TEFLE
R/W
7
TEFFE
R/W
6
TEFW
R/W
5
TEFNE
R/W
4
TFEE
R/W
3
TCFE
R/W
2
TCE
R/W
1
HPME
R/W
0
RF1LE
R/W
RF1FE
R/W
RF1WE
R/W
RF1NE
R/W
RF0LE
R/W
RF0FE
R/W
RF0WE
R/W
RF0NE
R/W
表8-44. Interrupt Enable Field Descriptions
Bit
31:30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Field
Type
Reset
Description
RSVD
ARAE
PEDE
PEAE
WDIE
BOE
R
0x0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Access to Reserved Address Enable
Protocol Error in Data Phase Enable
Protocol Error in Arbitration Phase Enable
Watchdog Interrupt Enable
Bus_Off Status Interrupt Enable
Warning Status Interrupt Enable
Error Passive Interrupt Enable
EWE
EPE
ELOE
BEUE
BECE
DRXE
TOOE
MRAFE
TSWE
TEFLE
TEFFE
TEFW
TEFNE
TFEE
TCFE
TCE
Error Logging Overflow Interrupt Enable
Bit Error Uncorrected Interrupt Enable
Bit Error Corrected Interrupt Enable
Message stored to Dedicated Rx Buffer Interrupt Enable
Timeout Occurred Interrupt Enable
Message RAM Access Failure Interrupt Enable
Timestamp Wraparound Interrupt Enable
Tx Event FIFO Event Lost Interrupt Enable
Tx Event FIFO Full Interrupt Enable
Tx Event FIFO Watermark Reached Interrupt Enable
Tx Event FIFO New Entry Interrupt Enable
Tx FIFO Empty Interrupt Enable
Transmission Cancellation Finished Interrupt Enable
Transmission Completed Interrupt Enable
High Priority Message Interrupt Enable
Rx FIFO 1 Message Lost Interrupt Enable
Rx FIFO 1 Full Interrupt Enable
8
HPME
RF1LE
RF1FE
RF1WE
7
6
5
Rx FIFO 1 Watermark Reached Interrupt Enable
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表8-44. Interrupt Enable Field Descriptions (continued)
Bit
4
Field
Type
R/W
R/W
R/W
R/W
R/W
Reset
Description
RF1NE
RF0LE
RF0FE
RF0WE
RF0NE
0
0
0
0
0
Rx FIFO 1 New Message Interrupt Enable
Rx FIFO 0 Message Lost Interrupt Enable
Rx FIFO 0 Full Interrupt Enable
3
2
1
Rx FIFO 0 Watermark Reached Interrupt Enable
Rx FIFO 0 New Message Interrupt Enable
0
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8.6.4.20 Interrupt Line Select (address = h1058) [reset = h00000000]
The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt
Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be
enabled via ILE.EINT0 and ILE.EINT1.
• 0 –Interrupt assigned to interrupt line m_can_int0
• 1 –Interrupt assigned to interrupt line m_can_int1
图8-50. Interrupt Line Select Register
31
30
29
ARAL
R/W
21
28
PEDL
R/W
20
27
PEAL
R/W
19
26
WDIL
R/W
18
25
BOL
R/W
17
24
EWL
R/W
16
RSVD
R
23
EPL
R/W
15
22
ELOL
R/W
14
BEUL
R/W
13
BECL
R/W
12
DRXL
R/W
11
TOOL
R/W
10
MRAFL
R/W
9
TSWL
R/W
8
TEFLL
R/W
7
TEFFL
R/W
6
TEFWL
R/W
5
TEFNL
R/W
4
TFEL
R/W
3
TCFL
R/W
2
TCL
R/W
1
HPML
R/W
0
RF1LL
R/W
RF1FL
R/W
RF1WL
R/W
RF1NL
R/W
RF0LL
R/W
RF0FL
R/W
RF0WL
R/W
RF0NL
R/W
表8-45. Interrupt Line Select Field Descriptions
Bit
31:30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Field
Type
Reset
Description
RSVD
ARAL
PEDL
PEAL
WDIL
BOL
R
0x0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Access to Reserved Address Line
Protocol Error in Data Phase Line
Protocol Error in Arbitration Phase Line
Watchdog Interrupt Line
Bus_Off Status Interrupt Line
Warning Status Interrupt Line
Error Passive Interrupt Line
EWL
EPL
ELOL
BEUL
BECL
DRXL
TOOL
MRAFL
TSWL
TEFLL
TEFFL
TEFWL
TEFNL
TFEL
TCFL
TCL
Error Logging Overflow Interrupt Line
Bit Error Uncorrected Interrupt Line
Bit Error Corrected Interrupt Line
Message stored to Dedicated Rx Buffer Interrupt Line
Timeout Occurred Interrupt Line
Message RAM Access Failure Interrupt Line
Timestamp Wraparound Interrupt Line
Tx Event FIFO Event Lost Interrupt Line
Tx Event FIFO Full Interrupt Line
Tx Event FIFO Watermark Reached Interrupt Line
Tx Event FIFO New Entry Interrupt Line
Tx FIFO Empty Interrupt Line
Transmission Cancellation Finished Interrupt Line
Transmission Completed Interrupt Line
High Priority Message Interrupt Line
Rx FIFO 1 Message Lost Interrupt Line
Rx FIFO 1 Full Interrupt Line
8
HPML
RF1LL
RF1FL
7
6
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表8-45. Interrupt Line Select Field Descriptions (continued)
Bit
5
Field
Type
R/W
R/W
R/W
R/W
R/W
R/W
Reset
Description
RF1WL
RF1NL
RF0LL
RF0FL
RF0WL
RF0NL
0
0
0
0
0
0
Rx FIFO 1 Watermark Reached Interrupt Line
Rx FIFO 1 New Message Interrupt Line
Rx FIFO 0 Message Lost Interrupt Line
Rx FIFO 0 Full Interrupt Line
4
3
2
1
Rx FIFO 0 Watermark Reached Interrupt Line
Rx FIFO 0 New Message Interrupt Line
0
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8.6.4.21 Interrupt Line Enable (address = h105C) [reset = h00000000]
图8-51. Interrupt Line Enable Register
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
RSVD
R
RSVD
R
RSVD
R
1
0
RSVD
R
EINT1
R/W
EINT0
R/W
表8-46. Interrupt Line Enable Field Descriptions
Bit
Field
Type
Reset
Description
31:24
23:16
15:8
7:2
RSVD
RSVD
RSVD
RSVD
R
0x0
Reserved
R
0x0
Reserved
R
0x0
Reserved
R
0x0
Reserved
Enable Interrupt Line 1
1
0
EINT1
EINT0
R/W
R/w
0
0
0 - Interrupt line m_can_int1 disabled
1 - Interrupt line m_can_int1 enabled
Enable Interrupt Line 0
0 - Interrupt line m_can_int0 disabled
1 - Interrupt line m_can_int0 enabled
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8.6.4.22 Reserved (address = h1060 - h107C) [reset = h00000000]
图8-52. Reserved
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
RSVD
R
RSVD
R
RSVD
R
1
0
RSVD
R
表8-47. Reserved Field Descriptions
Bit
31:0
Field
Type
Reset
Description
RSVD
R
0
Reserved
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8.6.4.23 Global Filter Configuration (address = h1080) [reset = h00000000]
图8-53. Global Filter Configuration Register
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
RSVD
R
RSVD
R
RSVD
R
1
0
RSVD
R
ANFS[1:0]
RP
ANFE[1:0]
RP
RRFS
RP
RRFE
RP
表8-48. Global Filter Configuration Field Descriptions
Bit
Field
Type
Reset
Description
Reserved
Reserved
Reserved
Reserved
31:24
23:16
15:8
7:6
RSVD
RSVD
RSVD
RSVD
R
0x0
R
0x0
R
0x0
R
0x0
Accept Non-matching Frames Standard
Defines how received messages with 11-bit IDs that do not
match any element of the filter list are treated.
00 - Accept in Rx FIFO 0
01 - Accept in Rx FIFO 1
10 - Reject
5:4
3:2
ANFS[1:0]
ANFE[1:0]
RP
RP
0x0
0x0
11 - Reject
Accept Non-matching Frames Extended
Defines how received messages with 29-bit IDs that do not
match any element of the filter list are treated.
00 - Accept in Rx FIFO 0
01 - Accept in Rx FIFO 1
10 - Reject
11 - Reject
Reject Remote Frames Standard
1
0
RRFS
RRFE
RP
RP
0
0
0 - Filter remote frames with 11-bit standard IDs
1 - Reject all remote frames with 11-bit standard IDs
Reject Remote Frames Extended
0 - Filter remote frames with 29-bit extended IDs
1 - Reject all remote frames with 29-bit extended IDs
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8.6.4.24 Standard ID Filter Configuration (address = h1084) [reset = h00000000]
The MRAM and start address for this register, FLSSA, has special consideration.
• The start address must be word aligned (32-bit) in the MRAM. The 2 least significant bits are ignored on a
write to ensure this behavior.
• When entering the MRAM start address, the 0x8000 prefix is NOT necessary. For example, if the desired
start address is 0x8634, then bits SA[15:0] will be 0x0634.
图8-54. Standard ID Filter Configuration Register
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
RSVD
R
LSS[7:0]
RP
FLSSA[15:8]
RP
1
0
FLSSA[7:0]
RP
表8-49. Standard ID Filter Configuration Field Descriptions
Bit
Field
Type
Reset
Description
31:24
RSVD
R
0x0
Reserved
List Size Standard
0 - No standard Message ID filter
1-128 - Number of standard Message ID filter elements
>128 - Values greater than 128 are interpreted as 128
23:16
LSS[7:0]
RP
RP
0x0
0x0
Filter List Standard Start Address
Start address of standard Message ID filter list
15:0
FLSSA[15:0]
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8.6.4.25 Extended ID Filter Configuration (address = h1088) [reset = h00000000]
The MRAM and start address for this register, FLSEA, has special consideration.
• The start address must be word aligned (32-bit) in the MRAM. The 2 least significant bits are ignored on a
write to ensure this behavior.
• When entering the MRAM start address, the 0x8000 prefix is NOT necessary. For example, if the desired
start address is 0x8634, then bits SA[15:0] will be 0x0634.
图8-55. Extended ID Filter Configuration Register
31
30
22
14
6
29
21
13
5
28
20
12
4
27
26
18
10
2
25
17
9
24
16
8
RSVD
R
23
RSVD
R
19
LSE[6:0]
RP
15
11
FLSEA[15:8]
RP
7
3
1
0
FLSEA[7:0]
RP
表8-50. Extended ID Filter Configuration Field Descriptions
Bit
Field
Type
Reset
0x0
0
Description
Reserved
Reserved
31:24
23
RSVD
RSVD
R
R
List Size Extended
0 - No extended Message ID filter
1-64 - Number of extended Message ID filter elements
>64 - Values greater than 64 are interpreted as 64
22:16
15:0
LSE[6:0]
RP
RP
0x0
0x0
Filter List Extended Start Address
Start address of extended Message ID filter list
FLSEA[15:0]
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8.6.4.26 Reserved (address = h108C) [reset = h00000000]
图8-56. Reserved
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
RSVD
R
RSVD
R
RSVD
R
1
0
RSVD
R
表8-51. Reserved Field Descriptions
Bit
31:0
Field
Type
Reset
Description
RSVD
R
0
Reserved
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8.6.4.27 Extended ID AND Mask (address = h1090) [reset = h1FFFFFFF]
图8-57. Extended ID AND Mask Register
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
RSVD
R
EIDM[28:24]
RP
EIDM[23:16]
RP
EIDM[15:8]
RP
1
0
RP-0xFF
RP
表8-52. Extended ID AND Mask Field Descriptions
Bit
Field
RSVD
Type
Reset
Description
31:30
R
2'b00
Reserved
Extended ID Mask
For acceptance filtering of extended frames, the Extended ID
AND Mask is ANDed with the Message ID of a received frame.
Intended for masking of 29-bit IDs in SAE J1939. With the reset
value of all bits set to one, the mask is not active.
29:24
EIDM[28:24]
RP
RP
6'b011111
Extended ID Mask
For acceptance filtering of extended frames, the Extended ID
0xFFFFFF AND Mask is ANDed with the Message ID of a received frame.
Intended for masking of 29-bit IDs in SAE J1939. With the reset
value of all bits set to one, the mask is not active.
23:0
EIDM[23:16] to EIDM[7:0]
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8.6.4.28 High Priority Message Status (address = h1094) [reset = h00000000]
图8-58. High Priority Message Status Register
31
23
30
22
14
6
29
21
13
5
28
20
12
4
27
26
18
10
2
25
17
9
24
16
8
RSVD
R
19
RSVD
R
15
FLST
R
11
FIDX[6:0]
R
3
7
1
0
MSI[1:0]
R
BIDX[5:0]
R
表8-53. High Priority Message Status Field Descriptions
Bit
Field
Type
Reset
Description
Reserved
Reserved
Filter List
31:24
23:16
RSVD
RSVD
R
0x0
R
0x0
Indicates the filter list of the matching filter element.
0 - Standard Filter List
1 - Extended Filter List
15
FLST
R
R
0x0
0x0
Filter Index
14:8
FIDX[6:0]
Index of matching filter element.
Range is 0 to SIDFC.LSS - 1 resp. XIDFC.LSE - 1.
Message Storage Indicator
00 - No FIFO selected
7:6
5:0
MSI[1:0]
R
R
0x0
0x0
01 - FIFO message lost
10 - Message stored in FIFO 0
11 - Message stored in FIFO 1
Buffer Index
Index of Rx FIFO element to which the message was stored.
BIDX[5:0]
Only valid when MSI[1] = ‘1’
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8.6.4.29 New Data 1 (address = h1098) [reset = h00000000]
图8-59. New Data 1 Register
31
ND31
R/W
23
30
ND30
R/W
22
29
ND29
R/W
21
28
ND28
R/W
20
27
ND27
R/W
19
26
ND26
R/W
18
25
ND25
R/W
17
24
ND24
R/W
16
ND23
R/W
15
ND22
R/W
14
ND21
R/W
13
ND20
R/W
12
ND19
R/W
11
ND18
R/W
10
ND17
R/W
9
ND16
R/W
8
ND15
R/W
7
ND14
R/W
6
ND13
R/W
5
ND12
R/W
4
ND11
R/W
3
ND10
R/W
2
ND9
R/W
1
ND8
R/W
0
ND7
R/W
ND6
R/W
ND5
R/W
ND4
R/W
ND3
R/W
ND2
R/W
ND1
R/W
ND1
R/W
表8-54. New Data 1 Field Descriptions
Bit
Field
Type
Reset
Description
The register holds the New Data flags of Rx Buffers 0 to 31. The
flags are set when the respective Rx Buffer has been updated
from a received frame. The flags remain set until the Host clears
them. A flag is cleared by writing a ’1’to the corresponding
bit position. Writing a ’0’has no effect. A hard reset will clear
the register.
31:0
ND31 to ND0
R/W
0
0 - Rx Buffer not updated
1 - Rx Buffer updated from new message
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8.6.4.30 New Data 2 (address = h109C) [reset = h00000000]
图8-60. New Data 2 Register
31
ND63
R/W
23
30
ND62
R/W
22
29
ND61
R/W
21
28
ND60
R/W
20
27
ND59
R/W
19
26
ND58
R/W
18
25
ND57
R/W
17
24
ND56
R/W
16
ND55
R/W
15
ND54
R/W
14
ND53
R/W
13
ND52
R/W
12
ND51
R/W
11
ND50
R/W
10
ND49
R/W
9
ND48
R/W
8
ND47
R/W
7
ND46
R/W
6
ND45
R/W
5
ND44
R/W
4
ND43
R/W
3
ND42
R/W
2
ND41
R/W
1
ND40
R/W
0
ND39
R/W
ND38
R/W
ND37
R/W
ND36
R/W
ND35
R/W
ND34
R/W
ND33
R/W
ND32
R/W
表8-55. New Data 2 Field Descriptions
Bit
Field
Type
Reset
Description
The register holds the New Data flags of Rx Buffers 32 to 63.
The flags are set when the respective Rx Buffer has been
updated from a received frame. The flags remain set until the
Host clears them. A flag is cleared by writing a ’1’to the
corresponding bit position. Writing a ’0’has no effect. A hard
reset will clear the register
31:0
ND63 to ND32
R/W
0
0 - Rx Buffer not updated
1 - Rx Buffer updated from new message
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8.6.4.31 Rx FIFO 0 Configuration (address = h10A0) [reset = h00000000]
The MRAM and start address for this register, F0SA, has special consideration.
• The start address must be word aligned (32-bit) in the MRAM. The 2 least significant bits are ignored on a
write to ensure this behavior.
• When entering the MRAM start address, the 0x8000 prefix is NOT necessary. For example, if the desired
start address is 0x8634, then bits SA[15:0] will be 0x0634.
图8-61. Rx FIFO 0 Configuration Register
31
F0OM
RP
30
22
14
6
29
21
13
5
28
20
12
4
27
F0WM[6:0]
RP
26
18
10
2
25
17
9
24
16
8
23
19
RSVD
R
F0S[6:0]
RP
15
11
F0SA[15:8]
RP
7
3
1
0
F0SA[7:0]
RP
表8-56. Rx FIFO 0 Configuration Field Descriptions
Bit
Field
Type
Reset
Description
FIFO 0 Operation Mode
FIFO 0 can be operated in blocking or in overwrite mode
0 - FIFO 0 blocking mode
31
F0OM
RP
0
1 - FIFO 0 overwrite mode
Rx FIFO 0 Watermark
0 - Watermark interrupt disabled
1-64 - Level for Rx FIFO 0 watermark interrupt (IR.RF0W)
>64 - Watermark interrupt disabled
30:24
23
F0WM[6:0]
RSVD
RP
R
0x0
0
Reserved
Rx FIFO 0 Size
0 - No Rx FIFO 0
22:16
15:0
F0S[6:0]
RP
RP
0x0
1-64 - Number of Rx FIFO 0 elements
>64 - Values greater than 64 are interpreted as 64
The Rx FIFO 0 elements are indexed from 0 to F0S-1
Rx FIFO 0 Start Address
Start address of Rx FIFO 0 in Message RAM
F0SA[15:0]
0x00
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8.6.4.32 Rx FIFO 0 Status (address = h10A4) [reset = h00000000]
图8-62. Rx FIFO 0 Status Register
31
23
15
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
RF0L
R
24
F0F
R
RSVD
R
17
16
RSVD
R
F0PI[5:0]
R
9
1
8
0
RSVD
R
F0GI[5:0]
R
7
RSVD
R
F0FL[6:0]
R
表8-57. Rx FIFO 0 Status Field Descriptions
Bit
Field
Type
Reset
Description
31:26
RSVD
R
0x0
Reserved
Rx FIFO 0 Message Lost
This bit is a copy of interrupt flag IR.RF0L. When IR.RF0L is
reset, this bit is also reset.
0 - No Rx FIFO 0 message lost
1 - Rx FIFO 0 message lost; also set after write attempt to Rx
FIFO 0 of size zero
25
RF0L
R
0
Note: Overwriting the oldest message when RXF0C.F0OM =
‘1’will not set this flag
Rx FIFO 0 Full
24
F0F
R
0
0 - Rx FIFO 0 not full
1 - Rx FIFO 0 full
23:22
21:16
15:14
13:8
7
RSVD
R
R
R
R
R
R
0x0
0x0
0x0
0x0
0
Reserved
Rx FIFO 0 Put Index
Rx FIFO 0 write index pointer, range 0 to 63
F0PI[5:0]
RSVD
Reserved
Rx FIFO 0 Get Index
Rx FIFO 0 read index pointer, range 0 to 63
F0GI[5:0]
RSVD
Reserved
Rx FIFO 0 Fill Level
Number of elements stored in Rx FIFO 0, range 0 to 64.
6:0
F0FL[6:0]
0x0
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8.6.4.33 Rx FIFO 0 Acknowledge (address = h10A8) [reset = h00000000]
图8-63. Rx FIFO 0 Acknowledge Register
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
RSVD
R
RSVD
R
RSVD
R
1
0
RSVD
R
F0AI[5:0]
R/W
表8-58. Rx FIFO 0 Acknowledge Field Descriptions
Bit
Field
Type
Reset
Description
31:24
23:16
15:8
7:6
RSVD
RSVD
RSVD
RSVD
R
0x0
Reserved
R
0x0
Reserved
R
0x0
Reserved
R
0x0
Reserved
Rx FIFO 0 Acknowledge Index
After the Host has read a message or a sequence of messages
from Rx FIFO 0 it has to write the buffer index of the last
element read from Rx FIFO 0 to F0AI. This will set the Rx FIFO
0 Get Index RXF0S.F0GI to F0AI + 1 and update the FIFO 0 Fill
Level RXF0S.F0FL.
5:0
F0AI[5:0]
R/W
0x0
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8.6.4.34 Rx Buffer Configuration (address = h10AC) [reset = h00000000]
图8-64. Rx Buffer Configuration Register
31
23
30
22
29
28
27
26
25
17
24
16
RSVD
21
20
19
18
RSVD
R
15
7
14
6
13
5
12
4
11
3
10
2
9
1
8
0
RBSA[15:8]
RP
RBSA[7:0]
RP
表8-59. Rx Buffer Configuration Field Descriptions
Bit
Field
Type
Reset
Description
31:24
23:16
RSVD
RSVD
R
0x0
Reserved
R
0x0
Reserved
Rx Buffer Start Address
15:0
RBSA[15:0]
RP
0x0
Configures the start address of the Rx Buffers section in the
Message RAM . Also used to reference debug messages A,B,C
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8.6.4.35 Rx FIFO 1 Configuration (address = h10B0) [reset = h00000000]
The MRAM and start address for this register, F1SA, has special consideration.
• The start address must be word aligned (32-bit) in the MRAM. The 2 least significant bits are ignored on a
write to ensure this behavior.
• When entering the MRAM start address, the 0x8000 prefix is NOT necessary. For example, if the desired
start address is 0x8634, then bits SA[15:0] will be 0x0634.
图8-65. Rx FIFO 1 Configuration Register
31
F10M
RP
30
22
14
6
29
21
13
5
28
20
12
4
27
F1WM[6:0]
RP
26
18
10
2
25
17
9
24
16
8
23
19
RSVD
R
F1S[6:0]
RP
15
11
F1SA[15:8]
RP
7
3
1
0
F1SA[7:0]
RP
表8-60. Rx FIFO 1 Configuration Field Descriptions
Bit
Field
Type
Reset
Description
FIFO 1 Operation Mode
FIFO 1 can be operated in blocking or in overwrite mode
0 - FIFO 1 blocking mode
31
F10M
RP
0
1- FIFO 1 overwrite mode
Rx FIFO 1 Watermark
0 - Watermark interrupt disabled
1-64 - Level for Rx FIFO 1 watermark interrupt (IR.RF1W)
>64 - Watermark interrupt disabled
30:24
23
F1WM[6:0]
RSVD
RP
R
0x0
0
Reserved
Rx FIFO 1 Size
0 - No Rx FIFO 1
20:16
15:0
F1S[6:0]
RP
RP
0x0
0x0
1-64 - Number of Rx FIFO 1 elements
>64 - Values greater than 64 are interpreted as 64
The Rx FIFO 1 elements are indexed from 0 to F1S - 1
Rx FIFO 1 Start Address
Start address of Rx FIFO 1 in Message RAM
F1SA[15:0]
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8.6.4.36 Rx FIFO 1 Status (address = h10B4) [reset = h00000000]
图8-66. Rx FIFO 1 Status Register
31
23
15
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
26
18
10
2
25
RF1L
R
24
F1F
R
DMS[1:0]
R
RSVD
R
17
16
RSVD
R
F1PI[5:0]
R
9
1
8
0
RSVD
R
F1GI[5:0]
R
3
7
RSVD
R
F1FL[6:0]
R
表8-61. Rx FIFO 1 Status Field Descriptions
Bit
Field
Type
Reset
Description
Debug Message Status
00 - Idle state, wait for reception of debug messages, DMA
request is cleared
01 - Debug message A received
10 - Debug messages A, B received
11 - Debug messages A, B, C received, DMA request is set
31:30
29:26
DMS[1:0]
RSVD
R
0x0
R
0x0
Reserved
Rx FIFO 1 Message Lost
This bit is a copy of interrupt flag IR.RF1L. When IR.RF1L is
reset, this bit is also reset
0 - No Rx FIFO 1 message lost
1 - Rx FIFO 1 message lost, also set after write attempt to Rx
FIFO 1 of size zero
25
RF1L
R
0
Note: Overwriting the oldest message when RXF1C.F1OM =
‘1’will not set this flag.
Rx FIFO 1 Full
24
F1F
R
0
0 - Rx FIFO 1 not full
1 - Rx FIFO 1 full
23:22
21:16
15:14
13:8
7
RSVD
R
R
R
R
R
R
0x0
0x0
0x0
0x0
0
Reserved
Rx FIFO 1 Put Index
Rx FIFO 1 write index pointer, range 0 to 63
F1PI[5:0]
RSVD
Reserved
Rx FIFO 1 Get Index
Rx FIFO 1 read index pointer, range 0 to 63.
F1GI[5:0]
RSVD
Reserved
Rx FIFO 1 Fill Level
Number of elements stored in Rx FIFO 1, range 0 to 64.
6:0
F1FL[6:0]
0x0
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8.6.4.37 Rx FIFO 1 Acknowledge (address = h10B8) [reset = h00000000]
图8-67. Rx FIFO 1 Acknowledge Register
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
RSVD
R
RSVD
R
RSVD
R
1
0
RSVD
R
F1AI[5:0]
R/W
表8-62. Rx FIFO 1 Acknowledge Field Descriptions
Bit
Field
Type
Reset
Description
31:24
23:16
15:8
7:6
RSVD
RSVD
RSVD
RSVD
R
0x0
Reserved
R
0x0
Reserved
R
0x0
Reserved
R
0x0
Reserved
Rx FIFO 1 Acknowledge Index
After the Host has read a message or a sequence of messages
from Rx FIFO 1 it has to write the buffer index of the last
element read from Rx FIFO 1 to F1AI. This will set the Rx FIFO
1 Get Index RXF1S.F1GI to F1AI + 1 and update the FIFO 1 Fill
Level RXF1S.F1FL.
5:0
F1AI[5:0]
R/W
0x0
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8.6.4.38 Rx Buffer/FIFO Element Size Configuration (address = h10BC) [reset = h00000000]
图8-68. Rx Buffer/FIFO Element Size Configuration Register
31
23
15
30
22
14
6
29
28
20
12
4
27
19
11
26
18
10
2
25
17
24
16
8
RSVD
R
21
RSVD
R
13
9
RBDS[2:0]
RP
RSVD
R
7
RSVD
R
5
3
RSVD
R
1
0
F1DS[2:0]
RP
F0DS[2:0]
RP
表8-63. Rx Buffer/FIFO Element Size Configuration Field Descriptions
Bit
Field
Type
Reset
Description
Reserved
Reserved
Reserved
31:24
31:24
31:24
RSVD
RSVD
RSVD
R
0x0
R
0x0
R
0x0
Rx Buffer Data Field Size
000 - 8 byte data field
001 - 12 byte data field
010 - 16 byte data field
011 - 20 byte data field
100 - 24 byte data field
101 - 32 byte data field
110 - 48 byte data field
111 - 64 byte data field
10:8
RBDS[2:0]
RSVD
RP
R
0x0
7
0
Reserved
Rx FIFO 1 Data Field Size
000 - 8 byte data field
001 - 12 byte data field
010 - 16 byte data field
011 - 20 byte data field
100 - 24 byte data field
101 - 32 byte data field
110 - 48 byte data field
111 - 64 byte data field
6:4
3
F1DS[2:0]
RSVD
RP
R
0x0
0
Reserved
Rx FIFO 0 Data Field Size
000 - 8 byte data field
001 - 12 byte data field
010 - 16 byte data field
011 - 20 byte data field
100 - 24 byte data field
101 - 32 byte data field
110 - 48 byte data field
111 - 64 byte data field
2:0
F0DS[2:0]
RP
0x0
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8.6.4.39 Tx Buffer Configuration (address = h10C0) [reset = h00000000]
The MRAM and start address for this register, TBSA, has special consideration.
• The start address must be word aligned (32-bit) in the MRAM. The 2 least significant bits are ignored on a
write to ensure this behavior.
• When entering the MRAM start address, the 0x8000 prefix is NOT necessary. For example, if the desired
start address is 0x8634, then bits SA[15:0] will be 0x0634.
图8-69. Tx Buffer Configuration Register
31
RSVD
R
30
TFQM
RP
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
TFQS[5:0]
RP
23
22
RSVD
R
NDTB[5:0]
RP
15
7
14
6
TBSA[15:8]
RP
1
0
TBSA[7:0]
RP
表8-64. Tx Buffer Configuration Field Descriptions
Bit
Field
Type
Reset
Description
31
RSVD
R
0
Reserved
Tx FIFO/Queue Mode
0 - Tx FIFO operation
1 - Tx Queue operation
30
TFQM
RP
0
Transmit FIFO/Queue Size
0 - No Tx FIFO/Queue
1-32 - Number of Tx Buffers used for Tx FIFO/Queue
>32 - Values greater than 32 are interpreted as 32
29:24
23:22
21:16
TFQS[5:0]
RSVD
RP
R
0x0
0x0
0x0
Reserved
Number of Dedicated Transmit Buffers
0 - No Dedicated Tx Buffers
1-32 - Number of Dedicated Tx Buffers
>32 - Values greater than 32 are interpreted as 32
NDTB[5:0]
RP
Tx Buffers Start Address
Start address of Tx Buffers section in Message RAM
Note: Be aware that the sum of TFQS and NDTB may be not
greater than 32. There is no check for erroneous configurations.
The Tx Buffers section in the Message RAM starts with the
dedicated Tx Buffers.
15:0
TBSA[15:0]
RP
0x0
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8.6.4.40 Tx FIFO/Queue Status (address = h10C4) [reset = h00000000]
图8-70. Tx FIFO/Queue Status Register
31
23
15
7
30
22
29
28
20
12
4
27
19
11
3
26
25
17
9
24
16
8
RSVD
R
21
TFQF
R
18
RSVD
R
TFQPI[4:0]
R
14
RSVD
R
13
10
TFGI[4:0]
R
2
6
5
1
0
RSVD
R
TFFL[5:0]
R
表8-65. Tx FIFO/Queue Status Field Descriptions
Bit
Field
Type
Reset
Description
Reserved
Reserved
31:24
23:22
RSVD
RSVD
R
0x0
R
0x0
Tx FIFO/Queue Full
21
TFQF
R
0
0 - Tx FIFO/Queue not full
1 - Tx FIFO/Queue full
Tx FIFO/Queue Put Index
Tx FIFO/Queue write index pointer, range 0 to 31.
20:16
15:13
TFQPI[4:0]
RSVD
R
R
0x0
0x0
Reserved
Tx FIFO Get Index
Tx FIFO read index pointer, range 0 to 31. Read as zero when
Tx Queue operation is configured (TXBC.TFQM = ‘1’).
12:8
7:6
TFGI[4:0]
RSVD
R
R
0x0
0x0
Reserved
Tx FIFO Free Level
Number of consecutive free Tx FIFO elements starting from
TFGI, range 0 to 32. Read as zero when Tx Queue operation is
configured (TXBC.TFQM = ‘1’)
Note: In case of mixed configurations where dedicated Tx
Buffers are combined with a Tx FIFO or a Tx Queue, the Put
and Get Indices indicate the number of the Tx Buffer starting
with the first dedicated Tx Buffers
5:0
TFFL[5:0]
R
0x0
Example: For a configuration of 12 dedicated Tx Buffers and a
Tx FIFO of 20 Buffers a Put Index of 15 points to the fourth
buffer of the Tx FIFO
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8.6.4.41 Tx Buffer Element Size Configuration (address = h10C8) [reset = h00000000]
图8-71. Tx Buffer Element Size Configuration Register
31
23
15
7
30
22
14
6
29
21
13
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
RSVD
R
RSVD
R
RSVD
R
5
RSVD
R
1
0
TBDS[2:0]
RP
表8-66. Tx Buffer Element Size Configuration Field Descriptions
Bit
Field
Type
Reset
Description
Reserved
Reserved
Reserved
Reserved
31:24
23:16
15:8
7:3
RSVD
RSVD
RSVD
RSVD
R
0x0
R
0x0
R
0x0
R
0x0
Tx Buffer Data Field Size
000 - 8 byte data field
001 - 12 byte data field
010 - 16 byte data field
011 - 20 byte data field
100 - 24 byte data field
101 - 32 byte data field
110 - 48 byte data field
111 - 64 byte data field
2:0
TBDS[2:0]
RP
0x0
Note: In case the data length code DLC of a Tx Buffer element
is configured to a value higher than the Tx Buffer data field size
TXESC.TBDS, the bytes not defined by the Tx Buffer are
transmitted as “0xCC”(padding bytes).
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8.6.4.42 Tx Buffer Request Pending (address = h10CC) [reset = h00000000]
图8-72. Tx Buffer Request Pending Register
31
TRP31
R
30
TRP30
R
29
TRP29
R
28
TRP28
R
27
TRP27
R
26
TRP26
R
25
TRP22
R
24
TRP24
R
16
23
22
21
20
19
18
17
TRP23
R
TRP22
R
TRP21
R
TRP20
R
TRP19
R
TRP18
R
TRP17
R
TRP16
R
15
14
13
12
11
10
9
8
TRP15
R
TRP14
R
TRP13
R
TRP12
R
TRP11
R
TRP10
R
TRP9
R
TRP8
R
7
6
5
4
3
2
1
0
TRP7
R
TRP6
R
TRP5
R
TRP4
R
TRP3
R
TRP2
R
TRP1
R
TRP0
R
表8-67. Tx Buffer Request Pending Field Descriptions
Bit
Field
Type
Reset
Description
Transmission Request Pending
Each Tx Buffer has its own Transmission Request Pending bit.
The bits are set via register TXBAR.
The bits are reset after a requested transmission has completed
or has been cancelled via register TXBCR. TXBRP bits are set
only for those Tx Buffers configured via TXBC. After a TXBRP
bit has been set, a Tx scan is started to check for the pending
Tx request with the highest priority (Tx Buffer with lowest
Message ID).
A cancellation request resets the corresponding transmission
request pending bit of register TXBRP. In case a transmission
has already been started when a cancellation is requested, this
is done at the end of the transmission, regardless whether the
transmission was successful or not. The cancellation request
bits are reset directly after the corresponding TXBRP bit has
been reset.
After a cancellation has been requested, a finished cancellation
is signaled via TXBCF
31:0
TRP31 to TRP0
R
0
•
•
•
•
after successful transmission together with the
corresponding TXBTO bit
when the transmission has not yet been started at the point
of cancellation
when the transmission has been aborted due to lost
arbitration
when an error occurred during frame transmission
In DAR mode all transmissions are automatically cancelled if
they are not successful. The corresponding TXBCF bit is set for
all unsuccessful transmissions.
0 - No transmission request pending
1- Transmission request pending
Note: TXBRP bits which are set while a Tx scan is in progress
are not considered during this particular Tx scan. In case a
cancellation is requested for such a Tx Buffer, this Add Request
is cancelled immediately, the corresponding TXBRP bit is reset.
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8.6.4.43 Tx Buffer Add Request (address = h10D0) [reset = h00000000]
图8-73. Tx Buffer Add Request Register
31
AR31
R/W
23
30
AR30
R/W
22
29
AR29
R/W
21
28
AR28
R/W
20
27
AR27
R/W
19
26
AR26
R/W
18
25
AR25
R/W
17
24
AR24
R/W
16
AR23
R/W
15
AR22
R/W
14
AR21
R/W
13
AR20
R/W
12
AR19
R/W
11
AR18
R/W
10
AR17
R/W
9
AR16
R/W
8
AR14
R/W
7
AR14
R/W
6
AR13
R/W
5
AR12
R/W
4
AR11
R/W
3
AR10
R/W
2
AR9
R/W
1
AR8
R/W
0
AR7
R/W
AR6
R/W
AR5
R/W
AR4
R/W
AR3
R/W
AR2
R/W
AR1
R/W
AR0
R/W
表8-68. Tx Buffer Add Request Field Descriptions
Bit
Field
Type
Reset
Description
Add Request
Each Tx Buffer has its own Add Request bit. Writing a ‘1’will
set the corresponding Add Request bit; writing a ‘0’has no
impact. This enables the Host to set transmission requests for
multiple Tx Buffers with one write to TXBAR. TXBAR bits are set
only for those Tx Buffers configured via TXBC. When no Tx
scan is running, the bits are reset immediately, else the bits
remain set until the Tx scan process has completed.
0 - No transmission request added
31:0
AR31 to AR0
R/W
0
1 - Transmission requested added
Note: If an add request is applied for a Tx Buffer with pending
transmission request (corresponding TXBRP bit already set),
this add request is ignored.
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8.6.4.43.1 Tx Buffer Cancellation Request (address = h10D4 [reset = h00000000]
图8-74. Tx Buffer Cancellation Request Register
31
CR31
R/W
23
30
CR30
R/W
22
29
CR29
R/W
21
28
CR28
R/W
20
27
CR27
R/W
19
26
CR26
R/W
18
25
CR25
R/W
17
24
CR24
R/W
16
CR23
R/W
15
CR22
R/W
14
CR21
R/W
13
CR20
R/W
12
CR19
R/W
11
CR18
R/W
10
CR17
R/W
9
CR16
R/W
8
CR15
R/W
7
CR14
R/W
6
CR13
R/W
5
CR12
R/W
4
CR11
R/W
3
CR10
R/W
2
CR9
R/W
1
CR8
R/W
0
CR7
R/W
CR6
R/W
CR5
R/W
CR4
R/W
CR3
R/W
CR2
R/W
CR1
R/W
CR0
R/W
表8-69. Tx Buffer Cancellation Request Field Descriptions
Bit
Field
Type
Reset
Description
Cancellation Request
Each Tx Buffer has its own Cancellation Request bit. Writing a
‘1’will set the corresponding Cancellation Request bit;
writing a ‘0’has no impact. This enables the Host to set
cancellation requests for multiple Tx Buffers with one write to
TXBCR. TXBCR bits are set only for those Tx Buffers configured
via TXBC. The bits remain set until the corresponding bit of
TXBRP is reset.
31:0
CR31 to CR0
R/W
0
0 - No cancellation pending
1 - Cancellation pending
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8.6.4.43.2 Tx Buffer Add Request Transmission Occurred (address = h10D8) [reset = h00000000]
图8-75. Tx Buffer Add Request Transmission Occurred Register
31
TO31
R
30
TO30
R
29
TO29
R
28
TO28
R
27
TO27
R
26
TO26
R
25
TO25
R
24
TO24
R
23
22
21
20
19
18
17
16
TO23
R
TO22
R
TO21
R
TO20
R
TO19
R
TO18
R
TO17
R
TO16
R
15
14
13
12
11
10
9
8
TO15
R
TO14
R
TO13
R
TO12
R
TO11
R
TO10
R
TO9
R
TO8
R
7
6
5
4
3
2
1
0
TO7
R
TO6
R
TO5
R
TO4
R
TO3
R
TO2
R
TO1
R
TO0
R
表8-70. Tx Buffer Add Request Transmission Occurred Field Descriptions
Bit
Field
Type
Reset
Description
Transmission Occurred
Each Tx Buffer has its own Transmission Occurred bit. The bits
are set when the corresponding TXBRP bit is cleared after a
successful transmission. The bits are reset when a new
transmission is requested by writing a ‘1’to the
corresponding bit of register TXBAR.
31:0
TO31 to TO0
R
0
0 - No transmission occurred
1 - Transmission occurred
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8.6.4.43.3 Tx Buffer Cancellation Finished (address = h10DC) [reset = h00000000]
图8-76. Tx Buffer Cancellation Finished Register
31
CF31
R
30
CF30
R
29
CF29
R
28
CF28
R
27
CF27
R
26
CF26
R
25
CF25
R
24
CF24
R
23
22
21
20
19
18
17
16
CF23
R
CF22
R
CF21
R
CF20
R
CF19
R
CF18
R
CF17
R
CF16
R
15
14
13
12
11
10
9
8
CF15
R
CF14
R
CF13
R
CF12
R
CF11
R
CF10
R
CF9
R
CF8
R
7
6
5
4
3
2
1
0
CF7
R
CF6
R
CF5
R
CF4
R
CF3
R
CF2
R
CF1
R
CF0
R
表8-71. Tx Buffer Cancellation Finished Field Descriptions
Bit
Field
Type
Reset
Description
Cancellation Finished
Each Tx Buffer has its own Cancellation Finished bit. The bits
are set when the corresponding TXBRP bit is cleared after a
cancellation was requested via TXBCR. In case the
corresponding TXBRP bit was not set at the point of
cancellation, CF is set immediately. The bits are reset when a
new transmission is requested by writing a ‘1’to the
corresponding bit of register TXBAR.
31:0
CF31 to CF0
R
0
0 - No transmit buffer cancellation
1 - Transmit buffer cancellation finished
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8.6.4.43.4 Tx Buffer Transmission Interrupt Enable (address = h10E0) [reset = h00000000]
图8-77. Tx Buffer Transmission Interrupt Enable Register
31
TIE31
R/W
23
30
TIE30
R/W
22
29
TIE29
R/W
21
28
TIE28
R/W
20
27
TIE27
R/W
19
26
TIE26
R/W
18
25
TIE25
R/W
17
24
TIE24
R/W
16
TIE23
R/W
15
TIE22
R/W
14
TIE21
R/W
13
TIE20
R/W
12
TIE19
R/W
11
TIE18
R/W
10
TIE17
R/W
9
TIE16
R/W
8
TIE15
R/W
7
TIE14
R/W
6
TIE13
R/W
5
TIE12
R/W
4
TIE11
R/W
3
TIE10
R/W
2
TIE9
R/W
1
TIE8
R/W
0
TIE7
R/W
TIE6
R/W
TIE5
R/W
TIE4
R/W
TIE3
R/W
TIE2
R/W
TIE1
R/W
TIE0
R/W
表8-72. Tx Buffer Transmission Interrupt Enable Field Descriptions
Bit
Field
Type
Reset
Description
Transmission Interrupt Enable
Each Tx Buffer has its own Transmission Interrupt Enable bit.
0 - Transmission interrupt disabled
TIE31 to TIE0
R/W
0
1 - Transmission interrupt enable
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8.6.4.43.5 Tx Buffer Cancellation Finished Interrupt Enable (address = h10E4) [reset = h00000000]
图8-78. Tx Buffer Cancellation Finished Interrupt Enable Register
31
CFIE31
R/W
30
CFIE30
R/W
29
CFIE29
R/W
28
CFIE28
R/W
27
CFIE27
R/W
26
CFIE26
R/W
25
CFIE25
R/W
17
24
CFIE24
R/W
16
23
22
21
20
19
18
CFIE23
R/W
CFIE22
R/W
CFIE21
R/W
CFIE20
R/W
CFIE19
R/W
CFIE18
R/W
CFIE17
R/W
9
CFIE16
R/W
8
15
14
13
12
11
10
CFIE15
R/W
CFIE14
R/W
CFIE13
R/W
CFIE12
R/W
CFIE11
R/W
CFIE10
R/W
CFIE9
R/W
1
CFIE8
R/W
0
7
6
5
4
3
2
CFIE7
R/W
CFIE6
R/W
CFIE5
R/W
CFIE4
R/W
CFIE3
R/W
CFIE2
R/W
CFIE1
R/W
CFIE0
R/W
表8-73. Tx Buffer Cancellation Finished Interrupt Enable Field Descriptions
Bit
Field
Type
Reset
Description
Bit 31:0 CFIE[31:0]: Cancellation Finished Interrupt Enable
Each Tx Buffer has its own Cancellation Finished Interrupt
Enable bit.
31:0
CFIE31 to CFIE0
RW
0
0 - Cancellation finished interrupt disabled
1 - Cancellation finished interrupt enabled
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8.6.4.43.6 Reserved (address = h10E8) [reset = h00000000]
图8-79. Reserved
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
RSVD
R
RSVD
R
RSVD
R
1
0
RSVD
R
表8-74. Reserved Field Descriptions
Bit
31:0
Field
Type
Reset
Description
RSVD
R
0
Reserved
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8.6.4.43.7 Reserved (address = h10EC) [reset = h00000000]
图8-80. Reserved
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
RSVD
R
RSVD
R
RSVD
R
1
0
RSVD
R
表8-75. Reserved Field Descriptions
Bit
31:0
Field
Type
Reset
Description
RSVD
R
0
Reserved
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8.6.4.43.8 Tx Event FIFO Configuration (address = h10F0) [reset = h00000000]
The MRAM and start address for this register, EFSA, has special consideration.
• The start address must be word aligned (32-bit) in the MRAM. The 2 least significant bits are ignored on a
write to ensure this behavior.
• When entering the MRAM start address, the 0x8000 prefix is NOT necessary. For example, if the desired
start address is 0x8634, then bits SA[15:0] will be 0x0634.
图8-81. Tx Event FIFO Configuration Register
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
RSVD
R
EFWM[5:0]
RP
RSVD
R
EFS[5:0]
RP
EFSA[15:8]
RP
1
0
EFSA[7:0]
RP
表8-76. Tx Event FIFO Configuration Field Descriptions
Bit
Field
Type
Reset
Description
31:30
29:24
23:22
RSVD
R
0x0
Reserved
Event FIFO Watermark
0 - Watermark interrupt disabled
1-32 - Level for Tx Event FIFO watermark interrupt (IR.TEFW)
>32 - Watermark interrupt disabled
EFWM[5:0]
RSVD
RP
R
0x0
0x0
Reserved
Event FIFO Size
0 - Tx Event FIFO disabled
21:16
15:0
EFS[5:0]
RP
RP
0x0
0x0
1-32 - Number of Tx Event FIFO elements
>32 - Values greater than 32 are interpreted as 32
The Tx Event FIFO elements are indexed from 0 to EFS - 1
Event FIFO Start Address
Start address of Tx Event FIFO in Message RAM
EFSA[15:0]
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8.6.4.43.9 Tx Event FIFO Status (address = h10F4) [reset = h00000000]
图8-82. Tx Event FIFO Status Register
31
23
15
7
30
29
21
13
5
28
20
12
4
27
19
11
3
26
25
TEFL
R
24
EFF
R
RSVD
R
22
RSVD
R
18
17
16
EFPI[4:0]
R
14
10
9
1
8
0
RSVD
R
REFGI[4:0]
R
2
6
RSVD
R
EFFL[5:0]
R
表8-77. Tx Event FIFO Status Field Descriptions
Bit
Field
Type
Reset
Description
31:26
RSVD
R
0x0
Reserved
Tx Event FIFO Element Lost
This bit is a copy of interrupt flag IR.TEFL. When IR.TEFL is
reset, this bit is also reset.
0 - No Tx Event FIFO element lost
25
TEFL
R
0
1 - Tx Event FIFO element lost, also set after write attempt to Tx
Event FIFO of size zero.
Event FIFO Full
24
EFF
R
0
0 - Tx Event FIFO not full
1 - Tx Event FIFO full
23:21
20:16
15:13
12:8
7:6
RSVD
R
R
R
R
R
R
0x0
0x0
0x0
0x0
0x0
0x0
Reserved
Event FIFO Put Index
Tx Event FIFO write index pointer, range 0 to 31.
EFPI[4:0]
RSVD
Reserved
Event FIFO Get Index
Tx Event FIFO read index pointer, range 0 to 31.
REFGI[4:0]
RSVD
Reserved
Event FIFO Fill Level
Number of elements stored in Tx Event FIFO, range 0 to 32
5:0
EFFL[5:0]
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8.6.4.43.10 Tx Event FIFO Acknowledge (address = h10F8) [reset = h00000000]
图8-83. Tx Event FIFO Acknowledge Register
31
23
15
7
30
22
14
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
25
17
9
24
16
8
RSVD
R
RSVD
R
RSVD
R
6
RSVD
R
2
1
0
EFAI[4:0]
R/W
表8-78. Tx Event FIFO Acknowledge Field Descriptions
Bit
Field
Type
Reset
Description
31:24
23:16
15:18
7:5
RSVD
RSVD
RSVD
RSVD
R
0x0
Reserved
R
0x0
Reserved
R
0x0
Reserved
R
0x0
Reserved
Event FIFO Acknowledge Index
After the Host has read an element or a sequence of elements
from the Tx Event FIFO it has to write the index of the last
element read from Tx Event FIFO to EFAI. This will set the Tx
Event FIFO Get Index TXEFS.EFGI to EFAI + 1 and update the
Event FIFO Fill Level TXEFS.EFFL.
4:0
EFAI[4:0]
E/W
0x0
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8.6.4.43.11 Reserved (address = h10FC) [reset = h00000000]
图8-84. Reserved
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
RSVD
R
RSVD
R
RSVD
R
1
0
RSVD
R
表8-79. Reserved Field Descriptions
Bit
31:0
Field
Type
Reset
Description
RSVD
R
0
Reserved
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Design Consideration
9.1.1 Crystal and Clock Input Requirements
Selecting the crystal or clock input depends upon system implementation. To support 2 and 5 Mbps CAN FD the
clock in or crystal needs to have 0.5% frequency accuracy. The minimum value of 20 MHz is needed to support
CAN FD with a rate of 2 Mbps. The recommended value for CLKIN or crystal is 40 MHz to meet CAN FD rates
up to 5 Mbps data rates in order to support higher data throughout. If a crystal is used see the manufacturer’s
documentation on proper biasing.
备注
The TCAN4550-Q1 was evaluated with the NX2016SA 20MHz and 40MHz crystals
9.1.2 Bus Loading, Length and Number of Nodes
A typical CAN application can have a maximum bus length of 40 m and maximum stub length of 0.3 m. However,
with careful design, users can have longer cables, longer stub lengths, and many more nodes to a bus. A high
number of nodes require a transceiver with high input impedance such as this transceiver family.
Many CAN organizations and standards have scaled the use of CAN for applications outside the original ISO
11898-2:2016 standard. They made system level trade off decisions for data rate, cable length, and parasitic
loading of the bus. Examples of these CAN systems level specifications are ARINC825, CANopen, DeviceNet,
SAE J2284, SAE J1939, and NMEA200.
A CAN system design is a series of tradeoffs. In ISO 11898-2:2016 the driver differential output is specified with
a bus load that can range from 50 Ω to 65 Ω where the differential output must be greater than 1.5 V. The
TCAN4550-Q1 is specified to meet the 1.5 V requirement with a across this load range and is specified to meet
1.4 V differential output at 45 Ω bus load. The differential input resistance of this family of transceiver is a
minimum of 30 kΩ. If 167 of these transceivers are in parallel on a bus, this is equivalent to a 180 Ω differential
load in parallel with the 60 Ω from termination gives a total bus load of 45 Ω. Therefore, this family theoretically
supports over 167 transceivers on a single bus segment with margin to the 1.2 V minimum differential input
voltage requirement at each receiving node. However, for CAN network design margin must be given for signal
loss across the system and cabling, parasitic loadings, timing, network imbalances, ground offsets and signal
integrity thus a practical maximum number of nodes is much lower. Bus length may also be extended beyond the
original ISO 11898-2:2016 standard of 40 m by careful system design and data rate tradeoffs. For example,
CANopen network design guidelines allow the network to be up to 1 km with changes in the termination
resistance, cabling, less than 64 nodes and significantly lowered data rate.
This flexibility in CAN network design is one of its key strengths allowing for these system level network
extensions and additional standards to build on the original ISO 11898-2 CAN standard. However, when using
this flexibility, the CAN network system designer must take the responsibility of good network design to ensure
robust network operation.
9.1.3 CAN Termination
The standard CAN bus interconnection to be a single twisted pair cable (shielded or unshielded) with 120 Ω
characteristic impedance (ZO).
Termination
Resistors equal to the characteristic impedance of the line should be used to terminate both ends of the cable to
prevent signal reflections. Unterminated drop-lines (stubs) connecting nodes to the bus should be kept as short
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as possible to minimize signal reflections. The termination may be in a node but is generally not recommended,
especially if the node may be removed from the bus. Termination must be carefully placed so that it is not
removed from the bus. System level CAN implementations such as CANopen allow for different termination and
cabling concepts for example to add cable length.
Node 2
Node 3
Node n
(with termination)
MCU or DSP
MCU or DSP
Node 1
MCU or DSP
CAN
Controller
CAN
Controller
MCU or DSP
TCAN4550
RTERM
TCAN4550
TCAN1051/G
TCAN1042/G
RTERM
图9-1. Typical CAN Bus
Termination may be a single 120 Ω resistor at each end of the bus, either on the cable or in a terminating node.
If filtering and stabilization of the common mode voltage of the bus is desired then “split termination” may be
used, see 图 9-2. Split termination improves the electromagnetic emissions behavior of the network by
eliminating fluctuations in the bus common mode voltage levels at the start and end of message transmissions.
Split Termination
Standard Termination
CANH
CANH
RTERM/2
CAN
Transceiver
CAN
Transceiver
RTERM
CSPLIT
RTERM/2
CANL
CANL
图9-2. CAN Bus Termination Concepts
9.1.3.1 CAN Bus Biasing
Bus biasing can be normal biasing, active in normal mode and inactive in low-power mode. Automatic voltage
biasing is where the bus is active in normal mode but is controlled by the voltage between CANH and CANL in
lower power modes. See 图 9-3 for the state diagram on how the TCAN4550-Q1 performs automatic biasing. 图
9-4 provides the bus biasing based upon the mode of operation.
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Recessive state > tWK-FILTER
Wait
Bus Biasing Inactive
Bus Biasing Inactive
Power On
Dominant state > tWK-FILTER
tWK_TIMEOUT
1
Bus Biasing Inactive
Recessive state > tWK-FILTER
tWK_TIMEOUT
2
Bus Biasing Inactive
Dominant state > tWK-FILTER
On implementation
enters Normal Mode
tSILENCE expired and implementation
In low power mode
3
Bus Biasing Active
From all other nodes
Low Power Mode:
Dominant state > tWK-FILTER
Normal Mode: Dominant state
Low Power Mode:
Recessive state > tWK-FILTER
Normal Mode: Recessive state
tSILENCE expired and implementation
In low power mode
4
Bus Biasing
Active
图9-3. Automatic bus biasing state diagram
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Power Up &
Reset
Prog to
Sleep
Prog to
Normal
Sleep Mode
Bus Bias: GND
Standby Mode
Bus Bias: GND
Normal Mode
Bus Bias: 2.5 V
Fail-Safe
WAKE Pin
Prog to
Sleep
Prog to
Standby or
Fault
Yes
tSILENCE
Expired
Yes
tSILENCE
Expired
No
No
tSILENCE
Expired
WAKE
Pin
Standby Mode
Bus Bias: 2.5 V
Sleep Mode
Bus Bias: 2.5 V
WUP
WUP
tSILENCE
Expired
图9-4. Bus Biasing Based on Modes of Operation
9.1.4 INH Brownout Behavior
A brownout condition takes place when VSUP ramps down below the minimum recommended operation
conditions and then ramps back above the recommended operating conditions. 图 9-5 provides the behavior of
the INH pin based upon process, voltage and temperature during this condition. Once VSUP drops below the
digital core going into reset, the device will have to be reprogrammed as all registers will be set back to default.
~ 5.5 V
UVSUP rise
VSUP
Digital core out
of reset
UVSUP fall
~ 4.7 V
~ 3.6 V
~ 4.25 V
Digital core into reset
1.67 V > INH on > 4.15 V
1.42 V < INH off < 3.14 V
INH
图9-5. INH Brownout Behavior
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9.2 Typical Application
The TCAN4550-Q1 is typically used in applications with a host microprocessor or FPGA that does not include
the link layer portion of the CAN protocol. Below is a typical application configuration for 3.3 V microprocessor
applications.
3 kΩ
10 µF
10 nF
33 kΩ
VBAT
330 nF
10 µF
100 nF
EN
VIN
VSUP
WAKE
FLTR
VCCOUT
Voltage
Regulator
(e.g.
INH
VINT
VLVRX
TPSxxxx)
LDO(s)
Filter
VOUT
VIO
Under
Voltage
CNTL
POR
TCAN4550
VIO
100 nF
10 µF
CANH
TXD_INT
RXD_INT
VINT
nWKRQ
VCC
TX/RX Data
Buffer
GPIO3
TX/RX CAN-FD
Controller with
Filters
VIO
2-wire
CAN
bus
RST
SCLK
SDI
Reset
SCLK
CAN-FD
SPI
Transceiver
System
Controller
MOSI
MISO
SDO
MCU
CANL
nCS
nCS
GPIO2
GPIO1
GPIO
GPO2
nINT
GPIO1
Optional:
Terminating
Node
Optional:
Filtering,
GND
OSC1
OSC2
Transient and
ESD
40 MHz
图9-6. Typical CAN Applications for TCAN4550-Q1 for 3.3 V µC and Crystal
Note: Add decoupling capacitors as needed.
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3 kΩ
10 µF
10 nF
33 kΩ
VBAT
330 nF
10 µF
100 nF
EN
VIN
VSUP
WAKE
FLTR
VCCOUT
Voltage
Regulator
(e.g.
INH
VINT
VLVRX
TPSxxxx)
LDO(s)
Filter
VOUT
VIO
Under
Voltage
CNTL
POR
VIO
TCAN4550
100 nF
10 µF
CANH
TXD_INT
RXD_INT
VINT
nWKRQ
TX/RX Data
Buffer
GPIO3
VCC
TX/RX CAN-FD
Controller with
Filters
VIO
2-wire
CAN
bus
RST
SCLK
SDI
Reset
SCLK
CAN-FD
SPI
Transceiver
System
Controller
MOSI
MISO
SDO
MCU
CANL
nCS
nCS
GPIO2
GPIO1
GPIO
GPO2
nINT
GPIO1
Optional:
Terminating
Node
Optional:
Filtering,
GND
OSC1
OSC2
Transient and
ESD
20 MHz
OSC1
OSC2
图9-7. Typical CAN Applications for TCAN4550-Q1 for 3.3 V µC; Clock from MCU
9.2.1 Detailed Requirements
The TCAN4550-Q1 works with 3.3 V and 5 V microprocessors when using the VIO pin from the microprocessor
voltage regulator. The bus termination is shown for illustrative purposes.
9.2.2 Detailed Design Procedures
The TCAN4550-Q1 is designed to work in application using the ISO 11898 standard supporting bus loads from
50 Ω to 65 Ω. As the TCAN4550-Q1 supports CAN FD data rates up to 8 Mbps it is recommended to use a 40
MHz crystal and keep trace lengths matched and short as feasible between the processor and device. As the
CAN stub length are defined in the standard it is recommended to design the system according to these. As the
TCAN4550-Q1 CAN transceiver is self-powered but also allows for up to 70 mA at 5 V to be sourced on VCCOUT
,
the system design needs to account for the CAN transceiver requirements when determining the load the LDO is
to support. With this and the high temperature and input voltage range it is recommended to use a high-k board
using proper thermal dissipation methods to ensure the highest performance.
9.2.3 Application Curves
图9-8 and 图9-9 shows the behavior of the 5 V LDO in relationship to ISUP, VSUP, LDO load of 70 mA, CAN bus
dominant and ambient temperature. The ISUP current is based upon a 70 mA load on VCCOUT and the CAN bus
held dominant for about a total of 120 mA. As can be seen, an ambient temperature of 125°C can cause a
thermal shut down event when VSUP reaches 20 V and VCCOUT is providing 70 mA to a load. The load on the
CAN bus is 60 Ω. When the CAN bus load is 50 Ωa VSUP of 19 V and ambient temperature of 125 can trigger
a thermal shut down event. The reason the curve shows ISUP leveling out to approximately 74.5 mA is due to
thermal shut down where the device shuts off the LDO and CAN transceiver. The device cools below TSD
leaving thermal shutdown quickly. When the TSD event goes away the device then enters standby mode, turning
on the LDO. The 74.5 mA is the 70 mA LDO load and a dominant on the CAN bus in standby mode. This is
happening quickly enough that LDO shut off is not seen. If the TSD event is prolonged the current would drop to
micro-amps and VCCOUT would be 0 V once the decoupling capacitor discharges.
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140
120
100
80
5.5
5
4.5
4
3.5
3
2.5
2
60
40
1.5
1
-40°C
25°C
55°C
85°C
105°C
125°C
-40°C
25°C
55°C
85°C
105°C
125°C
20
0.5
0
0
0
3
6
9
12
15
VSUP (V)
18
21
24
27
30
D003
0
3
6
9
12
15
VSUP (V)
18
21
24
27
30
D005
A.
VCCOUT = 5 V at 70
mA
CAN Bus =
Dominant
A.
VCCOUT = 5 V at 70
mA
CAN Bus =
Dominant
CAN Load = 60 Ω
CAN Load = 60 Ω
图9-8. ISUP vs VSUP CAN Dominant with 70 mA
图9-9. VCCOUT vs VSUP
Load on VCCOUT
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10 Power Supply Recommendations
The TCAN4550-Q1 is designed to operate off of the battery Vbat. It has internal regulators to reduce the voltage
to acceptable low power levels supporting the CAN FD controller, CAN transceiver and low voltage CAN
receiver. In order to support a wide range of microprocessors the SPI and GPIO are powered off of the VIO pin
which supports levels from 3 V to 5.5 V. Bulk capacitance, should be placed on the VSUP and the VIO voltage
rails where system requirements are met. It is recommended that a capacitance of a 100 nF is placed near the
TCAN4550-Q1 VSUP and the VIO supply terminals. The FLTR terminal requires a minimum of 300 nF
capacitance to ground to regulate the internal digital power rail. VCCOUT needs a minimum capacitance to ground
of 10 µF at the terminal.
备注
• The capacitance values selected should take into consideration the degradation over time such
that the values do not fall below the minimum values shown
• Above is a minimum amount of capacitance but due to system considerations more may be
needed
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11 Layout
Robust and reliable bus node design often requires the use of external transient protection device in order to
protect against EFT and surge transients that may occur in industrial environments. Because ESD and transients
have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, high-frequency layout techniques must
be applied during PCB design. The family comes with high on-chip IEC ESD protection, but if higher levels of
system level immunity are desired external TVS diodes can be used. TVS diodes and bus filtering capacitors
should be placed as close to the on-board connectors as possible to prevent noisy transient events from
propagating further into the PCB and system.
11.1 Layout Guidelines
Place the protection and filtering circuitry as close to the bus connector, J1, to prevent transients, ESD and noise
from propagating onto the board. The layout example provides information on components around the device
itself. Transient voltage suppression (TVS) device can be added for extra protection, shown as D1. The
production solution can be either a bi-directional TVS diode or a varistor with ratings matching the application
requirements. This example also shows optional bus filter capacitors C10 and C11. A series common mode
choke (CMC) is placed on the CANH and CANL lines between TCAN4550-Q1 and connector J1.
Design the bus protection components in the direction of the signal path. Do not force the transient current to
divert from the signal path to reach the protection device. Use supply and ground planes to provide low
inductance.
备注
High-frequency currents follows the path of least impedance and not the path of least resistance.
Use at least two vias for supply and ground connections of bypass capacitors and protection devices to minimize
trace and via inductance.
• Bypass and bulk capacitors should be placed as close as possible to the supply terminals of transceiver,
examples are C3, C4 and C5 on the FLTR, VIO, VCCOUT, pins and C6 and C7 on the VSUP supply.
• Bus termination: this layout example shows split termination. This is where the termination is split into two
resistors, R4 and R5, with the center or split tap of the termination connected to ground via capacitor C9. Split
termination provides common mode filtering for the bus. When bus termination is placed on the board instead
of directly on the bus, additional care must be taken to ensure the terminating node is not removed from the
bus thus also removing the termination.
• As terminal 8 (nINT) and 9 (GPO2) are open drain an external resistor to VIO is required. These can have a
value between 2 kΩand 10 kΩ.
• Terminal 12 (WAKE) is a bi-directional triggered wake-up input that is usually connected to an external switch.
It should be configured as shown with a 10 nF (C8) to GND where R2 is 33 kΩand R3 is 3 kΩ.
• Terminal 15 (INH) can be left floating if not used but a 100 kΩpull-down resistor can be used to discharge
the INH to a sufficient level when the INH output is high-Z.
• Terminal 1 should have a series resistor (R8) when using a crystal oscillator. More information about sizing
this resistor can be found in the TCAN455x Clock Optimization and Design Guidelines application note.
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11.2 Layout Example
GND
Crystal
40 MHz
50 Ω
Traces for Pin 1 and 20
need to be Matched length
C1
C2
R8
GND
19
nWKRQ
GPIO1
SCLK
2
RST
FLTR
C3
GND
VIO
C4
GND
SDI
VCCOUT
C5
GND
SDO
INH
R1
GND
nCS
VIO
VSUP
C6
C7
GND
C8
R7
R6
nINT
VIO
R2
9
12
VSUP
GPO2
R3
WAKE
To Switch
Choke
R5
R4
C9
C11
C10
CANH
CANL
GND
D1
J1
图11-1. Example Layout
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
12.1.1.1 CAN Transceiver Physical Layer Standards:
• ISO 11898-2:2016: High speed medium access unit with low power mode
• ISO 8802-3: CSMA/CD –referenced for collision detection from ISO11898-2
• CAN FD 1.0 Spec and Papers
• Bosch “Configuration of CAN Bit Timing”, Paper from 6th International CAN Conference (ICC), 1999. This
is repeated a lot in the DCAN IP CAN Controller spec copied into this system spec.
• SAE J2284-2: High Speed CAN (HSC) for Vehicle Applications at 250 kbps
• SAE J2284-3: High Speed CAN (HSC) for Vehicle Applications at 500 kbps
• Bosch M_CAN Controller Area Network Revision 3.2.1.1 (3/24/2016)
12.1.1.2 EMC requirements:
• SAE J2962-2: US3 requirements for CAN Transceivers
• HW Requirements for CAN, LIN,FR V1.3:
12.1.1.3 Conformance Test requirements:
• HS_TRX_Test_Spec_V_1_0: GIFT / ICT CAN test requirements for High Speed Physical Layer
12.1.1.4 Support Documents
• “A Comprehensible Guide to Controller Area Network”, Wilfried Voss, Copperhill Media Corporation
• “CAN System Engineering: From Theory to Practical Applications”, 2nd Edition, 2013; Dr. Wolfhard
Lawrenz, Springer.
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TCAN4550RGYRQ1
TCAN4550RGYTQ1
ACTIVE
VQFN
VQFN
RGY
20
20
3000 RoHS & Green
250 RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
TCAN
4550Q1
Samples
Samples
ACTIVE
RGY
NIPDAU | SN
TCAN
4550Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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24-Apr-2023
OTHER QUALIFIED VERSIONS OF TCAN4550-Q1 :
Catalog : TCAN4550
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-May-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TCAN4550RGYRQ1
TCAN4550RGYRQ1
TCAN4550RGYTQ1
VQFN
VQFN
VQFN
RGY
RGY
RGY
20
20
20
3000
3000
250
330.0
330.0
180.0
12.4
12.4
12.4
3.8
3.71
3.8
4.8
4.71
4.8
1.18
1.1
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
1.18
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-May-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TCAN4550RGYRQ1
TCAN4550RGYRQ1
TCAN4550RGYTQ1
VQFN
VQFN
VQFN
RGY
RGY
RGY
20
20
20
3000
3000
250
367.0
367.0
213.0
367.0
367.0
191.0
38.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGY 20
3.5 x 4.5, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FGLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225264/A
www.ti.com
PACKAGE OUTLINE
RGY0020C
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.6
3.4
B
A
PIN 1 INDEX AREA
4.6
4.4
0.1 MIN
(0.05)
SECTION A-A
SCALE 30.000
SECTION A-A
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2.2 0.1
2X 1.5
SYMM
EXPOSED
THERMAL PAD
(0.2) TYP
10
11
14X 0.5
9
12
4.2 0.1
3.2 0.1
21
SYMM
2X
3.5
A
A
2
19
0.3
0.2
1
20
PIN 1 ID
(OPTIONAL)
20X
0.1
0.05
C A B
4X 0.25 0.05
0.5
0.3
20X
4223814/A 06/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGY0020C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.2)
4X (0.75)
(0.85)
SYMM
1
20
20X (0.6)
2
19
20X (0.25)
(R0.05) TYP
(1.35)
(4.2)
4X
21
SYMM
(3.2)
(4.3)
14X (0.5)
12
9
(
0.2) TYP
VIA
10
4X (0.25)
11
2X (0.75)
(3.3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223814/A 06/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGY0020C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X (0.98)
20
2X (0.25)
1
2X (0.2)
20X (0.6)
2
19
24X (0.25)
4X
(1.43)
(R0.05) TYP
21
SYMM
4X
(4.3)
(0.82)
TYP
14X (0.5)
12
9
EXPOSED METAL
TYP
10
11
4X (0.75)
(0.59) TYP
SYMM
(3.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 21
80% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223814/A 06/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
RGY0020F
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.6
3.4
A
B
PIN 1 INDEX AREA
4.6
4.4
0.1 MIN
(0.13)
A
-
A
3
0
.
0
0
0
SECTION A-A
TYPICAL
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08 C
2.2 0.1
2X 1.5
SYMM
(0.2) TYP
EXPOSED
THERMAL PAD
11
10
9
(0.16)
TYP
12
4.2 0.1
3.2 0.1
SYMM
21
2X 3.5
A
A
20X 0.5
19
2
1
20
0.5
0.3
0.3
0.2
PIN 1 ID
(45 X 0.3)
24X
20X
0.1
C A B
C
0.05
4229006/A 09/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGY0020F
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.2)
SYMM
20
SEE SOLDER MASK
DETAIL
1
20X (0.6)
24X (0.25)
19
2
20X (0.5)
(3.2)
21
SYMM
(4.3)
(4.2)
(R0.05) TYP
0.2) TYP
(1.35)
(
VIA
12
9
10
11
4X
(0.75)
(0.85)
(3.3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4229006/A 09/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGY0020F
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.59) TYP
2X (0.72)
2X (0.25)
1
20
20X (0.6)
24X (0.25)
2
19
20X (0.5)
(0.815) TYP
(4.3)
21
SYMM
4X (1.43)
(R0.05) TYP
12
9
EXPOSED METAL
TYP
10
11
4X (0.98)
4X
(0.75)
SYMM
(3.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
EXPOSED PAD 21
80% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4229006/A 09/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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