TCAN1057AVDRQ1 [TI]
TCAN1057A-Q1 and TCAN1057AV-Q1 Automotive Fault-Protected CAN FD Transceiver;型号: | TCAN1057AVDRQ1 |
厂家: | TEXAS INSTRUMENTS |
描述: | TCAN1057A-Q1 and TCAN1057AV-Q1 Automotive Fault-Protected CAN FD Transceiver |
文件: | 总39页 (文件大小:2389K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TCAN1057A-Q1, TCAN1057AV-Q1
SLLSFM8B – FEBRUARY 2021 – REVISED NOVEMBER 2021
TCAN1057A-Q1 and TCAN1057AV-Q1 Automotive Fault-Protected CAN FD
Transceiver
1 Features
3 Description
•
•
•
AEC-Q100 (Grade 1) Qualified for automotive
applications
Meets the requirements of ISO 11898-2:2016
physical layer standard
Functional Safety-Capable
– Documentation available to aid in functional
safety system design
Support of classical CAN and optimized CAN FD
performance at 2, 5, and 8 Mbps
– Short and symmetrical propagation delays for
enhanced timing margin
TCAN1057AV I/O voltage range supports 1.7 V to
5.5 V
Support for 12-V and 24-V battery applications
Receiver common mode input voltage: ±12 V
Protection features:
The TCAN1057A-Q1 and TCAN1057AV-Q1 are high
speed controller area network (CAN) transceivers
that meet the physical layer requirements of the ISO
11898-2:2016 high-speed CAN specification.
The transceivers have certified electromagnetic
compatibility (EMC) operation making it an ideal
choice for classical CAN and CAN FD networks
up to 5 megabits per second (Mbps). Upto 8
Mbps operation in simpler networks is possible
with these devices. The transceivers support two
modes of operation; normal mode and silent mode.
The transceivers also include many protection and
diagnostic features including thermal shutdown (TSD),
TXD-dominant timeout (DTO), and bus fault protection
up to ±58 V. The device has defined fail-safe behavior
in supply under-voltage or floating pin scenarios.
•
•
•
•
•
– Bus fault protection: ±58 V
– Undervoltage protection
– TXD-dominant time-out (DTO)
The transceiver features an integrated level shifter
on the VIO pin which supplies internal logic-level
translation for interfacing the transceiver I/Os directly
to 1.8-V, 2.5-V, 3.3-V, or 5-V logic level.
•
Data rates down to 9.2 kbps
– Thermal-shutdown protection (TSD)
Operating modes:
– Normal mode
– Silent mode
Optimized behavior when unpowered
•
•
Device Information
PART NUMBER
PACKAGE(1)
SOT-23 (DDF) (8)
VSON (DRB) (8)
SOIC (D) (8)
BODY SIZE (NOM)
2.90 mm x 1.60 mm
3.00 mm x 3.00 mm
4.90 mm x 3.91 mm
TCAN1057A-Q1
TCAN1057AV-Q1
– Bus and logic pins are high impedance (no load
to operating bus or application)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
– Hot-plug capable: power up/down glitch free
operation on bus and RXD output
•
•
Junction temperature from: –40°C to 150°C
Available in SOIC (8), small footprint SOT-23 (8),
and leadless VSON (8) package with improved
automated optical inspection (AOI) capability
Table 3-1. Device Comparison Table
Device number
Low voltage I/O
logic support on
Pin5
Pin8 Mode
selection
TCAN1057A-Q1
TCAN1057AV-Q1
No
Silent mode
Silent mode
2 Applications
Yes
•
Automotive and transportation
– Body control modules
VIN
VIN
VOUT
5V Voltage
Regulator
(e.g. TPSxxxx)
– Automotive gateway
– Advanced driver assistance system (ADAS)
– Infotainment
3
VDD
VCC
CANH
8
7
GPIO
S
MCU
TCAN1057AV
VIN
VOUT
1
4
TXD
RXD
CAN FD
Controller
1.8 V / 2.5
Regulator
(e.g. TPSxxxx)
V / 3.3 V
CANL
VIO GND
6
5
2
Optional:
Terminating
Node
Optional:
Filtering,
Transient and
ESD
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TCAN1057A-Q1, TCAN1057AV-Q1
SLLSFM8B – FEBRUARY 2021 – REVISED NOVEMBER 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 ESD Ratings Table — IEC Specifications ..................4
6.4 Recommended Operating Conditions ........................4
6.5 Thermal Characteristics .............................................5
6.6 Supply Characteristics ............................................... 5
6.7 Dissipation Ratings .................................................... 6
6.8 Electrical Characteristics ............................................6
6.9 Switching Characteristics ...........................................8
7 Parameter Measurement Information..........................10
8 Detailed Description......................................................13
8.1 Overview...................................................................13
8.2 Functional Block Diagram.........................................14
8.3 Feature Description...................................................14
8.4 Device Functional Modes..........................................18
9 Application Information Disclaimer.............................19
9.1 Application Information............................................. 19
9.2 Typical Application.................................................... 19
10 Power Supply Recommendations..............................22
11 Device and Documentation Support..........................24
11.1 Documentation Support.......................................... 24
11.2 Receiving Notification of Documentation Updates..24
11.3 Support Resources................................................. 24
11.4 Trademarks............................................................. 24
11.5 Electrostatic Discharge Caution..............................24
11.6 Glossary..................................................................24
12 Mechanical, Packaging, and Orderable
Information.................................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (May 2021) to Revision B (November 2021)
Page
•
Removed Product Preview from the DFF and D packages in the Device Information table.............................. 1
Changes from Revision * (February 2021) to Revision A (May 2021)
Page
•
Changed the document status from: Advanced Information to: Production data............................................... 1
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5 Pin Configuration and Functions
TXD
GND
VCC
1
2
3
4
8
7
6
5
S
TXD
GND
VCC
1
2
3
4
8
7
6
5
S
CANH
CANL
NC,VIO
CANH
CANL
NC,VIO
RXD
RXD
Not to scale
Not to scale
Figure 5-1. DDF Package, 8-Pin SOT, Top View
Figure 5-2. D Package, 8-Pin SOIC, Top View
TXD
GND
VCC
1
2
3
4
8
7
6
5
S
CANH
CANL
NC,VIO
Thermal
Pad
RXD
Not to scale
Figure 5-3. DRB Package, 8-Pin VSON, Top View
Table 5-1. Pin Functions
Pins
Type
Description
Name
TXD
GND
VCC
No.
1
Digital Input CAN transmit data input, integrated pull-up
2
GND
Ground connection
5-V supply voltage
3
Supply
RXD
NC
4
Digital Output CAN receive data output, tri-state when powered off
—
No connect (not internally connected); devices without VIO
I/O supply voltage
5
VIO
Supply
Bus IO
Bus IO
CANL
CANH
S
6
7
8
Low-level CAN bus input/output line
High-level CAN bus input/output line
Digital Input Silent mode control input, integrated pull-up
Connect the thermal pad to any internal PCB ground plane using multiple vias for optimal
thermal performance.
Thermal Pad (VSON only)
—
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6 Specifications
6.1 Absolute Maximum Ratings
(1) (2)
MIN
–0.3
–0.3
–58
–45
–0.3
–0.3
–8
MAX
UNIT
V
VCC
Supply voltage
6
6
VIO
Supply voltage I/O level shifter
CAN Bus I/O voltage
V
VBUS
VDIFF
VLogic_Input
VRXD
IO(RXD)
TJ
58
45
6
V
Max differential voltage between CANH and CANL
Logic input terminal voltage
RXD output terminal voltage range
RXD output current
V
V
6
V
8
mA
°C
°C
Junction temperature
–40
–65
165
150
TSTG
Storage temperature
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values, except differential I/O bus voltages, are with respect to ground terminal.
6.2 ESD Ratings
VALUE
UNIT
HBM classification level 3A for
all pins
±4000
V
Human-body model (HBM), per AEC Q100-002(1)
HBM classification level 3B for
global pins CANH and CANL
with respect to GND
VESD
Electrostatic discharge
±10000
±750
V
V
Charged-device model (CDM), per AEC Q100-011
CDM classification level C5 for all pins
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 ESD Ratings Table — IEC Specifications
VALUE
UNIT
Unpowered contact discharge
per ISO10605 (1)
±8000
±8000
V
V
V
SAE J2962-2 per ISO 10605
VESD System level Electrostatic discharge(1)
Powered Contact Discharge
(2)
SAE J2962-2 per ISO 10605
Powered Air Discharge (2)
±15000
CAN bus terminals (CANH and CANL) to GND
Pulse 1
–100
75
V
V
V
V
V
Pulse 2a
Transient voltage per ISO 7637-2(3)
VTran
Pulse 3a
–150
100
±30
Pulse 3b
Transient voltage per ISO 7637-3(4)
DCC slow transient pulse
(1) Tested according to IEC 62228-3:2019 CAN Transceivers.
(2) Results given here are specific to the SAE J2962-2 Communication Transceivers Qualification Requirements - CAN. Testing performed
by OEM approved independent third party, EMC report available upon request.
(3) Tested according to IEC 62228-3:2019 CAN Transceivers.
(4) Tested according to SAE J2962-2.
6.4 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
V
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6.4 Recommended Operating Conditions (continued)
MIN
1.7
NOM
MAX
UNIT
V
VIO
Supply voltage for I/O level shifter
5.5
IOH(RXD)
IOL(RXD)
IOH(RXD)
IOL(RXD)
TJ
RXD terminal high-level output current, Devices with VIO
RXD terminal low-level output current, Devices with VIO
RXD terminal high-level output current, Devices without VIO
RXD terminal low-level output current, Devices without VIO
Operating junction temperature
–1.5
mA
mA
mA
mA
℃
1.5
–2
2
-40
150
6.5 Thermal Characteristics
TCAN1057Ax-Q1
DDF (SOT)
THERMAL METRIC(1)
UNIT
D (SOIC)
DRB (VSON)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
127.5
67.6
70.9
19.3
70.2
--
122
63
55.2
℃/W
℃/W
℃/W
℃/W
℃/W
℃/W
RθJC(top)
RθJB
62.4
27.5
2.3
42.4
2.4
42.2
--
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ΨJB
27.4
11.5
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Supply Characteristics
Over recommended operating conditions with TJ = -40℃ to 150℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TXD = 0 V, S = 0 V, RL = 60 Ω, CL = open;
See Figure 7-1
45
70
mA
Dominant
Recessive
TXD = 0 V, S = 0 V, RL = 50 Ω, CL = open;
See Figure 7-1
49
80
mA
mA
Supply current
Normal mode
TXD = VCC or VIO, S = 0 V, RL = 50 Ω, CL
= open;
4.5
7.5
ICC
See Figure 7-1
TXD = 0 V, S = 0 V, CANH = CANL = ±25
V, RL = open, CL = open;
See Figure 7-1
Dominant with
bus fault
130
2.1
mA
mA
TXD = S = VCC or VIO, RL = 50 Ω, CL
=
Supply current
Silent mode
open;
See Figure 7-1
S = 0 V, TXD = 0 V
RXD floating
Dominant
Recessive
125
25
300
48
µA
µA
I/O supply current
Normal mode, Devices
with VIO
IIO
TXD = VIO , S = 0 V
RXD floating
Rising undervoltage detection on VCC for protected mode
Falling undervoltage detection on VCC for protected mode
4.2
4
4.4
V
V
UVCC
3.5
1.4
4.25
VHYS(UVCC) Hysteresis voltage on UVCC
Rising undervoltage detection on VIO (Devices with VIO
Falling undervoltage detection on VIO (Devices with VIO
200
1.56
1.51
40
mV
V
)
1.65
1.59
UVVIO
)
V
VHYS(UVIO) Hysteresis voltage on UVIO
mV
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6.7 Dissipation Ratings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC = 5 V, VIO = 1.8 V, TJ= 27°C, RL = 60Ω,
TXD input = 250 kHz 50% duty cycle square
wave, CL_RXD = 15 pF
95
mW
VCC = 5 V, VIO = 3.3 V, TJ= 27°C, RL = 60Ω,
TXD input = 250 kHz 50% duty cycle square
wave, CL_RXD = 15 pF
95
95
mW
mW
mW
mW
VCC = 5 V, VIO = 5 V, TJ= 27°C, RL = 60Ω, TXD
input = 250 kHz 50% duty cycle square wave,
CL_RXD = 15 pF
Average power dissipation
Normal mode
PD
VCC = 5.5 V, VIO = 1.8 V, TA= 150°C, RL = 60Ω,
TXD input = 2.5 MHz 50% duty cycle square
wave, CL_RXD = 15 pF
120
120
120
VCC = 5.5 V, VIO = 3.3 V, TA= 150°C, RL = 60Ω,
TXD input = 2.5 MHz 50% duty cycle square
wave, CL_RXD = 15 pF
VCC = 5.5 V, VIO = 5 V, TA= 150°C, RL = 60Ω,
TXD input = 2.5 MHz 50% duty cycle square
wave, CL_RXD = 15 pF
mW
°C
TTSD
Thermal shutdown temperature
175
195
12
210
TTSD(HYS) Thermal shutdown hysteresis
6.8 Electrical Characteristics
Over recommended operating conditions with TJ = -40℃ to 150℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Driver Electrical Characteristics
CANH
CANL
S = 0 V, TXD = 0 V
50 Ω ≤ RL ≤ 65 Ω, CL = open, RCM = open;
See Figure 7-2
2.75
0.5
4.5
V
V
Dominant output voltage
Normal mode
VO(DOM)
2.25
S = 0 V, TXD = VIO
CANH and CANL RL = open (no load), RCM = open
See Figure 7-2
Recessive output voltage
Normal or silent mode
VO(REC)
2
0.5 VCC
3
V
S = 0 V, TXD = 250 kHz, 1 MHz, 2.5 MHz
RL = 60 Ω, CSPLIT = 4.7 nF, CL = open,
RCM = open;
Driver symmetry
(VO(CANH) + VO(CANL))/VCC
VSYM
0.9
1.1 V/V
400 mV
See Figure 7-2 and Figure 9-2
S = 0 V
RL = 60 Ω, CL = open;
See Figure 7-2
DC output symmetry
(VCC - VO(CANH) - VO(CANL)
VSYM_DC
–400
1.5
)
S = 0 V, TXD = 0 V
50 Ω ≤ RL ≤ 65 Ω, CL = open;
See Figure 7-2
3
3.3
5
V
V
V
Differential output voltage
Normal mode
Dominant
S = 0 V, TXD = 0 V
45 Ω ≤ RL ≤ 70 Ω, CL = open;
See Figure 7-2
VOD(DOM)
CANH - CANL
1.4
S = 0 V, TXD = 0 V
RL = 2240 Ω, CL = open;
See Figure 7-2
1.5
S = 0 V, TXD = VIO
RL = 60 Ω, CL = open;
See Figure 7-2
–120
–50
–115
12 mV
50 mV
mA
Differential output voltage
Normal mode
Recessive
VOD(REC)
CANH - CANL
S = 0 V, TXD = VIO
RL = open, CL = open;
See Figure 7-2
S = 0 V, TXD = 0 V
V(CANH) = -15 V to 40 V, CANL = open;
See Figure 7-7
Short-circuit steady-state output current,
dominant
Normal mode
IOS(SS_DOM)
S = 0 V, TXD = 0 V
V(CAN_L) = -15 V to 40 V, CANH = open;
See Figure 7-7
115 mA
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6.8 Electrical Characteristics (continued)
Over recommended operating conditions with TJ = -40℃ to 150℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
S = 0 V, TXD = VIO
–27 V ≤ VBUS ≤ 32 V, where VBUS = CANH
= CANL;
See Figure 7-7
Short-circuit steady-state output current,
recessive
Normal mode
IOS(SS_REC)
–5
5
mA
Receiver Electrical Characteristics
Input threshold voltage
Normal and silent mode
S = 0 V, -12 V ≤ VCM ≤ 12 V;
See Figure 7-3 and Table 8-6
VIT
500
0.9
-4
900 mV
Dominant state differential input voltage range
Normal and silent mode
S = 0 V, -12 V ≤ VCM ≤ 12 V;
See Figure 7-3 and Table 8-6
VDOM
VREC
VHYS
VCM
9
V
V
Recessive state differential input voltage range
Normal and silent mode
S = 0 V, -12 V ≤ VCM ≤ 12 V;
See Figure 7-3 and Table 8-6
0.5
Hysteresis voltage for input threshold
Normal mode
S = 0 V, -12 V ≤ VCM ≤ 12 V;
See Figure 7-3 and Table 8-6
115
mV
Common-mode range
Normal and silent mode
See Figure 7-3 and Table 8-6
–12
12
5
V
ILKG(IOFF)
CI
Unpowered bus input leakage current
Input capacitance to ground (CANH or CANL)
Differential input capacitance
CANH = CANL = 5 V, VCC = VIO = GND
µA
20 pF
10 pF
90 kΩ
(1)
TXD = VIO
CID
RID
Differential input resistance
40
20
TXD = VIO (1), S = 0 V, -12 V ≤ VCM ≤ 12 V
Single-ended input resistance
(CANH or CANL)
RIN
45 kΩ
Input resistance matching
[1 – (RIN(CANH) / RIN(CANL))] × 100 %
RIN(M)
V(CAN_H) = V(CAN_L) = 5 V
–1
1
%
TXD Terminal (CAN Transmit Data Input)
VIH
VIH
VIL
VIL
IIH
High-level input voltage
High-level input voltage
Low-level input voltage
Low-level input voltage
High-level input leakage current
Devices without VIO
Devices with VIO
0.7 VCC
0.7 VIO
V
V
Devices without VIO
Devices with VIO
0.3 VCC
0.3 VIO
1
V
V
TXD = VCC = VIO = 5.5 V
–2.5
0
µA
TXD = 0 V
VCC= VIO = 5.5 V
IIL
Low-level input leakage current
–200
-100
–20 µA
TXD = 5.5 V
VCC= VIO = 0 V
ILKG(OFF)
CI
Unpowered leakage current
Input capacitance
–1
0
5
1
µA
pF
VIN = 0.4×sin(2×π×2×106×t)+2.5 V
RXD Terminal (CAN Receive Data Output)
IO = –2 mA
VOH
VOH
VOL
High-level output voltage
High-level output voltage
Low-level output voltage
Devices without VIO
See Figure 7-3
;
;
0.8 VCC
0.8 VIO
V
V
V
IO = –1.5 mA
Devices with VIO
See Figure 7-3
;
IO = 2mA
Devices without VIO
See Figure 7-3
0.2 VCC
IO = 1.5mA
VOL
Low-level output voltage
Devices with VIO
See Figure 7-3
;
0.2 VIO
V
RXD = 5.5 V
VCC = VIO = 0 V
ILKG(OFF)
Unpowered leakage current
–1
0
1
µA
S Terminal (Silent Mode Input)
VIH
VIH
VIL
VIL
IIH
High-level input voltage
Devices without VIO
Devices with VIO
Devices without VIO
Devices with VIO
0.7 VCC
0.7 VIO
V
V
High-level input voltage
Low-level input voltage
0.3 VCC
0.3 VIO
2
V
Low-level input voltage
V
High-level input leakage current
VCC = VIO = S = 5.5 V
–2
µA
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6.8 Electrical Characteristics (continued)
Over recommended operating conditions with TJ = -40℃ to 150℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
S = 0 V
VCC = VIO = 5.5 V,
IIL
Low-level input leakage current
–20
–2 µA
S = 5.5V
VCC = VIO = 0 V
ILKG(OFF)
Unpowered leakage current
–1
0
1
µA
(1) VIO = VCC in non-V variants of device
6.9 Switching Characteristics
Over recommended operating conditions with TJ = -40℃ to 150℃ (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Device Switching Characteristics
Total loop delay
Driver input (TXD) to receiver output (RXD),
recessive to dominant
S = 0 V, VIO = 2.8 V to 5.5 V
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF;
See Figure 7-4
tPROP(LOOP1)
tPROP(LOOP1)
tPROP(LOOP2)
125
165
150
180
210
255
210
ns
ns
ns
Total loop delay
Driver input (TXD) to receiver output (RXD),
recessive to dominant
S = 0 V, VIO = 1.7 V
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF;
See Figure 7-4
Total loop delay
Driver input (TXD) to receiver output (RXD),
dominant to recessive
S = 0 V, VIO = 2.8 V to 5.5 V
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF;
See Figure 7-4
Total loop delay
Driver input (TXD) to receiver output (RXD),
dominant to recessive
S = 0 V, VIO = 1.7 V
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF;
See Figure 7-4
tPROP(LOOP2)
255
20
ns
µs
Mode change time, from normal to standby or from
standby to normal
tMODE
See Figure 7-5
Driver Switching Characteristics
Propagation delay time, high TXD to driver
tpHR
80
70
ns
ns
recessive (dominant to recessive)
Propagation delay time, low TXD to driver dominant
(recessive to dominant)
tpLD
S = 0 V
RL = 60 Ω, CL = 100 pF;
See Figure 7-2
tsk(p)
tR
Pulse skew (|tpHR - tpLD|)
14
25
50
ns
ns
ns
Differential output signal rise time
Differential output signal fall time
tF
S = 0 V
tTXD_DTO
Dominant timeout
RL = 60 Ω, CL = 100 pF;
See Figure 7-6
1.2
4.0
ms
Receiver Switching Characteristics
Propagation delay time, bus recessive input to high
tpRH
81
66
ns
ns
output (dominant to recessive)
S = 0 V
CL(RXD) = 15 pF;
See Figure 7-3
Propagation delay time, bus dominant input to low
output (recessive to dominant)
tpDL
tR
tF
RXD output signal rise time
RXD output signal fall time
10
10
ns
ns
FD Timing Characteristics
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6.9 Switching Characteristics (continued)
Over recommended operating conditions with TJ = -40℃ to 150℃ (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Bit time on CAN bus output pins
tBIT(TXD) = 500 ns
450
525
ns
Bit time on CAN bus output pins
tBIT(TXD) = 200 ns
tBIT(BUS)
tBIT(RXD)
ΔtREC
160
85
205
130
540
210
135
20
ns
ns
ns
ns
ns
ns
ns
ns
Bit time on CAN bus output pins
tBIT(TXD) = 125 ns(1)
Bit time on RXD output pins
tBIT(TXD) = 500 ns
410
130
75
S = 0 V
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF
Bit time on RXD output pins
tBIT(TXD) = 200 ns
ΔtREC = tBIT(RXD) - tBIT(BUS)
See Figure 7-4
;
Bit time on RXD output pins
tBIT(TXD) = 125 ns(1)
Receiver timing symmetry
tBIT(TXD) = 500 ns
-50
-40
-40
Receiver timing symmetry
tBIT(TXD) = 200 ns
10
Receiver timing symmetry
tBIT(TXD) = 125 ns(1)
10
(1) Measured during characterization and not an ISO 11898-2:2016 parameter.
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7 Parameter Measurement Information
CANH
TXD
RL
CL
CANL
Figure 7-1. ICC Test Circuit
RCM
CANH
50%
50%
TXD
TXD
RL
CL
VOD
VCM
VCC
VO(CANH)
tpLD
tpHR
90%
10%
0V
CANL
RCM
0.9V
VO(CANL)
VOD
0.5V
tR
tF
Figure 7-2. Driver Test Circuit and Measurement
CANH
1.5V
0.9V
VID
IO
RXD
0.5V
0V
VID
tpDL
tpRH
VOH
CL_RXD
VO
CANL
90%
VO(RXD)
50%
10%
VOL
tF
tR
Figure 7-3. Receiver Test Circuit and Measurement
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TXD
VI
70%
tLOOP1
30%
30%
CANH
0 V
TXD
STB
VI
RL
CL
tBIT(TXD)
5 x tBIT(TXD)
CANL
tBIT(BUS)
0 V
900 mV
RXD
+
500 mV
VDIFF
VO
CL_RXD
œ
RXD
VOH
70%
30%
VOL
tBIT(RXD)
tLOOP2
Figure 7-4. Transmitter and Receiver Timing Test Circuit and Measurement
CANH
VIH
TXD
CL
0V
RL
S
50%
CANL
S
VI
0V
tMODE
RXD
VOH
VO
CL_RXD
RXD
50%
VOL
Figure 7-5. tMODE Test Circuit and Measurement
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VIH
CANH
TXD
TXD
0V
RL
CL
VOD
VOD(D)
CANL
0.9V
VOD
0.5V
0V
tTXD_DTO
Figure 7-6. TXD Dominant Timeout Test Circuit and Measurement
200 ꢀs
IOS
CANH
TXD
VBUS
IOS
CANL
VBUS
VBUS
0V
or
0V
VBUS
VBUS
Figure 7-7. Driver Short-Circuit Current Test and Measurement
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8 Detailed Description
8.1 Overview
The TCAN1057A(V)-Q1 devices meet or exceed the specifications of the ISO 11898-2:2016 high speed CAN
(Controller Area Network) physical layer standard. The device has been certified to the requirements of ISO
11898-2:2016 physical layer requirements according to the GIFT/ICT high speed CAN test specification. The
transceiver provides a number of different protection features making it ideal for the stringent automotive system
requirements while also supporting CAN FD data rates up to 8 Mbps.
The devices support the following CAN standards:
•
CAN transceiver physical layer standards:
– ISO 11898-2:2016 High speed medium access unit
– ISO 11898-5:2007 High speed medium access unit with low-power mode
– SAE J2284-1: High Speed CAN (HSC) for Vehicle Applications at 125 kbps
– SAE J2284-2: High Speed CAN (HSC) for Vehicle Applications at 250 kbps
– SAE J2284-3: High Speed CAN (HSC) for Vehicle Applications at 500 kbps
– SAE J2284-4: High-Speed CAN (HSC) for Vehicle Applications at 500 kbps with CAN FD Data at 2 Mbps
– SAE J2284-5: High-Speed CAN (HSC) for Vehicle Applications at 500 kbps with CAN FD Data at 5 Mbps
•
•
EMC requirements:
– IEC 62228-3 EMC evaluation of transceivers - CAN transceivers
– SAE J2962-2 Communication Transceivers Qualification Requirements – CAN
Conformance Test requirements:
– ISO 16845-2 Road vehicles – Controller area network (CAN) conformance test plan Part 2: High-speed
medium access unit conformance test plan
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8.2 Functional Block Diagram
VCC
3
NC or VIO
5
VCC or VIO
7
6
CANH
CANL
TSD
Dominant
time-out
TXD
1
VCC or VIO
S
8
Mode Select
UVP
VCC or VIO
4
Logic Output
RXD
2
GND
8.3 Feature Description
8.3.1 Pin Description
8.3.1.1 TXD
The TXD input is a logic-level signal, referenced to either VCC or VIO from a CAN controller to the transceivers.
8.3.1.2 GND
GND is the ground pin of the transceiver, it must be connected to the PCB ground.
8.3.1.3 VCC
VCC provides the 5-V power supply to the CAN transceiver.
8.3.1.4 RXD
The RXD output is a logic-level signal, referenced to either VCC or VIO, from the transceivers to the CAN
controller. RXD is only driven once VIO is present.
8.3.1.5 VIO
The VIO pin is the input source for the integrated level shifter which provides the transceiver I/O voltage. The VIO
pin should be connected to the controller's I/O voltage source.
8.3.1.6 CANH and CANL
These are the CAN high and CAN low differential bus pins. These pins are connected to the CAN transmitter
and receiver internally.
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8.3.1.7 S (Silent)
The S pin is an input pin used for silent mode control of the transceiver. The S pin can be supplied from either
the controller or from a static system voltage source. If normal mode is the only intended mode of operation than
the S pin can be tied directly to system GND using a pull-down resistor. If silent mode is the only intended mode
of operation than the S pin can be tied directly to a static system voltage source using a pull-up resistor.
8.3.2 CAN Bus States
The CAN bus has two logical states during operation: recessive and dominant. See Figure 8-1.
A dominant bus state occurs when the bus is driven differentially and corresponds to a logic low on the TXD and
RXD pins. A recessive bus state occurs when the bus is biased to VCC/2 via the high-resistance internal input
resistors RIN) of the receiver and corresponds to a logic high on the TXD and RXD pins.
A dominant state overwrites the recessive state during arbitration. Multiple CAN nodes may be transmitting a
dominant bit at the same time during arbitration, and in this case the differential voltage of the bus is greater than
the differential voltage of a single driver.
Normal Mode
Silent Mode
CANH
Vdiff
Vdiff
CANL
Recessive
Dominant
Recessive
Time, t
Figure 8-1. Bus States
8.3.3 TXD Dominant Timeout (DTO)
During normal mode, the only mode where the CAN driver is active, the TXD DTO circuit prevents the local node
from blocking network communication in the event of a hardware or software failure where TXD is held dominant
longer than the timeout period tTXD_DTO. The TXD DTO circuit is triggered by a falling edge on TXD. If no rising
edge is seen before the timeout period of the circuit, tTXD_DTO, the CAN driver is disabled. This frees the bus for
communication between other nodes on the network. The CAN driver is reactivated when a recessive signal is
seen on the TXD pin, thus clearing the dominant time out. The receiver remains active and biased to VCC/2 and
the RXD output reflects the activity on the CAN bus during the TXD DTO fault.
The minimum dominant TXD time allowed by the TXD DTO circuit limits the minimum possible transmitted data
rate of the device. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the
worst case, where five successive dominant bits are followed immediately by an error frame. The minimum
transmitted data rate may be calculated using Equation 1.
Minimum Data Rate = 11 bits / tTXD_DTO = 11 bits / 1.2 ms = 9.2 kbps
(1)
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Fault is repaired & transmission capability
restored
TXD fault stuck dominant: example PCB failure or bad software
tTXD_DTO
TXD (driver)
Driver disabled freeing bus for other nodes
Normal CAN communication
Bus would be —stuck dominant“ blocking communication for the whole network but TXD DTO
prevents this and frees the bus for communication after the time tTXD_DTO
.
CAN Bus Signal
tTXD_DTO
Communication from other bus node(s)
Communication from repaired node
RXD (receiver)
Communication from local node
Communication from other bus node(s)
Communication from repaired local node
Figure 8-2. Example Timing Diagram for TXD Dominant Timeout
8.3.4 CAN Bus short-circuit current limiting
The device has several protection features that limit the short-circuit current when a CAN bus line is shorted.
These include CAN driver current limiting in the dominant and recessive states and TXD dominant state timeout
which prevents permanently having the higher short-circuit current of a dominant state in case of a system fault.
During CAN communication the bus switches between the dominant and recessive states, thus the short-circuit
current may be viewed as either the current during each bus state or as a DC average current. When selecting
termination resistors or a common mode choke for the CAN design the average power rating, IOS(AVG), should
be used. The percentage dominant is limited by the TXD DTO and the CAN protocol which has forced state
changes and recessive bits due to bit stuffing, control fields, and interframe space. These ensure there is a
minimum amount of recessive time on the bus even if the data field contains a high percentage of dominant bits.
The average short-circuit current of the bus depends on the ratio of recessive to dominant bits and their
respective short-circuit currents. The average short-circuit current may be calculated using Equation 2.
IOS(AVG) = % Transmit x [(% REC_Bits x IOS(SS)_REC) + (% DOM_Bits x IOS(SS)_DOM)] + [% Receive x IOS(SS)_REC
]
(2)
Where:
•
•
•
•
•
•
•
IOS(AVG) is the average short-circuit current
% Transmit is the percentage the node is transmitting CAN messages
% Receive is the percentage the node is receiving CAN messages
% REC_Bits is the percentage of recessive bits in the transmitted CAN messages
% DOM_Bits is the percentage of dominant bits in the transmitted CAN messages
IOS(SS)_REC is the recessive steady state short-circuit current
IOS(SS)_DOM is the dominant steady state short-circuit current
This short-circuit current and the possible fault cases of the network should be taken into consideration when
sizing the power supply used to generate the transceivers VCC supply.
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8.3.5 Thermal Shutdown (TSD)
If the junction temperature of the device exceeds the thermal shutdown threshold, TTSD, the device turns off the
CAN driver circuitry and blocks the TXD to bus transmission path. The shutdown condition is cleared when the
junction temperature of the device drops below TTSD. The CAN bus pins are biased to VCC/2 during a TSD fault
and the receiver to RXD path remains operational. The device TSD circuit includes hysteresis which prevents
the CAN driver output from oscillating during a TSD fault.
8.3.6 Undervoltage Lockout
The supply pins, VCC and VIO, have undervoltage detection that places the device into a protected state. This
protects the bus during an undervoltage event on either supply pin.
Table 8-1. Undervoltage Lockout - TCAN1057A-Q1
VCC
DEVICE STATE
BUS
RXD PIN
> UVVCC
Normal
Per TXD
Mirrors bus
High impedance
< UVVCC
Protected
High impedance
Weak pull-down to ground(1)
(1) VCC = GND, see ILKG(OFF)
Table 8-2. VIO Undervoltage Lockout - TCAN1057AV-Q1
VCC
VIO
DEVICE STATE
BUS
RXD PIN
> UVVCC
> UVVIO
Normal
Per TXD
Mirrors bus
S = VIO: Silent mode
S = GND: Protected mode
Protected
< UVVCC
> UVVIO
Recessive
High impedance
Weak pull-down to ground(1)
> UVVCC
< UVVCC
< UVVIO
< UVVIO
High impedance
High impedance
Protected
(1) VCC = GND, see ILKG(OFF)
Once the undervoltage condition is cleared and tMODE has expired the device transitions to normal mode and the
host controller can send and receive CAN traffic again.
8.3.7 Unpowered Device
The device is designed to be an ideal passive or no load to the CAN bus if the device is unpowered. The bus
pins were designed to have low leakage currents when the device is unpowered, so they do not load the bus.
This is critical if some nodes of the network are unpowered while the rest of the of network remains operational.
The logic pins also have low leakage currents when the device is unpowered, so they do not load other circuits
which may remain powered.
8.3.8 Floating pins
The device has internal pull-ups on critical pins which place the device into known states if the pin floats. This
internal bias should not be relied upon by design though, especially in noisy environments, but instead should be
considered a failsafe protection feature.
When a CAN controller supporting open-drain outputs is used an adequate external pull-up resistor must be
chosen. This ensures that the TXD output of the CAN controller maintains acceptable bit time to the input of the
CAN transceiver. See Table 8-3 for details on pin bias conditions.
Table 8-3. Pin Bias
Pin
Pull-up or Pull-down
Comment
Weakly biases TXD toward recessive to prevent bus blockage or
TXD DTO triggering
TXD
Pull-up
Weakly biases S towards low-power silent mode to prevent
excessive system power
S
Pull-up
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8.4 Device Functional Modes
8.4.1 Operating Modes
The device has two main operating modes; normal mode and silent mode. Operating mode selection is made by
applying a high or low level to the S pin.
Table 8-4. Operating Modes
S
Device Mode
Silent mode
Normal Mode
Driver
Disabled
Enabled
Receiver
Enabled
Enabled
RXD Pin
High
Low
Mirrors bus state
8.4.2 Normal Mode
This is the normal operating mode of the device. The CAN driver and receiver are fully operational and CAN
communication is bi-directional. The driver is translating a digital input on the TXD input to a differential output
on the CANH and CANL bus pins. The receiver is translating the differential signal from CANH and CANL to a
digital output on the RXD output.
8.4.3 Silent Mode
In silent mode the CAN driver is disabled and the high-speed CAN receiver is enabled. CAN communication is
unidirectional into the device where the receiver is translating the differential signal from CANH and CANL to a
digital output on RXD. The power consumption of the TCAN1057A(V)-Q1 is reduced in silent mode due to the
CAN driver being disabled.
8.4.4 Driver and Receiver Function
The digital input and output levels for the device are CMOS levels with respect to either VCC or VIO.
Table 8-5. Driver Function Table
Bus Outputs
Device Mode
TXD Input(1)
Driven Bus State(2)
CANH
High
CANL
Low
Low
High or open
X
Dominant
Normal
Silent
High impedance
High impedance
High impedance
High impedance
Biased recessive
Biased recessive
(1) X = irrelevant
(2) For bus state see Figure 8-1
Table 8-6. Receiver Function Table Normal and Silent Mode
CAN Differential Inputs
VID = VCANH – VCANL
Device Mode
Bus State
RXD Pin
VID ≥ 0.9 V
0.5 V < VID < 0.9 V
VID ≤ 0.5 V
Dominant
Undefined
Recessive
Open
Low
Undefined
High
Normal or Silent
Any
Open (VID ≈ 0 V)
High
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9 Application Information Disclaimer
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
9.2 Typical Application
Figure 9-1 shows a typical configuration for 5 V system using the device. The bus termination is shown for
illustrative purposes.
VOUT
VIN
VIN
5V Voltage
Regulator
(e.g. TPSxxxx)
3
VDD
VCC
CANH
8
7
GPIO
S
MCU
TCAN1057A
1
4
TXD
RXD
CAN FD
Controller
CANL
6
NC GND
5
2
Optional:
Terminating
Node
Optional:
Filtering,
Transient and
ESD
Figure 9-1. Transceiver Application Using 5 V I/O Connections
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9.2.1 Design Requirements
9.2.1.1 CAN Termination
Termination may be a single 120-Ω resistor at each end of the bus, either on the cable or in a terminating node.
If filtering and stabilization of the common-mode voltage of the bus is desired then split termination may be used,
see Figure 9-2. Split termination improves the electromagnetic emissions behavior of the network by filtering
higher-frequency common-mode noise that may be present on the differential signal lines.
Standard Termination
Split Termination
CANH
CANH
RTERM/2
RTERM
TCAN Transceiver
TCAN Transceiver
CSPLIT
RTERM/2
CANL
CANL
Figure 9-2. CAN Bus Termination Concepts
9.2.2 Detailed Design Procedures
9.2.2.1 Bus Loading, Length and Number of Nodes
A typical CAN application may have a maximum bus length of 40 meters and maximum stub length of 0.3
meters. However, with careful design, users can have longer cables, longer stub lengths, and many more nodes
to a bus. A high number of nodes requires a transceiver with high input impedance such as the TCAN1057A(V)-
Q1.
Many CAN organizations and standards have scaled the use of CAN for applications outside the original ISO
11898-2 standard. They made system level trade off decisions for data rate, cable length, and parasitic loading
of the bus. Examples of these CAN systems level specifications are ARINC 825, CANopen, DeviceNet, SAE
J2284, SAE J1939, and NMEA 2000.
A CAN network system design is a series of tradeoffs. In the ISO 11898-2:2016 specification the driver
differential output is specified with a bus load that can range from 50 Ω to 65 Ω where the differential output
must be greater than 1.5 V. The TCAN1057A(V)-Q1 family is specified to meet the 1.5-V requirement down
to 50 Ω and is specified to meet 1.4-V differential output at 45Ω bus load. The differential input resistance
of the transceiver is a minimum of 40 kΩ. If 100 transceivers are in parallel on a bus, this is equivalent to
a 400-Ω differential load in parallel with the nominal 60 Ω bus termination which gives a total bus load of
approximately 52 Ω. Therefore, the TCAN1057A(V)-Q1 family theoretically supports over 100 transceivers on a
single bus segment. However, for a CAN network design margin must be given for signal loss across the system
and cabling, parasitic loadings, timing, network imbalances, ground offsets and signal integrity thus a practical
maximum number of nodes is often lower. Bus length may also be extended beyond 40 meters by careful
system design and data rate tradeoffs. For example, CANopen network design guidelines allow the network to
be up to 1 km with changes in the termination resistance, cabling, less than 64 nodes and significantly lowered
data rate.
This flexibility in CAN network design is one of the key strengths of the various extensions and additional
standards that have been built on the original ISO 11898-2 CAN standard. However, when using this flexibility
the CAN network system designer must take the responsibility of good network design to ensure robust network
operation.
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Node 1
Node 2
Node 3
Node n
(with termination)
System Controller
System Controller
System Controller
System Controller
CAN FD
Controller
CAN FD
Controller
CAN FD
Controller
CAN FD
Controller
TCAN1043-Q1
RTERM
TCAN1044A-Q1
TCAN1057AV-Q1
TCAN1057A-Q1
Figure 9-3. Typical CAN Bus
9.2.3 Application Curves
VCC = 5 V
VIO = 3.3 V
RL = 60 Ω
VCC = 5 V
VIO = 3.3 V
RL = 60 Ω
Figure 9-4. tPROP(LOOP1)
Figure 9-5. tPROP(LOOP2)
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9.2.4 System Examples
Figure 9-6 shows a typical configuration for 1.8 V, 2.5 V, or 3.3 V systems using the TCAN1057AV. The bus
termination is shown for illustrative purposes.
VIN
VIN
VOUT
5V Voltage
Regulator
(e.g. TPSxxxx)
3
VDD
VCC
CANH
8
7
GPIO
S
MCU
TCAN1057AV
VIN
VOUT
1
4
TXD
RXD
CAN FD
Controller
1.8 V / 2.5 V / 3.3 V
Regulator
(e.g. TPSxxxx)
CANL
VIO GND
6
5
2
Optional:
Terminating
Node
Optional:
Filtering,
Transient and
ESD
Figure 9-6. Typical Transceiver Application Using 1.8 V, 2.5 V, 3.3 V IO Connections
10 Power Supply Recommendations
The TCAN1057A transceiver is designed to operate with a main VCC input voltage supply range between 4.5 V
and 5.5 V. The TCAN1057AV implements an I/O level shifting supply input, VIO, designed for a range between
1.7 V and 5.5 V. Both supply inputs must be well regulated. A decoupling capacitance, typically 100 nF, should
be placed near the CAN transceiver's main VCC supply pin in addition to bypass capacitors. A decoupling
capacitor, typically 100 nF, should be placed near the CAN transceiver's VIO supply pin in addition to bypass
capacitors.
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Layout
Robust and reliable CAN node design may require special layout techniques depending on the application
and automotive design requirements. Since transient disturbances have high frequency content and a wide
bandwidth, high-frequency layout techniques should be applied during PCB design.
11.1 Layout Guidelines
•
Place the protection and filtering circuitry close to the bus connector, J1, to prevent transients, ESD, and
noise from propagating onto the board. This layout example shows a optional transient voltage suppression
(TVS) diode, D1, which may be implemented if the system-level requirements exceed the specified rating of
the transceiver. This example also shows optional bus filter capacitors C4 and C5.
Design the bus protection components in the direction of the signal path. Do not force the transient current to
divert from the signal path to reach the protection device.
•
•
•
Decoupling capacitors should be placed as close as possible to the supply pins VCC and VIO of transceiver.
Use at least two vias for supply and ground connections of bypass capacitors and protection devices to
minimize trace and via inductance.
Note
High frequency current follows the path of least impedance and not the path of least resistance.
•
This layout example shows how split termination could be implemented on the CAN node. The termination
is split into two resistors, R4 and R5, with the center or split tap of the termination connected to ground
via capacitor C3. Split termination provides common-mode filtering for the bus. See CAN Termination, CAN
Bus Short Circuit Current Limiting, and Equation 2 for information on termination concepts and power ratings
needed for the termination resistor(s).
11.2 Layout Example
S
R1
TXD
C4
R4
R5
L1(optional)
R2
GND
CANH
CANL
VIO
GND
C3
GND
C1
D1
J1
VCC
VCC
R3
RXD
µC V
C2
C5
Figure 11-1. Layout Example
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: TCAN1057A-Q1 TCAN1057AV-Q1
TCAN1057A-Q1, TCAN1057AV-Q1
SLLSFM8B – FEBRUARY 2021 – REVISED NOVEMBER 2021
www.ti.com
11 Device and Documentation Support
11.1 Documentation Support
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
24
Submit Document Feedback
Product Folder Links: TCAN1057A-Q1 TCAN1057AV-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
12-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TCAN1057ADDFRQ1
TCAN1057ADRBRQ1
TCAN1057ADRQ1
ACTIVE SOT-23-THIN
DDF
DRB
D
8
8
8
8
8
8
3000 RoHS & Green
3000 RoHS & Green
2500 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
2500 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
2HEF
ACTIVE
ACTIVE
SON
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
1057A
1057A
2HFF
SOIC
TCAN1057AVDDFRQ1
TCAN1057AVDRBRQ1
TCAN1057AVDRQ1
ACTIVE SOT-23-THIN
DDF
DRB
D
ACTIVE
ACTIVE
SON
1057AV
1057AV
SOIC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
12-Dec-2021
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Dec-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TCAN1057ADDFRQ1
SOT-
DDF
8
3000
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
23-THIN
TCAN1057ADRBRQ1
TCAN1057ADRQ1
SON
DRB
D
8
8
8
3000
2500
3000
330.0
330.0
180.0
12.4
12.4
8.4
3.3
6.4
3.2
3.3
5.2
3.2
1.1
2.1
1.4
8.0
8.0
4.0
12.0
12.0
8.0
Q1
Q1
Q3
SOIC
TCAN1057AVDDFRQ1
SOT-
DDF
23-THIN
TCAN1057AVDRBRQ1
TCAN1057AVDRQ1
SON
DRB
D
8
8
3000
2500
330.0
330.0
12.4
12.4
3.3
6.4
3.3
5.2
1.1
2.1
8.0
8.0
12.0
12.0
Q1
Q1
SOIC
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Dec-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TCAN1057ADDFRQ1
TCAN1057ADRBRQ1
TCAN1057ADRQ1
SOT-23-THIN
SON
DDF
DRB
D
8
8
8
8
8
8
3000
3000
2500
3000
3000
2500
210.0
367.0
853.0
210.0
367.0
853.0
185.0
367.0
449.0
185.0
367.0
449.0
35.0
35.0
35.0
35.0
35.0
35.0
SOIC
TCAN1057AVDDFRQ1
TCAN1057AVDRBRQ1
TCAN1057AVDRQ1
SOT-23-THIN
SON
DDF
DRB
D
SOIC
Pack Materials-Page 2
PACKAGE OUTLINE
DDF0008A
SOT-23 - 1.1 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC SMALL OUTLINE
C
2.95
2.65
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
6X 0.65
8
1
2.95
2.85
NOTE 3
2X
1.95
4
5
0.4
0.2
8X
0.1
C A
B
1.65
1.55
B
1.1 MAX
0.20
0.08
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.1
0.0
0 - 8
0.6
0.3
DETAIL A
TYPICAL
4222047/B 11/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(R0.05)
TYP
(2.6)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222047/B 11/2015
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
(R0.05) TYP
8
1
8X (0.45)
SYMM
6X (0.65)
5
4
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4222047/B 11/2015
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
VSON - 1 mm max height
DRB0008J
PLASTIC QUAD FLAT PACK- NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
0.1 MIN
(0.13)
SECTION A-A
TYPICAL
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
1.75
1.55
(0.2) TYP
6X 0.65
(0.19)
4
5
SYMM
9
2.5
2.3
1.95
1
8
0.36
0.26
8X
PIN 1 ID
(OPTIONAL)
0.1
0.05
C A B
C
SYMM
0.5
0.3
8X
4225036/A 06/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VSON - 1 mm max height
DRB0008J
PLASTIC QUAD FLAT PACK- NO LEAD
(2.8)
(1.65)
8X (0.6)
8X (0.31)
SYMM
1
8
6X (0.65)
SYMM
9
(1.95) (2.4)
(0.95)
(R0.05) TYP
4
5
(Ø 0.2) VIA
TYP
(0.575)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
NON- SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225036/A 06/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VSON - 1 mm max height
DRB0008J
PLASTIC QUAD FLAT PACK- NO LEAD
(2.8)
2X
(1.51)
8X (0.6)
8X (0.31)
SYMM
1
8
2X
(1.06)
6X (0.65)
SYMM
(1.95)
(0.63)
9
(R0.05) TYP
4
5
METAL
TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
81% PRINTED COVERAGE BY AREA
SCALE: 20X
4225036/A 06/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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