TCA9543ADR [TI]
具有中断、复位和电压转换功能的 2 通道、1.65V 至 5.5V I2C/SMBus 开关 | D | 14 | -40 to 85;型号: | TCA9543ADR |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有中断、复位和电压转换功能的 2 通道、1.65V 至 5.5V I2C/SMBus 开关 | D | 14 | -40 to 85 开关 光电二极管 接口集成电路 |
文件: | 总31页 (文件大小:812K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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TCA9543A
ZHCSC97B –MARCH 2014–REVISED NOVEMBER 2019
TCA9543A 具有中断逻辑电路和复位功能的低压 2 通道 I2C 总线开关
1 特性
2 应用
1
•
2 选 1 双向转换开关
•
•
•
•
服务器
•
•
•
•
•
与 I2C 总线和系统管理总线 (SMBus) 兼容
两个低电平有效中断输入
低电平有效中断输出
路由器(电信交换设备)
工厂自动化
具有 I2C 从器件地址冲突(多个完全一样的温度传
感器)的产品
低电平有效复位输入
两个地址引脚,允许在 I2C 总线上支持多达四个
TCA9543A 器件
3 说明
TCA9543A 是一款由 I2C 总线控制的双路双向转换开
关。串行时钟/串行数据 (SCL/SDA) 上行对扩展到 2 个
下行对,或者通道。根据可编程控制寄存器的内容,可
选择任一单独的 SCn/SDn 通道或者这两个通道。提供
两个中断输入 (INT1-INT0),每个中断输入针对一个下
行对。一个中断输出 (INT) 可作为两个中断输入的与
(AND) 操作。
•
•
•
•
通过 I2C 总线进行通道选择,可任意组合
上电时所有开关通道取消选定
低 RON 开关
支持在 1.8V、2.5V、3.3V 和 5V 总线间
进行电压电平转换
•
•
•
•
•
•
•
•
上电时无干扰
支持热插入
低待机电流
一个低电平有效复位 (RESET) 输入使得 TCA9543A
能够在其中一个下行 I2C 总线长时间处于低电平的情况
下恢复。将 RESET 下拉为低电平会使 I2C 状态机复
位,并且使这两个通道取消选中,这一功能与内部加电
复位功能的作用一样。
工作电源电压范围为 1.65V 至 5.5V
5.5V 耐压输入
0 至 400kHz 时钟频率
闩锁性能超过 100mA,符合 JESD78 规范
ESD 保护性能超过 JESD 22 规范要求
在开关上建有导通栅极,这样的话,VCC 引脚可被用
于限制将由 TCA9543A 传递的最大高压。这允许在每
个对上使用不同的总线电压,以便 1.8V,2.5V 或
3.3V 部件可以在没有任何额外保护的情况下与 5V 部
件通信。对于每个通道,外部上拉电阻器将总线电压上
拉至所需的电压水平。所有 I/O 引脚可耐受 5.5V 电
压。
–
–
4000V 人体放电模型 (A114-A)
1500V 充电器件模型 (C101)
器件信息(1)
器件型号
TCA9543A
封装
TSSOP (14)
SOIC (14)
封装尺寸(标称值)
5.00mm × 4.40mm
8.65mm × 3.91mm
(1) 要了解所有可用封装,请见数据表末尾的可订购产品附录。
简化应用示意图
VCC
SDA
SCL
INT
Channel 0
Channel 1
I2C or SMBus
Master
(e.g. Processor)
SD0
SC0
INT0
Slaves A0, A1...AN
RESET
TCA9543A
SD1
SC1
A0
A1
GND
Slaves B0, B1...BN
INT1
1
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。 有关适用的官方英文版本的最新信息,请访问 www.ti.com,其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SCPS206
TCA9543A
ZHCSC97B –MARCH 2014–REVISED NOVEMBER 2019
www.ti.com.cn
目录
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 12
8.5 Programming........................................................... 12
8.6 Register Maps......................................................... 14
Application and Implementation ........................ 17
9.1 Application Information............................................ 17
9.2 Typical Application .................................................. 17
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 I2C Interface Timing Requirements........................... 6
6.7 Switching Characteristics.......................................... 7
6.8 Interrupt and Reset Timing Requirements................ 7
6.9 Typical Characteristics.............................................. 8
Parameter Measurement Information .................. 9
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
9
10 Power Supply Recommendations ..................... 20
10.1 Power-On Reset Requirements ........................... 20
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Example .................................................... 22
12 器件和文档支持 ..................................................... 23
12.1 接收文档更新通知 ................................................. 23
12.2 支持资源................................................................ 23
12.3 商标....................................................................... 23
12.4 静电放电警告......................................................... 23
12.5 Glossary................................................................ 23
13 机械、封装和可订购信息....................................... 23
7
8
4 修订历史记录
Changes from Revision A (February 2015) to Revision B
Page
•
•
Changed the Pin Configuration images appearance.............................................................................................................. 3
Changed VCC = 3.3 V to VCC = 2.5 V in Figure 16 .............................................................................................................. 17
Changes from Original (September 2012) to Revision A
Page
•
已添加 添加了引脚配置和功能 部分、ESD 额定值 表、特性 说明 部分、器件功能模式、应用和实施 部分、电源相关
建议 部分、布局 部分、器件和文档支持 部分以及机械、封装和可订购信息 部分 ................................................................. 1
已添加 向数据表添加了 D 封装............................................................................................................................................... 1
Changed Handling Ratings table to ESD Ratings.................................................................................................................. 4
Added D package to the Thermal Information table. ............................................................................................................. 4
•
•
•
2
Copyright © 2014–2019, Texas Instruments Incorporated
TCA9543A
www.ti.com.cn
ZHCSC97B –MARCH 2014–REVISED NOVEMBER 2019
5 Pin Configuration and Functions
D Package
SOIC 14 Pins
Top View
PW Package
TSSOP 14 Pins
Top View
A0
A1
1
2
3
4
5
6
7
14
13
12
11
10
9
VCC
SDA
SCL
INT
A0
A1
1
2
3
4
5
6
7
14
13
12
11
10
9
VCC
SDA
SCL
INT
RESET
INT0
SD0
RESET
INT0
SD0
SC1
SD1
INT1
SC1
SD1
INT1
SC0
SC0
GND
8
GND
8
Not to scale
Not to scale
Pin Functions
PIN
DESCRIPTION
NO.
NAME
A0
1
2
Address input 0. Connect directly to VCC or ground.
A1
Address input 1. Connect directly to VCC or ground.
3
RESET
INT0
SD0
SC0
GND
INT1
SD1
SC1
INT
Active-low reset input. Connect to VCC or VDPUM(1) through a pull-up resistor, if not used.
Active-low interrupt input 0. Connect to VDPU0(1) through a pull-up resistor.
Serial data 0. Connect to VDPU0(1) through a pull-up resistor.
Serial clock 0. Connect to VDPU0(1) through a pull-up resistor.
Ground
Active-low interrupt input 1. Connect to VDPU1(1) through a pull-up resistor.
Serial data 1. Connect to VDPU1(1) through a pull-up resistor.
Serial clock 1. Connect to VDPU1(1) through a pull-up resistor.
Active-low interrupt output. Connect to VDPUM(1) through a pull-up resistor.
Serial clock line. Connect to VDPUM(1) through a pull-up resistor.
Serial data line. Connect to VDPUM(1) through a pull-up resistor.
Supply power
4
5
6
7
8
9
10
11
12
13
14
SCL
SDA
VCC
(1) VDPUX is the pull-up reference voltage for the associated data line. VDPUM is the master I2C reference voltage while VDPU0 and VDPU1 are
the slave channel reference voltages.
Copyright © 2014–2019, Texas Instruments Incorporated
3
TCA9543A
ZHCSC97B –MARCH 2014–REVISED NOVEMBER 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
MAX
UNIT
V
VCC
VI
Supply voltage range
Input voltage range(2)
7
7
V
II
Input current
±20
±25
±100
±100
400
85
mA
mA
mA
mA
mW
°C
IO
Output current
Continuous current through VCC
Continuous current through GND
Total power dissipation
Operating free-air temperature range
Storage temperature range
Ptot
TA
–40
–60
Tstg
150
°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±4000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions(1)
MIN
MAX
5.5
UNIT
VCC
VIH
Supply voltage
1.65
0.7 × VCC
0.7 × VCC
–0.5
V
SCL, SDA
6
High-level input voltage
V
A1, A0, INT1, INT0, RESET
SCL, SDA
VCC + 0.5
0.3 × VCC
0.3 × VCC
85
VIL
TA
Low-level input voltage
V
A1, A0, INT1, INT0, RESET
–0.5
Operating free-air temperature
–40
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
6.4 Thermal Information
TCA9543A
THERMAL METRIC(1)
PW
14 PINS
130.9
59.2
D
14 PINS
102.8
63.9
UNIT
RθJA
RθJCtop
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
72.7
57.1
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
10.5
26.7
ψJB
72.1
56.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2014–2019, Texas Instruments Incorporated
TCA9543A
www.ti.com.cn
ZHCSC97B –MARCH 2014–REVISED NOVEMBER 2019
6.5 Electrical Characteristics(1)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN TYP(2)
MAX
UNIT
Power-on reset voltage,
VCC rising
VPORR
VPORF
No load: VI = VCC or GND(3)
1.2
1.5
V
Power-on reset voltage,
VCC falling(4)
No load: VI = VCC or GND(3)
0.8
1
V
5 V
4.5 V to 5.5 V
3.3 V
3.6
2.6
1.6
1.0
0.5
4.5
2.8
1.8
1.9
1.4
0.8
3 V to 3.6 V
2.5 V
VSWin = VCC
ISWout = –100 μA
,
Vpass
Switch output voltage
V
2.3 V to 2.7 V
1.8 V
1.65 V to 1.95 V
1.65 V to 5.5 V
1.1
10
IOH
INT
VO = VCC
μA
VOL = 0.4 V
3
6
7
SDA
IOL
VOL = 0.6 V
1.65 V to 5.5 V
10
mA
INT
VOL = 0.4 V
3
SCL, SDA
SC1–SC0, SD1–SD0
A1, A0
VI = VCC or GND(3)
VI = VCC or GND(3)
VI = VCC or GND(3)
VI = VCC or GND(3)
VI = VCC or GND(3)
1.65 V to 5.5 V
1.65 V to 5.5 V
1.65 V to 5.5 V
1.65 V to 5.5 V
1.65 V to 5.5 V
5.5 V
–1
–1
–1
–1
–1
1
1
1
1
1
II
μA
INT1–INT0
RESET
50
20
11
6
VI = VCC or GND(3)
IO = 0
tr,max = 300 ns
3.6 V
fSCL = 400
kHz
2.7 V
1.65 V
Operating
mode
5.5 V
35
14
5
VI = VCC or GND(3)
IO = 0
tr,max = 1 µs
3.6 V
fSCL = 100
kHz
2.7 V
1.65 V
2
ICC
μA
5.5 V
1.6
1.0
0.7
0.4
1.6
1.0
0.7
0.4
2
1.3
1.1
0.55
2
VI = GND(3)
IO = 0
3.6 V
Low inputs
2.7 V
1.65 V
Standby
mode
5.5 V
3.6 V
1.3
1.1
0.55
VI = VCC
IO = 0
High inputs
INT1–INT0
2.7 V
1.65 V
One INT1–INT0 input at 0.6 V,
Other inputs at VCC or GND(3)
3
3
2
2
20
20
15
15
One INT1–INT0 input at VCC – 0.6 V,
Other inputs at VCC or GND(3)
Supply-
current
change
ΔICC
1.65 V to 5.5 V
μA
SCL or SDA input at 0.6 V,
Other inputs at VCC or GND(3)
SCL, SDA
SCL or SDA input at VCC – 0.6 V,
Other inputs at VCC or GND(3)
(1) For operation between specified voltage ranges, refer to the worst-case parameter in both applicable ranges.
(2) All typical values are at nominal supply voltage (1.8-V, 2.5-V, 3.3-V, or 5-V VCC), TA = 25°C.
(3) RESET = VCC (held high) when all other input voltages, VI = GND
(4) The power-on reset circuit resets the I2C bus logic when VCC < VPORF
.
Copyright © 2014–2019, Texas Instruments Incorporated
5
TCA9543A
ZHCSC97B –MARCH 2014–REVISED NOVEMBER 2019
www.ti.com.cn
Electrical Characteristics(1) (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
A1, A0
TEST CONDITIONS
VI = VCC or GND(3)
VI = VCC or GND(3)
VI = VCC or GND(3)
VCC
MIN TYP(2)
MAX
UNIT
1.65 V to 5.5 V
1.65 V to 5.5 V
1.65 V to 5.5 V
4.5
4.5
4.5
15
6
6
6
Ci
INT1–INT0
RESET
pF
5.5
19
8
SCL, SDA
(5)
Cio(OFF)
VI = VCC or GND(3), Switch OFF
1.65 V to 5.5 V
pF
SC1–SC0, SD1–SD0
4.5 V to 5.5 V
3 V to 3.6 V
4
5
10
13
16
25
16
20
45
70
VO = 0.4 V, IO = 15 mA
RON
Switch on-state resistance
Ω
2.3 V to 2.7 V
1.65 V to 1.95 V
7
VO = 0.4 V, IO = 10 mA
10
(5) Cio(ON) depends on the device capacitance and load that is downstream from the device.
6.6 I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5)
STANDARD MODE
I2C BUS
FAST MODE
I2C BUS
UNIT
MIN
0
MAX
MIN
0
MAX
fscl
tsch
tscl
tsp
I2C clock frequency
I2C clock high time
I2C clock low time
I2C spike time
I2C serial-data setup time
I2C serial-data hold time
I2C input rise time
I2C input fall time
100
400 kHz
4
0.6
1.3
μs
4.7
μs
50 ns
ns
50
tsds
tsdh
ticr
250
0(1)
100
0(1)
μs
(2)
1000 20 + 0.1Cb
300 20 + 0.1Cb
300 20 + 0.1Cb
300 ns
300 ns
300 ns
μs
(2)
(2)
ticf
tocf
tbuf
tsts
tsth
tsps
I2C output fall time
10-pF to 400-pF bus
I2C bus free time between stop and start
I2C start or repeated start condition setup
I2C start or repeated start condition hold
I2C stop condition setup
4.7
4.7
4
1.3
0.6
0.6
0.6
μs
μs
4
μs
tvdL(Data) Valid-data time (high to low)(3)
tvdH(Data) Valid-data time (low to high)(3)
SCL low to SDA output low valid
SCL low to SDA output high valid
1
1
μs
0.6
0.6 μs
ACK signal from SCL low
to SDA output low
tvd(ack)
Cb
Valid-data time of ACK condition
I2C bus capacitive load
1
1
μs
400
400 pF
(1) A device internally must provide a hold time of at least 300-ns for the SDA signal (referred to as the VIH min of the SCL signal), in order
to bridge the undefined region of the falling edge of SCL.
(2) Cb = total bus capacitance of one bus line in pF
(3) Data taken using a 1-kΩ pullup resistor and 50-pF load (see Figure 5)
6
Copyright © 2014–2019, Texas Instruments Incorporated
TCA9543A
www.ti.com.cn
ZHCSC97B –MARCH 2014–REVISED NOVEMBER 2019
6.7 Switching Characteristics
over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 7)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
RON = 20 Ω, CL = 15 pF
RON = 20 Ω, CL = 50 pF
0.3
1
(1)
tpd
Propagation delay time
SDA or SCL
SDn or SCn
ns
tiv
tir
Interrupt valid time(2)
Interrupt reset delay time(2)
INTn
INTn
INT
INT
4
μs
μs
2
(1) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
(2) Data taken using a 4.7-kΩ pullup resistor and 100-pF load (see Figure 7)
6.8 Interrupt and Reset Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7)
PARAMETER
Required low-level pulse duration of INTn inputs(1)
Required high-level pulse duration of INTn inputs(1)
Pulse duration, RESET low
MIN
1
MAX UNIT
tPWRL
tPWRH
tWL
μs
μs
ns
0.5
4
(2)
trst
RESET time (SDA clear)
500
ns
ns
tREC
Recovery time from RESET to start
0
(1) The device has interrupt input rejection circuitry for pulses less than the listed minimum.
(2) trst is the propagation delay measured from the time the RESET terminal is first asserted low to the time the SDA terminal is asserted
high, signaling a stop condition. It must be a minimum of tWL
.
Copyright © 2014–2019, Texas Instruments Incorporated
7
TCA9543A
ZHCSC97B –MARCH 2014–REVISED NOVEMBER 2019
www.ti.com.cn
6.9 Typical Characteristics
800
1.8
1.6
1.4
1.2
1
VCC = 5.5V
VCC = 3.3V
VCC = 1.65V
700
600
500
400
300
200
100
0
0.8
0.6
0.4
0.2
25ºC (Room Temperature)
85ºC
-40ºC
0
2
4
6
IOL (mA)
8
10
12
1.5
2
2.5
3
3.5
VCC (V)
4
4.5
5
5.5
D003
D004
Figure 1. SDA Output Low Voltage (VOL) vs Load Current
(IOL) at Three VCC Levels
Figure 2. Standby Current (ICC) vs Supply Voltage (VCC) at
Three Temperature Points
30
6
25ºC (Room Temperature)
85ºC
-40º
5.8
5.6
5.4
5.2
5
25
20
15
10
5
4.8
4.6
4.4
4.2
4
25ºC (Room Temperature)
85ºC
-40ºC
0
0
0.5
1
1.5
2
2.5
VCC (V)
3
3.5
4
4.5
5
5.5
0
0.5
1
1.5
2
2.5
VCC (V)
3
3.5
4
4.5
5
5.5
D001
D001
Figure 3. Slave channel (SCn/SDn) capacitance (Cio(OFF)) vs.
Supply Voltage (VCC) at Three Temperature Points
Figure 4. ON-Resistance (RON) vs Supply Voltage (VCC) at
Three Temperatures
8
Copyright © 2014–2019, Texas Instruments Incorporated
TCA9543A
www.ti.com.cn
ZHCSC97B –MARCH 2014–REVISED NOVEMBER 2019
7 Parameter Measurement Information
V
CC
R
L
= 1 kΩ
SDn, SCn
DUT
C
= 50 pF
L
(See Note A)
2
I C PORT LOAD CONFIGURATION
Two Bytes for Complete
Device Programming
Stop
Condition Condition
(P) (S)
Start
Address
Bit 7
(MSB)
R/W
Data
Bit 7
(MSB)
Data
Bit 0
(LSB)
Stop
Condition
(P)
ACK
(A)
Address
Bit 6
Address
Bit 1
ACK
(A)
Bit 0
(LSB)
BYTE
DESCRIPTION
2
1
I C address + R/W
2
Control register data
t
scl
t
sch
0.7 × VCC
0.3 × VCC
SCL
SDA
t
vd(ACK)
t
t
icr
sts
or t
vdL
t
icf
t
buf
t
t
sp
vdH
0.7 × VCC
0.3 × VCC
t
t
icr
icf
t
sdh
t
sps
t
sth
t
Repeat
sds
Stop
Condition
Start
Condition
Start or Repeat
Start Condition
VOLTAGE WAVEFORMS
A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω,
tr/tf = 30 ns.
C. The outputs are measured one at a time, with one transition per measurement.
Figure 5. I2C Interface Load Circuit, Byte Descriptions, and Voltage Waveforms
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Parameter Measurement Information (continued)
Figure 6. Reset Timing
VCC
RL = 4.7 kΩ
INT
DUT
CL = 100 pF
(See Note A)
INTERRUPT LOAD CONFIGURATION
INTn
INTn
0.5 × VCC
0.5 × VCC
(input)
(input)
t
ir
t
iv
INT
INT
0.5 × VCC
0.5 × VCC
(output)
(output)
VOLTAGE WAVEFORMS (t )
iv
VOLTAGE WAVEFORMS (t )
ir
A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω,
tr/tf = 30 ns.
Figure 7. Interrupt Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The TCA9543A is a 2-channel, bidirectional translating I2C switch. The master SCL/SDA signal pair is directed to
two channels of slave devices, SC0/SD0-SC1/SD1. Either individual downstream channel can be selected as
well as both channels. The TCA9543A also supports interrupt signals in order for the master to detect an
interrupt on the INT output terminal that can result from any of the slave devices connected to the INT1-INT0
input terminals.
The device offers an active-low RESET input which resets the state machine and allows the TCA9543A to
recover should one of the downstream I2C buses get stuck in a low state. The state machine of the device can
also be reset by cycling the power supply, VCC, also known as a power-on reset (POR). Either using the RESET
function or causing a POR will cause both channels to be deselected.
The connections of the I2C data path are controlled by the same I2C master device that is switched to
communicate with multiple I2C slaves. After the successful acknowledgment of the slave address (hardware
selectable by A0 and A1 terminals), a single 8-bit control register is written to or read from to determine the
selected channels and state of the interrupts.
The TCA9543A may also be used for voltage translation, allowing the use of different bus voltages on each
SCn/SDn pair such that 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts. This is achieved by using
external pull-up resistors to pull the bus up to the desired voltage for the master and each slave channel.
8.2 Functional Block Diagram
TCA9543A
6
SC0
10
SC1
5
SD0
9
SD1
7
Switch Control Logic
GND
14
VCC
Power-On
Reset
3
RESET
12
1
SCL
SDA
A0
A1
I2C Bus
Control
Input Filter
13
2
4
8
11
INT0
INT1
INT
Output Filter
Interrupt Logic
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8.3 Feature Description
The TCA9543A is a dual channel bidirectional translating switch for I2C buses that supports Standard-Mode (100
kHz) and Fast-Mode (400 kHz) operation. The TCA9543A features I2C control using a single 8-bit control register
in which bits 1 and 0 control the enabling and disabling of the two switch channels of I2C data flow. The
TCA9543A also supports interrupt signals for each slave channel and this data is held in bits 5 and 4 of the
control register. Depending on the application, voltage translation of the I2C bus can also be achieved using the
TCA9543A to allow 1.8-V, 2.5-V, or 3.3-V parts to communicate with 5-V parts. Additionally, in the event that
communication on the I2C bus enters a fault state, the TCA9543A can be reset to resume normal operation using
the RESET terminal feature or by a power-on reset which results from cycling power to the device.
8.4 Device Functional Modes
8.4.1 RESET Input
The RESET input can be used to recover the TCA9543A from a bus-fault condition. The registers and the I2C
state machine within this device initialize to their default states if this signal is asserted low for a minimum of tWL
.
Both channels also are deselected in this case. RESET must be connected to VCC through a pull-up resistor.
8.4.2 Power-On Reset
When power is applied to VCC, an internal power-on reset holds the TCA9543A in a reset condition until VCC has
reached VPORR. At this point, the reset condition is released and the TCA9543A registers and I2C state machine
are initialized to their default states, all zeroes, causing all the channels to be deselected. Thereafter, VCC must
be lowered below VPORF to reset the device.
8.5 Programming
8.5.1 I2C Interface
The I2C bus is for two-way, two-line communication between different ICs or modules. The two lines are a serial
data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pullup
resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not
busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high
period of the clock pulse as changes in the data line at this time is interpreted as control signals (see Figure 8).
SDA
SCL
Data Line
Stable;
Data Valid
Change
of data
allowed
Figure 8. Bit Transfer
Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the
clock is high is defined as the start condition (S). A low-to-high transition of the data line while the clock is high is
defined as the stop condition (P) (see Figure 9).
SDA
SDA
SCL
SCL
S
P
STOP Condition
START Condition
Figure 9. Definition of Start and Stop Conditions
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Programming (continued)
A device generating a message is a transmitter; a device receiving a message is the receiver. The device that
controls the message is the master and the devices that are controlled by the master are the slaves (see
Figure 10).
SDA
SCL
Master
Transmitter/
Receiver
Slave
Master
Transmitter/
Receiver
I2C-Bus
Slave
Master
Transmitter/
Receiver
Receiver
Transmitter
Multiplexer
Slave
Figure 10. System Configuration
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not
limited. Each byte of eight bits is followed by one acknowledge (ACK) bit. The transmitter must release the SDA
line before the receiver can send an ACK bit.
When a slave receiver is addressed, it must generate an ACK after the reception of each byte. Also, a master
must generate an ACK after the reception of each byte that has been clocked out of the slave transmitter. The
device that acknowledges must pull down the SDA line during the ACK clock pulse, so that the SDA line is stable
low during the high pulse of the ACK-related clock period (see Figure 11). Setup and hold times must be taken
into account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.
In this event, the transmitter must release the data line to enable the master to generate a stop condition.
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master
1
2
8
9
S
Clock Pulse for
Acknowledgment
Start
Condition
Figure 11. Acknowledgment on I2C Bus
Data is transmitted to the TCA9543A control register using the write mode shown in Figure 12.
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Programming (continued)
Slave Address
Control Register
SDA
S
1
1
1
0
0
A1 A0
0
A
X
X
X
X
X
X
B1 B0
A
P
Start
Condition
R/W Acknowledge
From Slave
Acknowledge
From Slave
Stop
Condition
Figure 12. Write Control Register
Data is read from the TCA9543A control register using the read mode shown in Figure 13.
Last Byte
Slave Address
Control Register
SDA
INT1
S
1
1
1
0
0
A1 A0
1
A
X
X
INT0
X
X
B1 B0 NA
P
Start
Condition
R/W Acknowledge
From Slave
No Acknowledge
From Master
Stop
Condition
Figure 13. Read Control Register
8.6 Register Maps
8.6.1 Device Address
Following a start condition, the bus master must output the address of the slave it is accessing. The address of
the TCA9543A is shown in Figure 14. To conserve power, no internal pullup resistors are incorporated on the
hardware-selectable address terminals and they must be pulled high or low.
1
1
1
0
0
A1 A0 R/W
Fixed
Hardware
selectable
Figure 14. Slave Address TCA9543A
The last bit of the slave address defines the operation to be performed. When set to a logic 1, a read is selected,
while a logic 0 selects a write operation.
8.6.2 Control Register Description
Following the successful acknowledgment of the slave address, the bus master sends a byte to the TCA9543A,
which is stored in the control register (see Figure 15). If multiple bytes are received by the TCA9543A, it saves
the last byte received. This register can be written and read via the I2C bus.
14
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Register Maps (continued)
Channel Selection Bits
(Read/Write)
Interrupt Bits
(Read Only)
7
6
X
5
4
3
X
2
X
1
0
X
INT1 INT0
B1 B0
Channel 0
Channel 1
INT0
INT1
Figure 15. Control Register
8.6.3 Control Register Definition
One or both SCn/SDn downstream pairs, or channels, are selected by the contents of the control register (see
Table 1). After the TCA9543A has been addressed, the control register is written. The two LSBs of the control
byte are used to determine which channel or channels are to be selected. When a channel is selected, the
channel becomes active after a stop condition has been placed on the I2C bus. This ensures that all SCn/SDn
lines are in a high state when the channel is made active, so that no false conditions are generated at the time of
connection. A stop condition must occur always right after the acknowledge cycle.
Table 1. Control Register Write (Channel Selection), Control Register Read (Channel Status)(1)
D7
D6
INT1
INT0
D3
D2
B1
B0
0
COMMAND
Channel 0 disabled
X
X
X
X
X
X
X
1
Channel 0 enabled
0
1
0
Channel 1 disabled
X
0
X
0
X
0
X
0
X
0
X
0
X
0
Channel 1 enabled
No channel selected; power-up/reset default state
(1) Channel 0 and channel 1 can be enabled at the same time. Care should be taken not to exceed the maximum bus capacitance.
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8.6.4 Interrupt Handling
The TCA9543A provides two interrupt inputs (one for each channel) and one open-drain interrupt output (see
Table 2). When an interrupt is generated by any device, it is detected by the TCA9543A and the interrupt output
is driven low. The channel does not need to be active for detection of the interrupt. A bit also is set in the control
register.
Bit 4 and Bit 5 of the control register correspond to the INT0 and INT1 inputs of the TCA9543A, respectively.
Therefore, if an interrupt is generated by any device connected to channel 1, the state of the interrupt inputs is
loaded into the control register when a read is accomplished. Likewise, an interrupt on any device connected to
channel 0 would cause bit 4 of the control register to be set on the read. The master then can address the
TCA9543A and read the contents of the control register to determine which channel contains the device
generating the interrupt. The master then can reconfigure the TCA9543A to select this channel, and locate the
device generating the interrupt and clear it.
It should be noted that more than one device can provide an interrupt on a channel, so it is up to the master to
ensure that all devices on a channel are interrogated for an interrupt.
The interrupt inputs may be used as general-purpose inputs if the interrupt function is not required.
If unused, interrupt input(s) must be connected to VCC through a pull-up resistor.
Table 2. Control Register Read (Interrupt)(1)
D7
D6
INT1
INT0
D3
D2
B1
B0
COMMAND
No interrupt on channel 0
0
1
X
X
X
X
X
X
X
Interrupt on channel 0
0
1
0
No interrupt on channel 1
X
0
X
0
X
0
X
0
X
0
X
0
X
0
Interrupt on channel 1
No channel selected; power-up/reset default state
(1) Two interrupts can be active at the same time.
16
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Applications of the TCA9543A will contain an I2C (or SMBus) master device and up to two I2C slave devices. The
downstream channels are ideally used to resolve I2C slave address conflicts. For example, if two identical digital
temperature sensors are needed in the application, one sensor can be connected at each channel: 0 and 1.
When the temperature at a specific location needs to be read, the appropriate channel can be enabled and the
other channel switched off, the data can be retrieved, and the I2C master can move on and read the next
channel.
In an application where the I2C bus will contain many additional slave devices that do not result in I2C slave
address conflicts, these slave devices can be connected to any desired channel to distribute the total bus
capacitance across both channels. If both switches will be enabled simultaneously, additional design
requirements must be considered (See Design Requirements and Detailed Design Procedure).
9.2 Typical Application
A typical application of the TCA9543A contains anywhere from 1 to 3 separate data pull-up voltages, VDPUX , one
for the master device (VDPUM) and one for each of the selectable slave channels (VDPU0 and VDPU1). In the event
where the master device and both slave devices operate at the same voltage, then the pass voltage, Vpass
=
VDPUX. Once the maximum Vpass is known, Vcc can be selected easily using Figure 17. In an application where
voltage translation is necessary, additional design requirements must be considered (See Design Requirements).
Figure 16 shows an application in which the TCA9543A can be used.
VDPUM = 1.65 V to 5.5 V
VCC = 2.5 V
VCC
VDPU0 = 1.65 V to 5.5 V
5
6
13
12
11
SDA
SCL
SD0
SC0
INT0
SDA
SCL
Channel 0
4
INT
I2C/SMBus
3
Master
RESET
TCA9543A
VDPU1 = 1.65 V to 5.5 V
2
1
7
9
A1
SD1
SC1
Channel 1
10
8
A0
GND
INT1
Figure 16. Typical Application Schematic
9.2.1 Design Requirements
The pull-up resistors on the INT1-INT0 terminals in the application schematic are not required in all applications.
If the device generating the interrupt has an open-drain output structure or can be tri-stated, a pull-up resistor is
required. If the device generating the interrupt has a push-pull output structure and cannot be tri-stated, a pull-up
resistor is not required. The interrupt inputs should not be left floating in the application.
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Typical Application (continued)
The A0 and A1 terminals are hardware selectable to control the slave address of the TCA9543A. These
terminals may be tied directly to GND or VCC in the application.
If both slave channels will be activated simultaneously in the application, then the total IOL from SCL/SDA to GND
on the master side will be the sum of the currents through all pull-up resistors, Rp.
The pass-gate transistors of the TCA9543A are constructed such that the VCC voltage can be used to limit the
maximum voltage that is passed from one I2C bus to another.
Figure 17 shows the voltage characteristics of the pass-gate transistors (note that the graph was generated using
data specified in the Electrical Characteristics section of this data sheet). In order for the TCA9543A to act as a
voltage translator, the Vpass voltage must be equal to or lower than the lowest bus voltage. For example, if the
main bus is running at 5 V and the downstream buses are 3.3 V and 2.7 V, Vpass must be equal to or below 2.7 V
to effectively clamp the downstream bus voltages. As shown in Figure 17, Vpass(max) is 2.7 V when the TCA9543A
supply voltage is 4 V or lower, so the TCA9543A supply voltage could be set to 3.3 V. Pull-up resistors then can
be used to bring the bus voltages to their appropriate levels (see Figure 16).
9.2.2 Detailed Design Procedure
Once all the slaves are assigned to the appropriate slave channels and bus voltages are identified, the pull-up
resistors, Rp, for each of the buses need to be selected appropriately. The minimum pull-up resistance is a
function of VDPUX, VOL,(max), and IOL
:
VDPUX - VOL(max)
=
Rp(min)
IOL
(1)
The maximum pull-up resistance is a function of the maximum rise time, tr (300 ns for fast-mode operation, fSCL
400 kHz) and bus capacitance, Cb:
=
tr
Rp(max)
=
0.8473´Cb
(2)
The maximum bus capacitance for an I2C bus must not exceed 400 pF for fast-mode operation. The bus
capacitance can be approximated by adding the capacitance of the TCA9543A, Cio(OFF), the capacitance of
wires/connections/traces, and the capacitance of each individual slave on a given channel. If both channels will
be activated simultaneously, each of the slaves on both channels will contribute to total bus capacitance.
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Typical Application (continued)
9.2.3 Application Curves
25
20
15
10
5
5
Standard-mode
Fast-mode
25ºC (Room Temperature)
85ºC
-40ºC
4
3
2
1
0
0
0
0.5
1
1.5
2
2.5 3
VCC (V)
3.5
4
4.5
5
5.5
0
50
100 150 200 250 300 350 400 450
Cb (pF)
D007
D008
Space
spacespace
Space
spacespace
Standard-mode
(fSCL= 100 kHz, tr = 1 µs)
Fast-mode
(fSCL= 400 kHz, tr= 300 ns)
Figure 17. Pass-Gate Voltage (Vpass) vs Supply Voltage
(VCC) at Three Temperature Points
Figure 18. Maximum Pull-Up Resistance (Rp(max)) vs Bus
Capacitance (Cb)
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
VDPUX > 2V
VDPUX <= 2
0
0.5
1
1.5
2
2.5 3
VDPUX (V)
3.5
4
4.5
5
5.5
D009
VOL = 0.2*VDPUX, IOL = 2 mA when VDPUX ≤ 2 V
VOL = 0.4 V, IOL = 3 mA when VDPUX > 2 V
Figure 19. Minimum Pull-Up Resistance (Rp(min)) vs Pull-Up Reference Voltage (VDPUX
)
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10 Power Supply Recommendations
The operating power-supply voltage range of the TCA9543A is 1.65-V to 5.5-V applied at the VCC terminal.
When the TCA9543A is powered on for the first time or anytime the device needs to be reset by cycling the
power supply, the power-on reset requirements must be followed to ensure the I2C bus logic is initialized
properly.
10.1 Power-On Reset Requirements
In the event of a glitch or data corruption, TCA9543A can be reset to its default conditions by using the power-on
reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This
reset also happens when the device is powered on for the first time in an application.
A power-on reset is shown in Figure 20.
V
CC
Ramp-Down
Ramp-Up
V
CC_TRR
V
drops below VPORF – 50 mV
CC
Time
Time to Re-Ramp
V
V
CC_FT
CC_RT
Figure 20. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC
Table 3 specifies the performance of the power-on reset feature for TCA9543A for both types of power-on reset.
Table 3. Recommended Supply Sequencing And Ramp Rates(1)
PARAMETER
MIN TYP
MAX UNIT
VCC_FT
VCC_RT
Fall time
See Figure 20
See Figure 20
1
100
100
ms
ms
Rise time
0.1
Time to re-ramp (when VCC drops below VPORF(min) – 50 mV or
when VCC drops to GND)
VCC_TRR
VCC_GH
VCC_GW
See Figure 20
See Figure 21
See Figure 21
40
μs
V
Level that VCC can glitch down to, but not cause a functional
disruption when VCC_GW = 1 μs
1.2
10
Glitch width that will not cause a functional disruption when
VCC_GH = 0.5 × VCC
μs
VPORF
VPORR
Voltage trip point of POR on falling VCC
Voltage trip point of POR on rising VCC
See Figure 22
See Figure 22
0.8
1.25
1.5
V
V
1.05
(1) All supply sequencing and ramp rate values are measured at TA = 25°C
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Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and
device impedance are factors that affect power-on reset performance. Figure 21 and Table 3 provide more
information on how to measure these specifications.
V
CC
V
CC_GH
Time
V
CC_GW
Figure 21. Glitch Width and Glitch Height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the
registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based
on the VCC being lowered to or from 0. Figure 22 and Table 3 provide more details on this specification.
V
CC
V
PORR
V
PORF
Time
POR
Time
Figure 22. VPOR
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11 Layout
11.1 Layout Guidelines
For PCB layout of the TCA9543A, common PCB layout practices should be followed but additional concerns
related to high-speed data transfer such as matched impedances and differential pairs are not a concern for I2C
signal speeds. It is common to have a dedicated ground plane on an inner layer of the board and terminals that
are connected to ground should have a low-impedance path to the ground plane in the form of wide polygon
pours and multiple vias. By-pass and de-coupling capacitors are commonly used to control the voltage on the
VCC terminal, using a larger capacitor to provide additional power in the event of a short power supply glitch and
a smaller capacitor to filter out high-frequency ripple.
In an application where voltage translation is not required, all VDPUX voltages and VCC could be at the same
potential and a single copper plane can connect all of the pull-up resistors to the appropriate reference voltage.
In an application where voltage translation is required, VDPUM, VDPU0, and VDPU1, may all be on the same layer of
the board with split planes to isolate different voltage potentials.
To reduce the total I2C bus capacitance added by PCB parasitics, data lines (SCn, SDn and INTn) should be a
short as possible and the widths of the traces should also be minimized (e.g. 5-10 mils depending on copper
weight).
11.2 Layout Example
LEGEND
Polygonal
Copper Pour
Partial Power Plane
To I2C Master
VIA to Power Plane
VIA to GND Plane (Inner Layer)
By-pass/De-coupling
capacitors
VDPUM
GND
VCC
VDPU0
A0
A1
VCC
SDA
SCL
INT
VDPU1
RESET
INT0
SD0
SC1
SD1
INT1
SC0
GND
GND
Figure 23. Layout Example
22
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12 器件和文档支持
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品信息更改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
12.2 支持资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更,恕不另行通知,且
不会对此文档进行修订。如需获取此数据表的浏览器版本,请查阅左侧的导航栏。
版权 © 2014–2019, Texas Instruments Incorporated
23
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TCA9543ADR
ACTIVE
ACTIVE
SOIC
D
14
14
2500 RoHS & Green
2000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
TCA9543A
PW543A
TCA9543APWR
TSSOP
PW
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TCA9543ADR
SOIC
D
14
14
2500
2000
330.0
330.0
16.4
12.4
6.5
6.9
9.0
5.6
2.1
1.6
8.0
8.0
16.0
12.0
Q1
Q1
TCA9543APWR
TSSOP
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TCA9543ADR
SOIC
D
14
14
2500
2000
356.0
356.0
356.0
356.0
35.0
35.0
TCA9543APWR
TSSOP
PW
Pack Materials-Page 2
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