TCA9534ADWT_技术文档

Support &

Community

Product

Folder

Order

Now

Tools &

Software

Technical

Documents

TCA9534A

ZHCSCR9C –SEPTEMBER 2014–REVISED FEBRUARY 2017

TCA9534A 具有中断输出和配置寄存器的低压 8 位 I²C 和系统管理总线

(SMBUS) 低功耗输入输出 (I/O) 扩展器

1 特性

2 应用

1

•

低待机电流消耗

I²C 至并行端口扩展器

•

服务器

•

路由器（电信交换设备）

个人计算机

开漏电路低电平有效中断输出

1.65V 至 5.5V 的工作电源电压范围

可耐受 5V 电压的 I/O 端口

400kHz 快速 I²C 总线

3 个硬件地址引脚可在 I²C/SMBus 上支持最多 8

个器件

个人电子产品（例如：游戏机）

工业自动化

采用 GPIO 受限处理器的产品

3 说明

TCA9534A 是一款 16 引脚器件，可为两线双向 I²C 总

线（或 SMBus）协议提供 8 位通用并行输入和输出

(I/O) 扩展。该器件可在 1.65V 至 5.5V 的电源电压范

围内运行，从而允许使用各种器件。该器件支持

100kHz（标准模式）和 400kHz（快速模式）时钟频

率。当开关、传感器、按钮、LED、风扇和其它类似器

件需要额外的 I/O 时，I/O 扩展器（如 TCA9534A）可

提供简单解决方案。

•

输入和输出配置寄存器

极性反转寄存器

内部加电复位

所用通道在加电时被配置为输入

加电时无毛刺脉冲

SCL/SDA 输入端上的噪声滤波器

具有最大高电流驱动能力的锁存输出，适用于直接

驱动 LED

•

锁断性能超过 100mA，符合 JESD 78 II 类规范的

要求）

TCA9534A 的功能包括在 INT 引脚上生成中断。这

样，主设备就知道输入端口状态何时发生了变化。硬件

可选地址引脚 A0、A1 和 A2 最多允许 8 个

TCA9534A 器件位于同一 I²C 总线上。该器件还可通

过电源循环供电以生成加电复位，从而复位到默认状

态。

静电放电 (ESD) 保护性能超过 JESD 22 规范的要

求

–

2000V 人体放电模型 (A114-A)

1000V 充电器件模型 (C101)

器件信息⁽¹⁾

器件型号

TCA9534A

封装

TSSOP (16)

SOIC (16)

封装尺寸（标称值）

5.00mm x 4.40mm

10.30mm x 7.50mm

(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。

简化的原理图

VCC

SDA

SCL

Peripheral

Devices

I2C or SMBus

Master

(e.g. Processor)

P0

P1

P2

P3

INT

• RESET,

ENABLE, or

control

inputs

• INT or

status

TCA9534A

P4

P5

P6

P7

A0

A1

A2

outputs

• LEDs

GND

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SCPS198

TCA9534A

ZHCSCR9C –SEPTEMBER 2014–REVISED FEBRUARY 2017

www.ti.com.cn

8.4 Device Functional Modes........................................ 17

8.5 Programming........................................................... 17

8.6 Register Maps......................................................... 19

Application and Implementation ........................ 24

9.1 Application Information............................................ 24

9.2 Typical Application ................................................. 24

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 4

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ..................................... 5

6.2 Handling Ratings....................................................... 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics........................................... 6

6.6 I²C Interface Timing Requirements........................... 7

6.7 Switching Characteristics.......................................... 8

6.8 Typical Characteristics.............................................. 9

Parameter Measurement Information ................ 12

Detailed Description ............................................ 15

8.1 Overview ................................................................. 15

8.2 Functional Block Diagram ....................................... 16

8.3 Feature Description................................................. 17

9

10 Power Supply Recommendations ..................... 27

10.1 Power-On Reset Requirements ........................... 27

11 Layout................................................................... 29

11.1 Layout Guidelines ................................................. 29

11.2 Layout Example .................................................... 29

12 器件和文档支持 ..................................................... 30

12.1 相关文档ꢀ ........................................................... 30

12.2 接收文档更新通知 ................................................. 30

12.3 社区资源................................................................ 30

12.4 商标....................................................................... 30

12.5 静电放电警告......................................................... 30

12.6 Glossary................................................................ 30

13 机械、封装和可订购信息....................................... 30

7

8

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision B (December 2016) to Revision C

Page

•

Updated Figure 20 ............................................................................................................................................................... 13

Updated address in Table 1 ................................................................................................................................................. 18

Changes from Revision A (September 2014) to Revision B

Page

•

更新了说明部分 .................................................................................................................................................................... 1

已添加 DW 封装...................................................................................................................................................................... 1

Corrected ESD ratings to reflect ± ratings.............................................................................................................................. 5

VIH values, improved performance ........................................................................................................................................ 5

Made changes to I_OLin the Recommended Operating Conditions table................................................................................ 5

Changed V_PORRlimits.............................................................................................................................................................. 6

Changed V_OHat V_CC= 1.65 V................................................................................................................................................. 6

Updated I_OLin the Electrical Characteristics table.................................................................................................................. 6

Changed I_CCin the Electrical Characteristics table ................................................................................................................ 7

Deleted ΔI_CCparameter from the Electrical Characteristics table .......................................................................................... 7

Increased the pin capacitance maximum, decreased typical................................................................................................. 7

Updated graphs in Typical Characteristics section ................................................................................................................ 9

Updated Interrupt Output (INT) section ................................................................................................................................ 17

Added the Calculating Junction Temperature and Power Dissipation section..................................................................... 25

Updated parameter values in Table 8 ................................................................................................................................. 27

Added V_{CC_MV}to Table 8 ..................................................................................................................................................... 27

Updated Figure 39 ............................................................................................................................................................... 27

2

TCA9534A

www.ti.com.cn

ZHCSCR9C –SEPTEMBER 2014–REVISED FEBRUARY 2017

Changes from Original (August 2014) to Revision A

Page

•

最初发布的完整版本 ............................................................................................................................................................... 1

3

TCA9534A

ZHCSCR9C –SEPTEMBER 2014–REVISED FEBRUARY 2017

www.ti.com.cn

5 Pin Configuration and Functions

PW and DW Package

16-Pin TSSOP and SOIC

Top View

16

15

14

13

12

11

10

9

A0

A1

1

2

3

4

5

6

7

8

VCC

SDA

SCL

INT

P7

A2

P0

P1

P2

P6

P3

P5

GND

P4

Pin Functions

I/O

DESCRIPTION

NO.

NAME

A0

1

2

3

I

Address input. Connect directly to V_CCor ground

A1

A2

P-port input-output. Push-pull design structure. At power on,

P0 is configured as an input

4

5

6

P0

P1

P2

I/O

P-port input-output. Push-pull design structure. At power on,

P1 is configured as an input

P-port input-output. Push-pull design structure. At power on,

P2 is configured as an input

P-port input-output. Push-pull design structure. At power on,

P3 is configured as an input

7

8

9

P3

GND

P4

I/O

—

Ground

P-port input-output. Push-pull design structure. At power on,

P4 is configured as an input

I/O

P-port input-output. Push-pull design structure. At power on,

P5 is configured as an input

10

11

12

P5

P6

P7

I/O

P-port input-output. Push-pull design structure. At power on,

P6 is configured as an input

P-port input-output. Push-pull design structure. At power on,

P7 is configured as an input

13

14

15

16

INT

SCL

SDA

VCC

O

I

Interrupt output. Connect to V_CCthrough a pull-up resistor

Serial clock bus. Connect to V_CCthrough a pull-up resistor

Serial data bus. Connect to V_CCthrough a pull-up resistor

Supply voltage

I/O

—

4

TCA9534A

www.ti.com.cn

ZHCSCR9C –SEPTEMBER 2014–REVISED FEBRUARY 2017

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

MIN

–0.5

MAX

6

UNIT

V

V_CC

V_I

Supply voltage

(2)

Input voltage

6

V

(2)

V_O

I_IK

Output voltage

6

V

Input clamp current

V_I< 0

–20

±20

50

mA

I_OK

I_IOK

I_OL

I_OH

Output clamp current

V_O< 0

Input-output clamp current

V_O< 0 or V_O> V_CC

V_O= 0 to V_CC

Continuous output low current through a single P-port

Continuous output high current through a single P-port

–50

250

–160

100

150

Continuous current through GND by all P-ports, INT, and SDA

Continuous current through V_CCby all P-ports

I_CC

mA

T_J(MAX)Maximum junction temperature

T_stgStorage temperature

°C

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 Handling Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

±2000

Electrostatic

discharge

V_(ESD)

V

Charged device model (CDM), per JEDEC specification JESD22-C101, all

pins⁽²⁾

±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN

MAX UNIT

V_CC

V_IH

Supply voltage

1.65

0.7 × V_CC

–0.5

5.5

V

(1)

SCL, SDA

V_CC= 1.65 V to 5.5 V

V_CC= 1.65 V to 2.7 V

V_CC= 1.65 V to 5.5 V

V_CC= 1.65 V to 2.7 V

V_CC= 3 V to 5.5 V

V_CC

High-level input voltage

V

A0, A1, A2, P7–P0

SCL, SDA

5.5

0.3 × V_CC

V_IL

Low-level input voltage

High-level output current

–0.5

0.3 × V_CC

V

A0, A1, A2, P7–P0

Any P-port, P7–P0

–0.5

0.2 × V_CC

I_OH

–10

25

18

9

mA

T_j≤ 65°C

T_j≤ 85°C

T_j≤ 100°C

T_j≤ 85°C

T_j≤ 100°C

P00-P07, P10-P17

INT, SDA

I_OL

Low-level output current⁽²⁾

mA

6

3

Continuous current through

GND

All P-ports P7-P0, INT, and SDA

200

I_CC

T_A

mA

°C

Continuous current through V_CCAll P-ports P7-P0

Operating free-air temperature

–80

85

–40

(1) The SCL and SDA pins shall not be at a higher potential than the supply voltage V_CCin the application, or an increase in leakage

current, I_I, will result.

(2) The values shown apply to specific junction temperatures. See the Calculating Junction Temperature and Power Dissipation section on

how to calculate the junction temperature.

5

TCA9534A

ZHCSCR9C –SEPTEMBER 2014–REVISED FEBRUARY 2017

www.ti.com.cn

6.4 Thermal Information

TCA9534A

PW (TSSOP)

THERMAL METRIC⁽¹⁾

DW (SOIC)

16 PINS

92.2

UNIT

16 PINS

122

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

56.4

53.8

67.1

56.9

Junction-to-top characterization parameter

Junction-to-board characterization parameter

10.8

26.4

ψ_JB

66.5

56.4

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN TYP⁽¹⁾MAX UNIT

V_IK

Input diode clamp voltage

I_I= –18 mA

1.65 V to 5.5 V

–1.2

V

V_PORPower-on reset voltage, V_CC

V_I= V_CCor GND, I_O= 0

1.2

1

1.5

V

rising

R

V_PORPower-on reset voltage, V_CC

0.75

V

falling

F

1.65 V

2.3 V

1.2

1.8

2.6

4.1

1

I_OH= –8 mA

3 V

4.5 V

P-port high-level output

V_OH

voltage⁽²⁾

1.65 V

2.3 V

1.7

2.5

4

I_OH= –10 mA

3 V

4.5 V

SDA⁽³⁾

V_OL= 0.4 V

V_OL= 0.5 V

V_OL= 0.7 V

V_OL= 0.4 V

1.65 V to 5.5 V

3

8

I_OL

P port⁽⁴⁾

mA

10

3

(5)

INT

SCL, SDA

A2–A0

P port

±1

1

I_I

V_I= V_CCor GND

1.65 V to 5.5 V

μA

I_IH

I_IL

V_I= V_CC

1.65 V to 5.5 V

μA

P port

V_I= GND

–1

(1) All typical values are at nominal supply voltage (1.8-, 2.5-, 3.3-, or 5-V V_CC) and T_A= 25°C.

(2) Each P-port I/O configured as a high output must be externally limited to a maximum of 10 mA, and the total current sourced by all I/Os

(P-ports P7-P0) through V_CCmust be limited to a maximum current of 80 mA.

(3) The SDA pin must be externally limited to a maximum of 12 mA, and the total current sunk by all I/Os (P-ports P7-P0, INT, and SDA)

through GND must be limited to a maximum current of 200 mA.

(4) Each P-port I/O configured as a low output must be externally limited to a maximum of 25 mA, and the total current sunk by all I/Os (P-

ports P7-P0, INT, and SDA) through GND must be limited to a maximum current of 200 mA.

(5) The INT pin must be externally limited to a maximum of 7 mA, and the total current sunk by all I/Os (P-ports P7-P0, INT, and SDA)

through GND must be limited to a maximum current of 200 mA.

6

TCA9534A

www.ti.com.cn

ZHCSCR9C –SEPTEMBER 2014–REVISED FEBRUARY 2017

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

5.5 V

MIN TYP⁽¹⁾MAX UNIT

22

11

8

40

30

19

11

3.9

2.2

1.8

1.5

8.7

4

3.6 V

V_I= V_CCor GND, I_O= 0,

I/O = inputs, f_scl= 400 kHz, no load

Operating mode

2.7 V

1.65

5

5.5 V

1.5

0.9

0.6

0.4

1.5

0.9

0.6

0.4

3

3.6 V

I_CC

V_I= V_CC

μA

2.7 V

V_I= GND, I_O= 0,

I/O = inputs, f_scl= 0 kHz, no

load

1.95 V

5.5 V

Standby mode

3.6 V

V_I= GND

2.7 V

3

1.95 V

1.65 V to 5.5 V

2.2

8

C_i

SCL

V_I= V_CCor GND

V_IO= V_CCor GND

pF

SDA

P port

3

9.5

C_io

1.65 V to 5.5 V

3.7

6.6 I²C Interface Timing Requirements

over operating free-air temperature range (unless otherwise noted) (see Figure 19)

MIN

MAX

UNIT

STANDARD MODE

f_scl

I²C clock frequency

I²C clock high time

I²C clock low time

I²C spike time

I²C serial-data setup time

I²C serial-data hold time

I²C input rise time

I²C input fall time

I²C output fall time

I²C bus free time between stop and start

I²C start or repeated start condition setup

I²C start or repeated start condition hold

I²C stop condition setup

Valid data time

0

4

100

50

kHz

µs

ns

µs

ns

t_sch

t_scl

4.7

t_sp

t_sds

t_sdh

t_icr

250

0

1000

300

t_icf

t_ocf

t_buf

t_sts

10-pF to 400-pF bus

300

4.7

4

t_sth

t_sps

t_vd(data)

4

SCL low to SDA output valid

3.45

400

ACK signal from SCL low to

SDA (out) low

t_vd(ack)

Valid data time of ACK condition

I²C bus capacitive load

µs

pF

C_b

FAST MODE

f_scl

t_sch

t_scl

t_sp

I²C clock frequency

0

0.6

1.3

400

50

kHz

µs

ns

I²C clock high time

I²C clock low time

I²C spike time

I²C serial-data setup time

I²C serial-data hold time

I²C input rise time

t_sds

t_sdh

t_icr

100

0

20

300

7

TCA9534A

ZHCSCR9C –SEPTEMBER 2014–REVISED FEBRUARY 2017

www.ti.com.cn

I²C Interface Timing Requirements (continued)

over operating free-air temperature range (unless otherwise noted) (see Figure 19)

MIN

MAX

UNIT

20 × (V_DD

/

t_icf

I²C input fall time

I²C output fall time

300

ns

5.5 V)

20 × (V_DD

/

t_ocf

10-pF to 400-pF bus

ns

5.5 V)

t_buf

I²C bus free time between stop and start

I²C start or repeated start condition setup

I²C start or repeated start condition hold

I²C stop condition setup

1.3

µs

ns

t_sts

0.6

t_sth

0.6

t_sps

0.6

t_vd(data)

Valid data time

SCL low to SDA output valid

0.9

ACK signal from SCL low to

SDA (out) low

t_vd(ack)

C_b

Valid data time of ACK condition

I²C bus capacitive load

µs

pF

400

6.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted) (see Figure 20 and Figure 21)

FROM

(INPUT)

TO

(OUTPUT)

PARAMETER

MIN

MAX

UNIT

STANDARD and FAST MODE

t_iv

Interrupt valid time

Interrupt reset delay time

Output data valid

P port

SCL

INT

4

µs

ns

μs

t_ir

t_pv

t_ps

t_ph

SCL

P7–P0

SCL

350

Input data setup time

Input data hold time

P port

100

1

SCL

8

TCA9534A

www.ti.com.cn

ZHCSCR9C –SEPTEMBER 2014–REVISED FEBRUARY 2017

6.8 Typical Characteristics

T_A= 25°C (unless otherwise noted)

40

2.2

2

Vcc = 1.65 V

Vcc = 1.8 V

Vcc = 2.5 V

Vcc = 3.3 V

Vcc = 3.6 V

Vcc = 5 V

Vcc = 5.5V

Vcc = 1.65 V

Vcc = 1.8 V

Vcc = 2.5 V

Vcc = 3.3 V

Vcc = 3.6 V

Vcc = 5 V

Vcc = 5.5V

36

32

28

24

20

16

12

8

1.8

1.6

1.4

1.2

1

0.8

0.6

0.4

0.2

4

0

-40

-15

10

35

60

85

-40

-15

10

35

60

85

T_A- Temperature (°C)

D001

D002

Figure 1. Supply Current vs Temperature for Different

Figure 2. Standby Supply Current vs Temperature for

Different Supply Voltage (V_CC

Supply Voltage (V_CC

)

30

25

20

15

10

5

30

25

20

15

10

5

-40èC

25èC

85èC

-40èC

25èC

85èC

V_CC= 1.65 V

0

1.5

0

2

2.5

3

3.5

4

4.5

5

5.5

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

V_CC- Supply Voltage (V)

V_OL- Output Low Voltage (V)

D003

D004

Figure 3. Supply Current vs Supply Voltage for Different

Temperature (T_A)

Figure 4. I/O Sink Current vs Output Low Voltage for

Different Temperature (T_A) for V_CC= 1.65 V

35

60

50

40

30

20

10

0

-40èC

25èC

85èC

25èC

30

85èC

25

V_CC= 1.8 V

V_CC= 2.5 V

20

15

10

5

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

V_OL- Output Low Voltage (V)

D005

D006

Figure 5. I/O Sink Current vs Output Low Voltage for

Different Temperature (T_A) for V_CC= 1.8 V

Figure 6. I/O Sink Current vs Output Low Voltage for

Different Temperature (T_A) for V_CC= 2.5 V

9

TCA9534A

ZHCSCR9C –SEPTEMBER 2014–REVISED FEBRUARY 2017

www.ti.com.cn

Typical Characteristics (continued)

T_A= 25°C (unless otherwise noted)

70

80

70

60

50

40

30

20

10

0

-40èC

25èC

85èC

25èC

60

85èC

50

V_CC= 3.3 V

V_CC= 5 V

40

30

20

10

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

V_OL- Output Low Voltage (V)

D007

D009

Figure 7. I/O Sink Current vs Output Low Voltage for

Different Temperature (T_A) for V_CC= 3.3 V

Figure 8. I/O Sink Current vs Output Low Voltage for

Different Temperature (T_A) for V_CC= 5 V

300

250

200

150

100

50

90

80

70

60

50

40

30

20

10

0

1.8 V, 1 mA

1.8 V, 10 mA

3.3 V, 1mA

3.3 V, 10 mA

5 V, 1 mA

5 V, 10 mA

-40èC

25èC

85èC

V_CC= 5.5 V

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

-40

-15

10

35

60

85

V_OL- Output Low Voltage (V)

T_A- Temperature (°C)

D010

D011

Figure 9. I/O Sink Current vs Output Low Voltage for

Different Temperature (T_A) for V_CC= 5.5 V

Figure 10. II/O Low Voltage vs Temperature for Different V_CC

and I_OL

20

15

10

5

25

-40èC

25èC

85èC

-40èC

25èC

85èC

20

V_CC= 1.65 V

V_CC= 1.8 V

15

10

5

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

V_CC-V_OH- Output High Voltage (V)

D012

D013

Figure 11. I/O Source Current vs Output High Voltage for

Different Temperature (T_A) for V_CC= 1.65 V

Figure 12. I/O Source Current vs Output High Voltage for

Different Temperature (T_A) for V_CC= 1.8 V

10

TCA9534A

www.ti.com.cn

ZHCSCR9C –SEPTEMBER 2014–REVISED FEBRUARY 2017

Typical Characteristics (continued)

T_A= 25°C (unless otherwise noted)

40

60

50

40

30

20

10

0

-40èC

25èC

85èC

-40èC

25èC

85èC

35

30

25

20

15

10

5

V_CC= 2.5 V

V_CC= 3.3 V

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

V_CC-V_OH- Output High Voltage (V)

D014

D015

Figure 13. I/O Source Current vs Output High Voltage for

Different Temperature (T_A) for V_CC= 2.5 V

Figure 14. I/O Source Current vs Output High Voltage for

Different Temperature (T_A) for V_CC= 3.3 V

70

80

-40èC

25èC

85èC

25èC

70

60

50

40

30

20

10

0

60

85èC

50

V_CC= 5 V

V_CC= 5.5 V

40

30

20

10

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

V_CC-V_OH- Output High Voltage (V)

D016

D017

Figure 15. I/O Source Current vs Output High Voltage for

Different Temperature (T_A) for V_CC= 5 V

Figure 16. I/O Source Current vs Output High Voltage for

Different Temperature (T_A) for V_CC= 5.5 V

400

18

1.65 V, 10 mA

2.5 V, 10 mA

3.6 V, 10 mA

5 V, 10 mA

5.5 V, 10 mA

1.65 V

1.8 V

2.5 V

3.3 V

5 V

5.5 V

350

300

250

200

150

100

50

15

12

9

6

3

0

-40

-15

10

35

60

85

-40

-15

10

35

60

85

T_A- Temperature (°C)

D018

D019

Figure 17. V_CC– V_OHVoltage vs Temperature for Different

V_CC

Figure 18. Δ I_CCvs Temperature for Different V_CC(V_I= V_CC

–

0.6 V)

11

TCA9534A

ZHCSCR9C –SEPTEMBER 2014–REVISED FEBRUARY 2017

www.ti.com.cn

7 Parameter Measurement Information

V_CC

R_L= 1 kW

SDA

DUT

C_L= 50 pF

(see Note A)

SDA LOAD CONFIGURATION

Three Bytes for Complete

Device Programming

Data

Bit 07

(MSB)

Stop

Condition Condition

(P) (S)

Start

Address

Bit 7

Data

Stop

R/W

Bit 0

(LSB)

Address

Bit 6

Address

Bit 1

ACK

(A)

Bit 10 Condition

(MSB)

(LSB)

(P)

t_scl

t_sch

0.7 ´ V_CC

0.3 ´ V_CC

SCL

t_icr

t_sts

t_PHL

t_icf

t_buf

t_sp

t_PLH

0.7 ´ V_CC

0.3 ´ V_CC

SDA

t_icf

t_icr

t_sdh

t_sps

t_sth

t_sds

Repeat

Stop

Condition

Start

Start or

Repeat

Start

Condition

VOLTAGE WAVEFORMS

BYTE

1

DESCRIPTION

I²C address

P-port data

2, 3

A. C_Lincludes probe and jig capacitance.

B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω, t_r/t_f≤ 30 ns.

C. All parameters and waveforms are not applicable to all devices.

Figure 19. I²C Interface Load Circuit and Voltage Waveforms

12

TCA9534A

www.ti.com.cn

ZHCSCR9C –SEPTEMBER 2014–REVISED FEBRUARY 2017

Parameter Measurement Information (continued)

V

CC

R

L

= 4.7 kΩ

INT

DUT

C

L

= 100 pF

(see Note A)

INTERRUPT LOAD CONFIGURATION

ACK

From Slave

ACK

Start

8 Bits

From Slave

Condition

R/W

(One Data Byte)

From Port

Slave Address

Data From Port

Data 2

Data 1

A

1

P

S

0

1

A2 A1 A0

1

A

1

2

3

4

5

6

7

8

A

t

ir

B

t

ir

INT

A

t

iv

t

sps

A

Data

Into

Port

Address

Data 1

Data 2

0.7 × V

0.3 × V

CC

0.7 × V

0.3 × V

CC

SCL

INT

R/W

A

CC

t

iv

t

ir

0.7 × V

0.3 × V

0.7 × V

0.3 × V

CC

INT

P

n

CC

View A−A

A. C_Lincludes probe and jig capacitance.

View B−B

B. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω, t_r/t_f≤ 30 ns.

C. All parameters and waveforms are not applicable to all devices.

Figure 20. Interrupt Load Circuit and Voltage Waveforms

13

TCA9534A

ZHCSCR9C –SEPTEMBER 2014–REVISED FEBRUARY 2017

www.ti.com.cn

Parameter Measurement Information (continued)

Pn

500 Ω

DUT

2 x V_CC

CL = 50 pF

(see Note A)

500 Ω

P-PORT LOAD CONFIGURATION

0.7 x V_CC

0.3 x V_CC

SCL

SDA

P0

A

P3

Slave

ACK

t_pv

(see Note B)

Last Stable Bit

Unstable Data

WRITE MODE (R/W = 0)

0.7 x V_CC

0.3 x V_CC

P0

A

P3

SCL

t_ph

t_ps

0.7 x V_CC

0.3 x V_CC

Pn

READ MODE (R/W = 1)

A. C_Lincludes probe and jig capacitance.

B. t_pvis measured from 0.7 × V_CCon SCL to 50% I/O (Pn) output.

C. All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω, t_r/t_f≤ 30 ns.

D. The outputs are measured one at a time, with one transition per measurement.

E. All parameters and waveforms are not applicable to all devices.

Figure 21. P-Port Load Circuit and Voltage Waveforms

14

TCA9534A

www.ti.com.cn

ZHCSCR9C –SEPTEMBER 2014–REVISED FEBRUARY 2017

8 Detailed Description

8.1 Overview

The TCA9534A is an 8-bit I/O expander for the two-line bidirectional bus (I²C) is designed for 1.65-V to 5.5-V V_CC

operation. It provides general-purpose remote I/O expansion for most micro-controller families via the I²C

interface (serial clock, SCL, and serial data, SDA, pins).

The TCA9534A open-drain interrupt (INT) output is activated when any input state differs from its corresponding

Input Port register state and is used to indicate to the system master that an input state has changed. The INT

pin can be connected to the interrupt input of a micro-controller. By sending an interrupt signal on this line, the

remote I/O can inform the micro-controller if there is incoming data on its ports without having to communicate

via the I²C bus. Thus, the TCA9534A can remain a simple slave device. The device outputs (latched) have high-

current drive capability for directly driving LEDs.

Three hardware pins (A0, A1, and A2) are used to program and vary the fixed I²C slave address and allow up to

eight devices to share the same I²C bus or SMBus.

The system master can reset the TCA9534A in the event of a timeout or other improper operation by cycling the

power supply and causing a power-on reset (POR). A reset puts the registers in their default state and initializes

the I²C /SMBus state machine.

The TCA9534A consists of one 8-bit Configuration (input or output selection), Input Port, Output Port, and

Polarity Inversion (active high or active low) registers. At power on, the I/Os are configured as inputs. However,

the system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The

data for each input or output is kept in the corresponding Input Port or Output Port register. The polarity of the

Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system

master.

The TCA9534A is identical to the TCA9554 except for the removal of the internal I/O pull-up resistors, which

greatly reduces power consumption when the I/Os are held LOW.

15

TCA9534A

ZHCSCR9C –SEPTEMBER 2014–REVISED FEBRUARY 2017

www.ti.com.cn

8.2 Functional Block Diagram

13

Interrupt

Logic

INT

LP Filter

1

A0

2

3

A1

A2

P7−P0

14

15

SCL

SDA

2

Input

Filter

I C Bus

Control

Shift

I/O

8 Bits

Register

Port

Write Pulse

Read Pulse

Power-On

Reset

16

8

VCC

GND

Pin numbers shown are for the PW package.

Figure 22. Functional Block Diagram

Data From

Shift Register

Output Port

Register Data

Configuration

Register

V_CC

Data From

Shift Register

Q1

Q

D

FF

C_{K Q}

Write Configuration

Pulse

Q

D

FF

P0 to P7

Write Pulse

C_{K Q}

Q2

ESD Protection

Diode

Output Port

Register

Input Port

Register

GND

Input Port

Register Data

D

Q

FF

Read Pulse

C_K

Q

To INT

Polarity

Register Data

Data From Shift

Register

D

FF

Q

Write Polarity

Pulse

C_K

Polarity Inversion

Register

At power-on reset, all registers return to default values.

Figure 23. Simplified Schematic Of P0 To P7

16

TCA9534A

www.ti.com.cn

ZHCSCR9C –SEPTEMBER 2014–REVISED FEBRUARY 2017

8.3 Feature Description

8.3.1 I/O Port

When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input. The input

voltage may be raised above V_CCto a maximum of 5.5 V.

If the I/O is configured as an output, Q1 or Q2 is enabled depending on the state of the output port register. In

this case, there are low impedance paths between the I/O pin and either V_CCor GND. The external voltage

applied to this I/O pin must not exceed the recommended levels for proper operation.

8.3.2 Interrupt Output (INT)

An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, t_iv, the

signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original

setting or data is read from the port that generated the interrupt. Resetting occurs in the read mode at the

acknowledge (ACK) bit after the rising edge of the SCL signal. Note that the INT is reset at the ACK just before

the byte of changed data is sent. Interrupts that occur during the ACK clock pulse can be lost (or be very short)

because of the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and

is transmitted as INT.

Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output

cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the

state of the pin does not match the contents of the Input Port register.

The INT output has an open-drain structure and requires pull-up resistor to V_CC

8.4 Device Functional Modes

.

8.4.1 Power-On Reset

When power (from 0 V) is applied to VCC, an internal power-on reset holds the TCA9534A in a reset condition

until V_CChas reached V_PORR. At that point, the reset condition is released and the TCA9534A registers and

SMBus/I²C state machine initialize to their default states. After that, V_CCmust be lowered to below V_PORFand

then back up to the operating voltage for a power-on reset cycle.

8.5 Programming

8.5.1 I²C Interface

The TCA9534A has a standard bidirectional I²C interface that is controlled by a master device in order to be

configured or read the status of this device. Each slave on the I²C bus has a specific device address to

differentiate between other slave devices that are on the same I²C bus. Many slave devices require configuration

upon startup to set the behavior of the device. This is typically done when the master accesses internal register

maps of the slave, which have unique register addresses. A device can have one or multiple registers where

data is stored, written, or read. For more information see the Understanding the I²C Bus application report.

The physical I²C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL lines

must be connected to V_CCthrough a pull-up resistor. The size of the pull-up resistor is determined by the amount

of capacitance on the I²C lines. For further details, see the I²C Pull-up Resistor Calculation application report.

Data transfer may be initiated only when the bus is idle. A bus is considered idle if both SDA and SCL lines are

high after a STOP condition.

Figure 24 and Figure 25 show the general procedure for a master to access a slave device:

1. If a master wants to send data to a slave:

–

Master-transmitter sends a START condition and addresses the slave-receiver.

Master-transmitter sends data to slave-receiver.

Master-transmitter terminates the transfer with a STOP condition.

2. If a master wants to receive or read data from a slave:

–

Master-receiver sends a START condition and addresses the slave-transmitter.

Master-receiver sends the requested register to read to slave-transmitter.

Master-receiver receives data from the slave-transmitter.

17

TCA9534A

ZHCSCR9C –SEPTEMBER 2014–REVISED FEBRUARY 2017

www.ti.com.cn

Programming (continued)

–

Master-receiver terminates the transfer with a STOP condition.

{/[

{5!

5ata Çransfer

{Ç!wÇ

/ondition

{Çhꢀ

/ondition

Figure 24. Definition of Start and Stop Conditions

{5! line stꢀble while {/[ line is high

{/[

1

0

1

!/Y

0

{5!

a{.

.it

[{.

!/Y

.yte: 1010 1010 ( 0x!!h )

Figure 25. Bit Transfer

Table 1 shows the TCA9534A interface definition.

Table 1. Interface Definition Table

BIT

BYTE

7 (MSB)

6

H

5

H

4

H

3

2

1

0 (LSB)

R/W

I²C slave address

Px I/O data bus

L

A2

P3

A1

P2

A0

P1

P7

P6

P5

P4

P0

18

TCA9534A

www.ti.com.cn

ZHCSCR9C –SEPTEMBER 2014–REVISED FEBRUARY 2017

8.6 Register Maps

8.6.1 Device Address

Figure 26 shows the address byte of the TCA9534A.

Slave Address

0

1

A2 A1 A0 R/W

Hardware

Selectable

Fixed

Figure 26. TCA9534A Address

Table 2 shows the TCA9534A address reference.

Table 2. Address Reference

INPUTS

I²C BUS SLAVE ADDRESS

A2

L

A1

L

A0

L

56 (decimal), 38 (hexadecimal)

57 (decimal), 39 (hexadecimal)

58 (decimal), 3A (hexadecimal)

59 (decimal), 3B (hexadecimal)

60 (decimal), 3C (hexadecimal)

61 (decimal), 3D (hexadecimal)

62 (decimal), 3E (hexadecimal)

63 (decimal), 3F (hexadecimal)

L

H

L

H

L

H

L

H

L

H

L

H

The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read

is selected, while a low (0) selects a write operation.

8.6.2 Control Register and Command Byte

Following the successful Acknowledgment of the address byte, the bus master sends a command byte that is

stored in the control register in the TCA9534A (see Figure 27). Two bits of this command byte state the operation

(read or write) and the internal register (input, output, polarity inversion or configuration) that is affected. This

register can be written or read through the I²C bus. The command byte is sent only during a write transmission.

Once a command byte has been sent, the register that was addressed continues to be accessed by reads until a

new command byte has been sent.

0

B2 B1 B0

Figure 27. Control Register Bits

Table 3 shows the TCA9534A command byte.

Table 3. Command Byte Table

CONTROL REGISTER BITS

COMMAND BYTE

REGISTER

PROTOCOL

POWER-UP DEFAULT

(HEX)

B1

0

B0

0

0×00

0×01

0×02

0×03

Input Port

Output Port

Read byte

XXXX XXXX

1111 1111

0000 0000

1111 1111

0

1

Read/write byte

1

0

Polarity Inversion

Configuration

1

19

TCA9534A

ZHCSCR9C –SEPTEMBER 2014–REVISED FEBRUARY 2017

www.ti.com.cn

8.6.3 Register Descriptions

The Input Port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is

defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these

registers have no effect. The default value, X, is determined by the externally applied logic level. See Table 4.

Before a read operation, a write transmission is sent with the command byte to indicate to the I²C device that the

Input Port register is accessed next.

Table 4. Register 0 (Input Port Register) Table

BIT

I7

X

I6

X

I5

X

I4

X

I3

X

I2

X

I1

X

I0

X

DEFAULT

The Output Port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the

Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this

register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. See

Table 5.

Table 5. Register 1 (Output Port Register) Table

BIT

O7

1

O6

1

O5

1

O4

1

O3

1

O2

1

O1

1

O0

1

DEFAULT

The Polarity Inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration

register. If a bit in this register is set (written with 1), the corresponding port pin polarity is inverted. If a bit in this

register is cleared (written with a 0), the corresponding port pin original polarity is retained. See Table 6.

Table 6. Register 2 (Polarity Inversion Register) Table

BIT

N7

0

N6

0

N5

0

N4

0

N3

0

N2

0

N1

0

N0

0

DEFAULT

The Configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1,

the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this register is

cleared to 0, the corresponding port pin is enabled as an output. See Table 7.

Table 7. Register 3 (Configuration Register) Table

BIT

C7

1

C6

1

C5

1

C4

1

C3

1

C2

1

C1

1

C0

1

DEFAULT

20

TCA9534A

www.ti.com.cn

ZHCSCR9C –SEPTEMBER 2014–REVISED FEBRUARY 2017

8.6.3.1 Bus Transactions

Data is exchanged between the master and the TCA9534A through write and read commands.

8.6.3.1.1 Writes

To write on the I²C bus, the master sends a START condition on the bus with the address of the slave, as well

as the last bit (the R/W bit) set to 0, which signifies a write. After the slave sends the acknowledge bit, the master

then sends the register address of the register to which it wishes to write. The slave acknowledges again, letting

the master know it is ready. After this, the master starts sending the register data to the slave until the master

has sent all the data necessary (which is sometimes only a single byte), and the master terminates the

transmission with a STOP condition.

See Table 3 to see list of the internal registers and a description of each one.

Figure 28 shows an example of writing a single byte to a slave register.

ꢄaster controls {5! line

{lave controls {5! line

írite to one register in a device

wegister !ddress ꢁ (8 bits)

5ata .yte to wegister ꢁ (8 bits)

5evice ({lave) !ddress (7 bits)

{

0

1

!2 !1 !0

0

!

.7 .6 .ꢀ .4 .3 .2 .1 .0

!

57 56 5ꢀ 54 53 52 51 50

!

ꢂ

{Ç!wÇ

w/í=0 !ꢃY

!ꢃY

!ꢃY {Çhꢂ

Figure 28. Write to Register

Figure 29 shows an example of writing to the output port register.

SCL

1

2

3

4

5

6

7

8

9

Slave Address

Command Byte

Data to Port

S

0

1

A2 A1 A

0

A

0

1

A

Data 1

A

P

SDA

ACK From Slave

R/W ACK From Slave

Start Condition

Write to Port

Data Out

Data 1 Valid

From Port

t

pv

Figure 29. Write to Output Port Register

Figure 30 shows an example of writing to the configuration or polarity inversion registers.

21

TCA9534A

ZHCSCR9C –SEPTEMBER 2014–REVISED FEBRUARY 2017

www.ti.com.cn

SCL

1

2

3

4

5

6

7

8

9

Slave Address

Command Byte

Data to Register

Data

SDA

S

0

1

A2 A1 A0

0

A

0

1

0

1/0

A

P

Start Condition

R/W

ACK From Slave

Data to

Register

Figure 30. Write to Configuration or Polarity Inversion Registers

8.6.3.1.2 Reads

Reading from a slave is very similar to writing, but requires some additional steps. In order to read from a slave,

the master must first instruct the slave which register it wishes to read from. This is done by the master starting

off the transmission in a similar fashion as the write, by sending the address with the R/W bit equal to 0

(signifying a write), followed by the register address it wishes to read from. When the slave acknowledges this

register address, the master sends a START condition again, followed by the slave address with the R/W bit set

to 1 (signifying a read). This time, the slave acknowledges the read request, and the master releases the SDA

bus but continues supplying the clock to the slave. During this part of the transaction, the master becomes the

master-receiver, and the slave becomes the slave-transmitter.

The master continues to send out the clock pulses, but releases the SDA line so that the slave can transmit data.

At the end of every byte of data, the master sends an ACK to the slave, letting the slave know that it is ready for

more data. When the master has received the number of bytes it is expecting, it sends a NACK, signaling to the

slave to halt communications and release the bus. The master follows this up with a STOP condition.

See Table 3 for the list of the internal registers and a description of each one.

If a read is requested by the master after a POR without first setting the command byte via a write, the device will

NACK until a command byte-register address is set as described above.

Figure 31 shows an example of reading a single byte from a slave register.

ꢃaster controls {5! line

{lave controls {5! line

wead from one register in a device

5evice ({lave) !ddress (7 bits)

wegister !ddress ꢁ (8 bits)

5evice ({lave) !ddress (7 bits)

5ata .yte from wegister ꢁ (8 bits)

57 56 5ꢀ 54 53 52 51 50 ꢁ!

{

0

1

!2 !1 !0

0

!

.7 .6 .ꢀ .4

.2 .1 .0

!

{r

0

1

!2 !1 !0

1

!

ꢂ

.3

wꢄí=1

{Ç!wÇ

!/Y

!/Y wepeated {Ç!wÇ

!/Y

ꢁ!/Y {Çhꢂ

wꢄí=0

Figure 31. Read From Register

Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number

of data bytes received in one read transmission, but when the final byte is received, the bus master must not

acknowledge the data. See Figure 32.

22

TCA9534A

www.ti.com.cn

ZHCSCR9C –SEPTEMBER 2014–REVISED FEBRUARY 2017

1

2

3

4

5

6

7

8

9

SCL

Data From Port

Data 1

Slave Address

Data From Port

Data 4

S

0

1

A2 A1 A0

R/W

1

A

P

NA

A

SDA

Start

Condition

NACK From

Master

ACK From

Slave

ACK From

Master

Stop

Condition

Read From

Port

Data Into

Port

Data 2

Data 3

Data 4

Data 5

t

ph

t

ps

INT

t

iv

t

ir

A. This figure assumes the command byte has previously been programmed with 00h.

B. Transfer of data can be stopped at any moment by a Stop condition.

C. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address

call and actual data transfer from the P port. See the Reads section for these details.

Figure 32. Read From Input Port Register

23

TCA9534A

ZHCSCR9C –SEPTEMBER 2014–REVISED FEBRUARY 2017

www.ti.com.cn

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

Figure 33 shows an application in which the TCA9534A can be used.

IO Expanders such as the TCA9534A are commonly used to obtain more general purpose I/Os. There are many

common uses for these additionial I/Os:

•

Inputs from other ICs, such as interrupt signals from sensors

Inputs from physical buttons (for detecting button presses)

Outputs to control RESET or ENABLE signals on other ICs

Outputs for controlling LEDs for visual feedback to a user

9.2 Typical Application

V

CC

100 kΩ

2 kΩ

16

10 kΩ⁽¹⁾10 kΩ⁽¹⁾

(x 3)

10 kΩ

V

CC

VCC

15

14

4

Subsystem 1

SDA

SCL

INT

SDA

P0

P1

(e.g., temperature sensor)

Master

Controller

SCL

INT

5

INT

13

6

7

P2

P3

RESET

GND

Subsystem 2

(e.g., counter)

TCA9534A

9

P4

10

A

P5

P6

P7

3

2

A2

Controlled Device

(e.g., CBT device)

11

12

ENABLE

A1

A0

1

B

GND

ALARM

8

Subsystem 3

(e.g., alarm system)

V

CC

P6 and P7 are not used and must be configured as outputs.

Figure 33. Application Schematic

24

TCA9534A

www.ti.com.cn

ZHCSCR9C –SEPTEMBER 2014–REVISED FEBRUARY 2017

Typical Application (continued)

9.2.1 Design Requirements

9.2.1.1 Calculating Junction Temperature and Power Dissipation

When designing with the TCA9534A, it is important that the Recommended Operating Conditions not be violated.

Many of the parameters of this device are rated based on junction temperature. So junction temperature must be

calculated in order to verify that safe operation of the device is met. The basic equation for junction temperature

is shown in Equation 1.

T_j= T_A+ q ´ P

(

)

JA

d

(1)

θ_JAis the standard junction to ambient thermal resistance measurement of the package, as seen in Thermal

Information table. P_dis the total power dissipation of the device, and the approximation is shown in Equation 2.

P » I_{CC_STATIC}´ V_CC

(

+

P_{d_PORT _L}

+

P_{d_PORT _H}

)

d

å

(2)

Equation 2 is the approximation of power dissipation in the device. The equation is the static power plus the

summation of power dissipated by each port (with a different equation based on if the port is outputting high, or

outputting low. If the port is set as an input, then power dissipation is the input leakage of the pin multiplied by

the voltage on the pin). Note that this ignores power dissipation in the INT and SDA pins, assuming these

transients to be small. They can easily be included in the power dissipation calculation by using Equation 3 to

calculate the power dissipation in INT or SDA while they are pulling low, and this gives maximum power

dissipation.

P_{d_PORT _L}= I ´ V_OL

(

OL

)

(3)

Equation 3 shows the power dissipation for a single port which is set to output low. The power dissipated by the

port is the V_OLof the port multiplied by the current it is sinking.

P_{d_PORT _H}= I

(

´ V - V_OH

(

CC

)

OH

(4)

Equation 4 shows the power dissipation for a single port which is set to output high. The power dissipated by the

port is the current sourced by the port multiplied by the voltage drop across the device (difference between V_CC

and the output voltage).

9.2.1.2 Minimizing I_CCWhen I/Os Control LEDs

When the I/Os are used to control LEDs, normally they are connected to V_CCthrough a resistor as shown in

Figure 33. For a P-port configured as an input, I_CCincreases as V_Ibecomes lower than V_CC. The LED is a diode,

with threshold voltage V_T, and when a P-port is configured as an input the LED is off but V_Iis a V_Tdrop below

V_CC

.

For battery-powered applications, it is essential that the voltage of P-ports controlling LEDs is greater than or

equal to V_CCwhen the P-ports are configured as input to minimize current consumption. Figure 34 shows a high-

value resistor in parallel with the LED. Figure 35 shows V_CCless than the LED supply voltage by at least V_T.

Both of these methods maintain the I/O V_Iat or above V_CCand prevents additional supply current consumption

when the P-port is configured as an input and the LED is off.

V

CC

LED

100 k

V

CC

LEDx

Figure 34. High-Value Resistor in Parallel With LED

25

TCA9534A

ZHCSCR9C –SEPTEMBER 2014–REVISED FEBRUARY 2017

www.ti.com.cn

Typical Application (continued)

5 V

3.3 V

LED

V

CC

LEDx

Figure 35. Device Supplied by a Lower Voltage

9.2.2 Detailed Design Procedure

The pull-up resistors, R_P, for the SCL and SDA lines need to be selected appropriately and take into

consideration the total capacitance of all slaves on the I²C bus. The minimum pull-up resistance is a function of

V_CC, V_OL,(max), and I_OLas shown in Equation 5.

V_CC- V_OL(max)

=

R_p(min)

I_OL

(5)

The maximum pull-up resistance is a function of the maximum rise time, t_r(300 ns for fast-mode operation, f_SCL

400 kHz) and bus capacitance, C_bas shown in Equation 6.

=

t_r

R_p(max)

=

0.8473´C_b

(6)

The maximum bus capacitance for an I²C bus must not exceed 400 pF for standard-mode or fast-mode

operation. The bus capacitance can be approximated by adding the capacitance of the TCA9534A, C_ifor SCL or

C_iofor SDA, the capacitance of wires, connections, traces, and the capacitance of additional slaves on the bus.

9.2.3 Application Curves

25

20

15

10

5

1.8

1.6

1.4

1.2

1

Standard-mode

Fast-mode

0.8

0.6

0.4

0.2

0

V_CC> 2V

V_CC<= 2

0

50

100 150 200 250 300 350 400 450

C_b(pF)

0

0.5

1

1.5

2

2.5

V_CC(V)

3

3.5

4

4.5

5

5.5

D008

D009

Standard-mode

Fast-mode

V_OL= 0.2*V_CC, I_OL= 2 mA when V_CC≤ 2 V

(f_SCL= 100 kHz, t_r= 1 µs)

(f_SCL= 400 kHz, t_r= 300 ns)

V_OL= 0.4 V, I_OL= 3 mA when V_CC> 2 V

Figure 36. Maximum Pull-Up resistance (R_p(max)) vs Bus

Capacitance (C_b)

Figure 37. Minimum Pull-Up Resistance (R_p(min)) vs Pull-Up

Reference Voltage (V_CC

)

26

TCA9534A

www.ti.com.cn

ZHCSCR9C –SEPTEMBER 2014–REVISED FEBRUARY 2017

10 Power Supply Recommendations

10.1 Power-On Reset Requirements

In the event of a glitch or data corruption, the TCA9534A can be reset to its default conditions by using the

power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset.

This reset also happens when the device is powered on for the first time in an application.

The two types of power-on reset are shown in and Figure 38.

V

CC

Ramp-Down

Ramp-Up

V

CC_TRR

V

drops below V_PORF– 50 mV

CC

Time

Time to Re-Ramp

V

CC_FT

CC_RT

Figure 38. V_CCis Lowered Below the POR Threshold, then Ramped Back Up to V_CC

Table 8 specifies the performance of the power-on reset feature for the TCA9534A for both types of power-on

reset.

Table 8. Recommended Supply Sequencing and Ramp Rates⁽¹⁾

PARAMETER

MIN

1

MAX UNIT

V_{CC_FT}

V_{CC_RT}

Fall rate

See Figure 38

2000

ms

Rise rate

0.1

Time to re-ramp (when V_CCdrops to V_{POR_MIN}– 50 mV or when

V_CCdrops to GND)

V_{CC_TRR}

V_{CC_GH}

V_{CC_MV}

V_{CC_GW}

See Figure 38

See Figure 39

1

μs

V

Level that V_CCPcan glitch down to, but not cause a functional

disruption when V_{CCX_GW}= 1 μs

1.2

10

The minimum voltage that V_CCcan glitch down to without causing

a reset (V_{CC_GH}must not be violated)

1.5

V

Glitch width that does not cause a functional disruption when

V_{CCX_GH}= 0.5 × V_CCx

μs

(1) All supply sequencing and ramp rate values are measured at T_A= 25°C

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width

(V_{CC_GW}) and height (V_{CC_GH}) are dependent on each other. The bypass capacitance, source impedance, and

device impedance are factors that affect power-on reset performance. Figure 39 and Table 8 provide more

information on how to measure these specifications.

V

CC

V

CC_GH

V

CC_MV

Time

V

CC_GW

Figure 39. Glitch Width and Glitch Height

27

TCA9534A

ZHCSCR9C –SEPTEMBER 2014–REVISED FEBRUARY 2017

www.ti.com.cn

V_PORis critical to the power-on reset. V_PORis the voltage level at which the reset condition is released and all the

registers and the I²C/SMBus state machine are initialized to their default states. The value of V_PORdiffers based

on the V_CCbeing lowered to or from 0. Figure 40 and Table 8 provide more details on this specification.

V_CC

V_PORR

V_PORF

Time

POR

Time

Figure 40. V_POR

28

TCA9534A

www.ti.com.cn

ZHCSCR9C –SEPTEMBER 2014–REVISED FEBRUARY 2017

11 Layout

11.1 Layout Guidelines

For printed circuit board (PCB) layout of the TCA9534A, common PCB layout practices must be followed but

additional concerns related to high-speed data transfer such as matched impedances and differential pairs are

not a concern for I²C signal speeds.

In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from

each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher

amounts of current that commonly pass through power and ground traces. By-pass and de-coupling capacitors

are commonly used to control the voltage on the VCC pin, using a larger capacitor to provide additional power in

the event of a short power supply glitch and a smaller capacitor to filter out high-frequency ripple. These

capacitors must be placed as close to the TCA9534A as possible. These best practices are shown in Figure 41.

For the layout example provided in Figure 41, it is possible to fabricate a PCB with only 2 layers by using the top

layer for signal routing and the bottom layer as a split plane for power (V_CC) and ground (GND). However, a 4

layer board is preferable for boards with higher density signal routing. On a 4 layer PCB, it is common to route

signals on the top and bottom layer, dedicate one internal layer to a ground plane, and dedicate the other internal

layer to a power plane. In a board layout using planes or split planes for power and ground, vias are placed

directly next to the surface mount component pad which needs to attach to V_CCor GND and the via is connected

electrically to the internal layer or the other side of the board. Vias are also used when a signal trace needs to be

routed to the opposite side of the board, but this technique is not demonstrated in Figure 41.

11.2 Layout Example

LEGEND

Power or GND Plane

To I2C Master

VIA to Power Plane

V_CC

VIA to GND Plane

By-pass/De-coupling

capacitors

1

2

3

4

5

6

7

8

A0

VCC

SDA

SCL

INT

P7

16

15

14

13

12

11

10

9

A1

A2

P0

P1

P2

P6

P3

P5

GND

P4

GND

Figure 41. TCA9534A Layout

29

TCA9534A

ZHCSCR9C –SEPTEMBER 2014–REVISED FEBRUARY 2017

www.ti.com.cn

12 器件和文档支持

12.1 相关文档ꢀ

请参阅如下相关文档：

•

《I2C 总线上拉电阻器计算》

《I2C 总线在采用中继器时的最高时钟频率》

《逻辑器件简介》

《理解 I2C 总线》

《IO 扩展器 EVM 用户指南》

《为新设计挑选合适的 I2C 器件》

12.2 接收文档更新通知

如需接收文档更新通知，请访问 ti.com 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品

信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

12.4 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.5 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

12.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修

订此文档。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航。

30

PACKAGE OUTLINE

PW0016A

TSSOP - 1.2 mm max height

S

C

A

L

E

2

.

5

0

SMALL OUTLINE PACKAGE

SEATING

PLANE

C

6.6

6.2

TYP

A

0.1 C

PIN 1 INDEX AREA

14X 0.65

16

1

2X

5.1

4.9

4.55

NOTE 3

8

9

0.30

16X

4.5

4.3

NOTE 4

1.2 MAX

0.19

B

0.1

C A B

(0.15) TYP

SEE DETAIL A

0.25

GAGE PLANE

0.15

0.05

0.75

0.50

A

20

0 -8

DETAIL A

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153.

www.ti.com

EXAMPLE BOARD LAYOUT

PW0016A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

SYMM

16X (1.5)

(R0.05) TYP

16

1

16X (0.45)

SYMM

14X (0.65)

8

9

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

15.000

(PREFERRED)

SOLDER MASK DETAILS

4220204/A 02/2017

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

PW0016A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

16X (1.5)

SYMM

(R0.05) TYP

16

1

16X (0.45)

SYMM

14X (0.65)

8

9

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 10X

4220204/A 02/2017

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

GENERIC PACKAGE VIEW

DW 16

7.5 x 10.3, 1.27 mm pitch

SOIC - 2.65 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224780/A

www.ti.com

PACKAGE OUTLINE

DW0016A

SOIC - 2.65 mm max height

S

C

A

L

E

1

.

5

0

SOIC

C

10.63

9.97

SEATING PLANE

TYP

PIN 1 ID

AREA

0.1 C

A

14X 1.27

16

1

2X

10.5

10.1

NOTE 3

8.89

8

9

0.51

0.31

16X

7.6

7.4

B

2.65 MAX

0.25

C A B

NOTE 4

0.33

0.10

TYP

SEE DETAIL A

0.25

GAGE PLANE

0.3

0.1

0 - 8

1.27

0.40

DETAIL A

TYPICAL

(1.4)

4220721/A 07/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm, per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

5. Reference JEDEC registration MS-013.

www.ti.com

EXAMPLE BOARD LAYOUT

DW0016A

SOIC - 2.65 mm max height

SOIC

16X (2)

SEE

DETAILS

SYMM

1

16

16X (0.6)

SYMM

14X (1.27)

R0.05 TYP

9

8

(9.3)

LAND PATTERN EXAMPLE

SCALE:7X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4220721/A 07/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DW0016A

SOIC - 2.65 mm max height

SOIC

16X (2)

SYMM

1

16

16X (0.6)

SYMM

14X (1.27)

R0.05 TYP

8

9

(9.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:7X

4220721/A 07/2016

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TCA9534ADWT
厂家：	TEXAS INSTRUMENTS
描述：	具有中断和配置寄存器的 8 位 1.65V 至 5.5V I2C/SMBus I/O 扩展器 \| DW \| 16 \| -40 to 85 时钟光电二极管外围集成电路
文件：	总42页 (文件大小：1743K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TCA9534ADWT [TI]

相关型号：

TCA9534APWR

TCA9534DWR

TCA9534DWT

TCA9534PWR

TCA9535

TCA9535DBR

TCA9535DBT

TCA9535MRGER

TCA9535PWR

TCA9535RGER

TCA9535RTWR

TCA9535_16