TCA39416DDFR [TI]
具有上升时间加速器的超低电压 I3C 转换器 | DDF | 8 | -40 to 125;
| 型号： | TCA39416DDFR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有上升时间加速器的超低电压 I3C 转换器 | DDF | 8 | -40 to 125 转换器 |
| 文件： | 总26页 (文件大小：1304K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TCA39416
ZHCSPC7A –DECEMBER 2022 –REVISED JULY 2023
TCA39416 具有上升时间加速器的超低电压I3C 转换器
1 特性
3 说明
• 适用于I3C、I2C、SMBus 和SPI 应用的2 位双电
源双向转换器
• 在无方向引脚的情况下提供双向电压转换
• 高阻抗输出Ax 和Bx 引脚（当
OE = 0V 或VCC = 0V 时）
• Ax 和Bx 引脚上配有内部10kΩ上拉电阻器
TCA39416 是一款具有输出使能 (OE) 输入以及上升沿
和下降沿加速器的 2 位双向 MIPI I3C v1.1.1、I2C、
SMBus 和 SPI 电压电平转换器。该器件在 A 侧和 B
侧的工作电压范围为 0.72V 至 1.98V，VCCA 必须低于
VCCB，才能正常运行。有了此限制，该器件能够在典
型的 1V、1.2V 和 1.8V 电源轨之间进行任何高低逻辑
信号电平切换。
• A 端口和B 端口上的电压均为0.72V 至1.98V；
V
CCA ≤VCCB
OE 输入引脚的基准为 VCCA，可以直接连接至 VCCA
，
• 与MIPI I3C 兼容、支持高达12.5MHz 的速度
• VCC 隔离特性：如果任何一个VCC 输入接地
(GND)，则A 端口和B 端口均处于高阻抗状态
• 无需电源定序：VCCA 或VCCB 均可优先斜升
• 低至2.5µA 的Ioff（当VCCA 或VCCB = 0V 时）
• OE 输入可直接连接至VCCA，也可通过GPIO 进行
控制
但也可以承受 1.98V 的电压。用户还可以对 OE 引脚
进行控制，将其设置为低电平，使所有 Ax（A1、A2）
和Bx（B1、B2）引脚均处于高阻抗状态，从而显著减
少静态电流消耗。
TCA39416 与 12.5MHz I3C 速度兼容，并且能够通过
两个器件支持高速 SPI 应用。它还可在正常 I2C 和
SMBus 配置下为传统的 I2C 总线/SMBus 应用实现双
向电压电平转换。
• 闩锁性能超过100mA，符合JESD 78 II 类规范
• ESD 保护性能超过JESD 22 规范要求
– 4000V 人体放电模型(A114-B)
– 1500V 充电器件模型(C101)
TCA39416 在 Ax 和 Bx 上使用内部 10kΩ 上拉电阻器
充当高电平保持器，并在总线为高电平时根据各自的
VCC 电压启用。
2 应用
封装信息
• 服务器
• 可穿戴设备
• 个人电子产品
封装(1)
X2SON (8)
SOT-23-T (8)
封装尺寸(2)
器件型号
TCA39416
1mm x 1.35mm
2.9mm × 2.8mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
(2) 封装尺寸（长× 宽）为标称值，并包括引脚（如适用）。
VCCA
VCCB
Processor
Peripheral
I3C Translator
简化版应用
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCPS282
TCA39416
www.ti.com.cn
ZHCSPC7A –DECEMBER 2022 –REVISED JULY 2023
Table of Contents
8.2 Functional Block Diagram.........................................12
8.3 Feature Description...................................................12
8.4 Device Functional Modes..........................................14
9 Application and Implementation..................................15
9.1 Application Information............................................. 15
9.2 Typical Application.................................................... 15
9.3 Power Supply Recommendations.............................16
9.4 Layout....................................................................... 17
10 Device and Documentation Support..........................18
10.1 Documentation Support.......................................... 18
10.2 接收文档更新通知................................................... 18
10.3 支持资源..................................................................18
10.4 Trademarks.............................................................18
10.5 静电放电警告.......................................................... 18
10.6 术语表..................................................................... 18
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Timing Requirements..................................................7
6.7 Switching Characteristics............................................8
6.8 Typical Characteristics................................................9
7 Parameter Measurement Information..........................10
7.1 Voltage Waveforms................................................... 11
8 Detailed Description......................................................12
8.1 Overview...................................................................12
Information.................................................................... 18
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (December 2022) to Revision A (July 2023)
Page
• 删除了封装信息 表中X2SON 的产品预发布说明...............................................................................................1
• Added thermal information for DTW................................................................................................................... 5
• Deleted sentence "When VCCA is same as VCCB,…" from the Power Supply Recommendations .................. 16
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SCPS282
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ZHCSPC7A –DECEMBER 2022 –REVISED JULY 2023
5 Pin Configuration and Functions
B2
GND
VCCA
A2
1
2
3
8
7
6
5
B1
B2
GND
VCCA
A2
1
2
3
4
8
7
6
5
B1
VCCB
OE
VCCB
OE
A1
4
A1
Not to scale
Not to scale
图5-1. 8-PIN DTW
图5-2. 8-PIN DDF
(Top View)
(Top View)
表5-1. Pin Functions
PIN
NO.
TYPE
DESCRIPTION
NAME
DTW, DDF
B2
1
I/O
I/O
Input/output B. Referenced to VCCB
Input/output B. Referenced to VCCB
Ground.
.
.
B1
8
2
3
5
4
GND
VCCA
A1
GND
Power
I/O
A-port supply voltage. 0.72 V ≤VCCA ≤1.98 V.
Input/output A. Referenced to VCCA
Input/output A. Referenced to VCCA
.
.
A2
I/O
Output enable (active High). Pull OE low to place all outputs in 3-state mode.
Referenced to VCCA
B-port supply voltage. 0.72 V ≤VCCB ≤1.98 V.
OE
6
7
I
.
VCCB
Power
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English Data Sheet: SCPS282
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ZHCSPC7A –DECEMBER 2022 –REVISED JULY 2023
6 Specifications
6.1 Absolute Maximum Ratings
over recommended operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
MAX
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
UNIT
V
VCCA
VCCB
Supply voltage range
Supply voltage range
V
A port
B port
A port
B port
A port
B port
VI < 0
VO < 0
VI
Input voltage range(2)
V
V
V
Voltage range applied to any output
VO
VO
in the high-impedance or power-off state(2)
Voltage range applied to any output in the high or low state(2) (3)
IIK
IOK
IO
Input clamp current
mA
mA
mA
mA
°C
–50
–50
±50
Output clamp current
Continuous output current
Continuous current through VCCA, VCCB, or GND
Storage temperature
±100
150
Tstg
Ptot
–65
Total power dissipation
100
mW
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCCA and VCCB are provided in the recommended operating conditions table.
6.2 ESD Ratings
VALUE
±4000
±1500
UNIT
V
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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English Data Sheet: SCPS282
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ZHCSPC7A –DECEMBER 2022 –REVISED JULY 2023
6.3 Recommended Operating Conditions
over recommended operating free-air temperature range (unless otherwise noted)
VCCA
VCCB
MIN
0.72
0.72
MAX
1.98
1.98
UNIT
V
VCCA
VCCB
Supply voltage
Supply voltage
V
A-port I/Os, B-port
I/Os, OE
VI
Input voltage
0 V to 1.98 V
0 V to 1.98 V
0
VCCA × 0.65
0
1.98
1.98
V
V
V
High-level
input voltage
VIH
VIL
OE input
OE input
0.72 V to 1.98 V
0.72 V to 1.98 V
Low-level
input voltage
0.72 V to 1.98 V
0.72 V to 1.98 V
0.72 V to 1.98 V
0.72 V to 1.98 V
VCCA × 0.35
Input transition rise and fall rate
Operating free-air temperature
5
ns/V
°C
Δt/ΔV
TA
125
–40
6.4 Thermal Information
TCA39416
TCA39416
THERMAL METRIC(1)
DDF (SOT-23)
8 PINS
220.8
DTW (X2SON)
8 PINS
261.6
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
132.4
128.6
138.3
146.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
24.2
8.2
137.2
146.1
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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ZHCSPC7A –DECEMBER 2022 –REVISED JULY 2023
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)1 2 3
TEST
CONDITIONS
PARAMETER
VCCA
VCCB
MIN
0.3
TYP
0.55
0.5
MAX
0.65
0.6
UNIT
UVLO Rising
Threshold
VUVLO for VCCA and VCCB are
independent
VUVLO_RISE
VUVLO_FALL
0 V to 1.98 V
0 V to 1.98 V
0 V to 1.98 V
0 V to 1.98 V
V
V
V
V
UVLO Falling
Threshold
VUVLO for VCCA and VCCB are
independent
0.25
4
RTA Activation
Threshold
VCCI
×
VCCI
×
VRTA
0.72 V to 1.98 V 0.72 V to 1.98 V
0.72 V to 1.98 V 0.72 V to 1.98 V
0.30
0.45
4
FTA Activation
Threshold
VCCI
×
VCCI
×
VFTA
0.40
0.70
RPU
II
0.72 V to 1.98 V 0.72 V to 1.98 V
0.72 V to 1.98 V 0.72 V to 1.98 V
0.72 V to 1.98 V 0.72 V to 1.98 V
7.5
10
±0.1
0
15
±1
VI = VCC –0.15 V
VI = VCCA or GND
OE less than VIL
kΩ
μA
μA
OE
IOZ
A or B port
±2.5
VI = 1.98 V, VO = 0 V
(TA ≤85℃)
A port
B port
A port
B port
0 V
0 V to 1.98 V
0 V
±0.1
±0.1
±0.1
±0.1
±0.5
±0.5
±2.5
±2.5
VI = 1.98 V, VO = 0 V
(TA ≤85℃)
0 V to 1.98 V
0 V
Ioff
μA
VI = 1.98 V, VO = 0 V
(TA ≤125℃)
0 V to 1.98 V
0 V
VI = 1.98 V, VO = 0 V (TA
≤125℃)
0 V to 1.98 V
VI = VO = 0 V to 1.98 V,
IO = 0,
OE = 0 V
VCCA
VCCB
2.5
2.5
20
20
ICC_OFF
0.72 V to 1.98 V 0.72 V to 1.98 V
μA
VI = VO = 0 V to 1.98 V,
IO = 0,
OE = 0 V
0.72 V
1.1 V
0.72 V to 1.98 V
1.1 V to 1.98 V
1.32 V to 1.98 V
1.98 V
1.5
2
40
25
25
28
24
26
26
28
46
48
48
54
20
28
18
3
VI = VO = 0 V or VCCI
IO = 0,
OE = VCCA
,
,
,
ICCA
μA
μA
1.32 V
1.98 V
0.72 V
1.1 V
3
4
0.72 V to 1.98 V
1.1 V to 1.98 V
1.32 V to 1.98 V
1.98 V
1
VI = VO = 0 V or VCCI
IO = 0,
OE = VCCA
1.5
2
ICCB
1.32 V
1.98 V
0.72 V
1.1 V
2.5
1
0.72 V to 1.98 V
1.1 V to 1.98 V
1.32 V to 1.98 V
1.98 V
VI = VO = 0 V or VCCI
IO = 0,
OE = VCCA
2
ICCA + ICCB
μA
1.32 V
1.98 V
1.8 V
4
6
VI = 0.1 V, IO = 2 mA
VI = 0.1 V, IO = 2 mA
VI = 0.1 V, IO = 2 mA
1.8 V
8
Ron
0.8 V, 1.8 V
1.2 V, 1.8 V
1.98 V
1.8 V, 0.8 V
1.8 V, 1.2 V
1.98 V
10
8
Ω
CI
OE
2
pF
pF
Cio
A or B port
0 V, 1 V, 1.98 V 0 V, 1 V, 1.98 V
4
8
(1) VCCI is the VCC associated with the input port.
(2) VCCO is the VCC associated with the output port.
(3) VCCA must be less than or equal to VCCB, and VCCA must not exceed 1.98 V.
(4) RTA is "rise time accelerator" and FTA is "fall time accelerator".
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English Data Sheet: SCPS282
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6.6 Timing Requirements
over operating free-air temperature range (unless otherwise noted). Typical specifications are at TA = 25 °C unless otherwise
noted.
PARAMETER
Time from VRTA to RTA disabling
Pulse width
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Ax, Bx = Hi-Z
tRTA
tW
80
210
ns
EN = VCC
data inputs
35
ns
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ZHCSPC7A –DECEMBER 2022 –REVISED JULY 2023
6.7 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
VCCA = 0.72 V
MIN
TYP
MAX
UNIT
8
7
20
18
13
9
VCCA = 0.8 V
VCCA = 1.0 V
VCCA = 1.2 V
VCCA = 1.8 V
VCCA = 0.72 V
VCCA = 0.8 V
VCCA = 1.0 V
VCCA = 1.2 V
VCCA = 1.8 V
VCCB = 0.72 V
VCCB = 0.8 V
VCCB = 1.0 V
VCCB = 1.2 V
VCCB = 1.8 V
VCCB = 0.72 V
VCCB = 0.8 V
VCCB = 1.0 V
VCCB = 1.2 V
VCCB = 1.8 V
tPHL
tPLH
tPHL
tPLH
A
A
B
B
B
B
A
A
4
ns
2
1
5
8
30
16
10
8
6
3
ns
ns
ns
2
0.5
9
4
18
15
16
17
18
35
18
16
15
14
3
8
8
2
2
9
2
1
0.5
0.5
tSK(O)-RISE
tSK(O)-FALL
ten
Rising Channel-to-channel skew (Propagation)
Falling Channel-to-channel skew (Propagation)
ns
ns
ns
ns
3
OE
OE
A or B
A or B
40
30
18
5
124
68
42
22
15
12
9
tdis
VCCA = 0.72 V
VCCA = 0.8 V
VCCA = 1.0 V
VCCA = 1.2 V
VCCA = 1.8 V
VCCB = 0.72 V
VCCB = 0.8 V
VCCB = 1.0 V
VCCB = 1.2 V
VCCB = 1.8 V
VCCA = 0.72 V
VCCA = 0.8 V
VCCA = 1.0 V
VCCA = 1.2 V
VCCA = 1.8 V
VCCB = 0.72 V
VCCB = 0.8 V
VCCB = 1.0 V
VCCB = 1.2 V
VCCB = 1.8 V
trA
trB
tfA
B-port
A-port
B-port
A-port
B-port
A-port
B-port
4
ns
ns
ns
2
1.5
6
34
21
15
13
8
4
3
2
1.5
4
12
11
11
11
12
9
4
3
3
4
4
4
9
tfB
A-port
3
10
11
11
26
ns
3
2
fdata
Data rate
0.06
Mbps
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6.8 Typical Characteristics
20
20
18
16
14
12
10
8
125ꢀC
125ꢀC
85ꢀC
25ꢀC
-40ꢀC
18
85ꢀC
25ꢀC
-40ꢀC
16
14
12
10
8
6
6
4
4
2
2
0
0
0.72
0.92
1.12
1.32
VCCB (V)
1.52
1.72
1.92
0.72
0.92
1.12
1.32
VCCA (V)
1.52
1.72
1.92
图6-1. ICCA (μA) vs VCCA (V)
图6-2. ICCB (μA) vs VCCB (V)
22
125ꢀC
85ꢀC
25ꢀC
-40ꢀC
20
18
16
14
12
0.8
1
1.2
1.4
1.6
1.8
1.98
VCCA (V)
V
CCA ≤VCCB
图6-3. RON (Ω) vs Min(VCCA, VCCB) (V)
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ZHCSPC7A –DECEMBER 2022 –REVISED JULY 2023
7 Parameter Measurement Information
Following load circuit is used to measure pulse duration, propagation delay, output rise-time and fall-time
measurement.
(D)
VCC
VEXT
RL
VIN
VOUT
Device
under test
Pulse generator
(C)
(B)
CL
RT
RL
图7-1. Load Circuit
A. Load resistance RL = 1 MΩ for measuring data rate, pulse width, propagation delay and output rise and fall measurements. RL = 50 kΩ
for measuring enable and disable times.
B. RT termination resistance should be equal to ZOUT of pulse generators.
C. CL Load capacitance includes probe and jig capacitance. CL = 15 pF when on the B-side.
D. VEXT External voltage for measuring switching times.
E. All input pulses are supplied by generators having the following characteristics: PRR ≤26 MHz, ZO = 50 Ω, slew rate ≥1 V/ns.
F. VCCI is the VCC associated with the input port.
G. VCCO is the VCC associated with the output port.
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7.1 Voltage Waveforms
VCCI
Input
V
CCI / 2
VCCI / 2
0 V
tPLH
tPHL
VOH
0.8 × VCCO
V
CCO / 2
tr
Output
VCCO / 2
0.2 × V
CCO
VOL
tf
图7-2. Propagation Delay Times
spacer
VCCA
VCCA / 2
VCCA / 2
OE input
0 V
tPLZ
tPZL
VOH
Output
Waveform 1
S1 at 2 × VCCO
VCCO / 2
VCCO × 0.2
VOL
(see Note 2)
tPHZ
tPZH
VOH
0 V
Output
Waveform 2
S1 at GND
VCCO × 0.8
VCCO / 2
(see Note 2)
1. CL includes probe and jig capacitance.
2. Waveform 1 in 图7-3 is for an output with internal such that the output is high, except when OE is high (see 图7-1). Waveform 2 in
图7-3 is for an output with conditions such that the output is low, except when OE is high.
3. All input pulses are supplied by generators having the following characteristics: PRR ≤26 MHz, ZO = 50 Ω, dv/dt ≥1 V/ns.
4. The outputs are measured one at a time, with one transition per measurement.
5. tPLZ and tPHZ are the same as tdis
.
6. tPZL and tPZH are the same as ten
.
7. tPLH and tPHL are the same as tpd
.
8. VCCI is the VCC associated with the input port.
9. VCCO is the VCC associated with the output port.
图7-3. Enable and Disable Times
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8 Detailed Description
8.1 Overview
The TCA39416 device is a directionless voltage-level translator specifically designed for translating logic voltage
levels. The device is MIPI I3C v1.1.1 compatible supporting data rates up to 12.5 Mbps in I3C Single Data Rate
(SDR) mode and 25 Mbps in I3C High Data Rate (HDR-DDR) mode. Like SDR Mode, HDR-DDR Mode uses
SCL as a clock; however unlike SDR, data is sampled on both edges of clock SCL effectively doubling the data
rate achieving 25 Mbps.
The A and B ports are able to accept I/O voltages ranging from 0.72 V to 1.98 V. VCCA must be ≤ VCCB to
ensure proper operation. The device is a pass-gate architecture with edge-rate accelerators (one-shots) to
improve the overall data rate and supports both high speed push-pull and low speed open-drain operation.
MIPI I3C specification requires dynamic pull-up control to switch between “strong pull-up” and “weak pull-
up” to optimize open-drain and push-pull timing requirements. In TCA39416, the internal 10-kΩ pull-up
resistors on Ax and Bx pins are enabled based on respective VCC voltage and OE input and act as High-Keeper
when the bus is high.
When OE is low, the TCA39416 is disabled, the one shots and internal pull ups are also disabled.
8.2 Functional Block Diagram
VCCA
VCCB
Gate Bias
Generator
OE
A1
Rise/Fall
Accelerator
Rise/Fall
Accelerator
B1
Rise/Fall
Accelerator
Rise/Fall
Accelerator
A2
B2
8.3 Feature Description
8.3.1 Architecture
The TCA39416 architecture (see 图 8-1) is an auto-direction-sensing based translator that does not require a
direction-control signal to control the direction of data flow from A to B or from B to A.
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VCCA
VCCB
Gate Bias
Generator
Rise Time
Logic
Rise Time
Logic
A
B
Fall Time
Logic
Fall Time
Logic
VCCA
VCCB
图8-1. Architecture of a TCA39416 Cell
These two bidirectional channels support both directions of data flow without a direction-control signal. By
properly biasing the gate of the pass-FET, the FET can turn on (low RDSON), when either side input voltage drops
to ~ 1 voltage threshold below the lowest of the two supplies.
The TCA39416 is part of the TI "Switch" type voltage translator family and employs key circuits to enable this
voltage translation:
1. An N-channel pass-gate transistor topology that ties the A-port to the B-port.
2. Output rise time accelerator circuitry to detect and accelerate rising edges on the A or B ports
3. Output fall time accelerator circuitry to detect and accelerate falling edges on the A or B ports
For bidirectional voltage translation, pull up resistors are included on the device for dc current sourcing
capability. The VGATE gate bias of the N-channel pass transistor is set to the lower supply voltage and can be
represented with VCCA
.
The rise and fall time accelerator (RTA and FTA, respectively) circuitry speeds up the output slew rate by
monitoring the input edge for transitions, helping maintain the data rate through the device. During a low-to-high
signal rising edge, the rise time accelerator (RTA) circuit turns on to increase the current drive capability of the
driver. This edge-rate acceleration provides high ac drive by bypassing the internal 10-kΩ pull up resistors
during the low-to-high transition to speed up the signal. The output resistance of the driver is decreased to
approximately 150 Ω during this acceleration phase. During a high-to-low signal falling edge, the fall time
accelerator (FTA) turns on to increase the current drive capability of the driver, similar to the rise time
accelerator. This helps reduce the fall time for large capacitive loads. For light capacitive loads, the fall time
accelerator will not enable.
8.3.2 Enable and Disable
The TCA39416 has an OE input that is used to disable the device by setting OE low, which prevents any signals
from propagating across the device. This pin is referenced to the VCCA supply. The rise and fall time accelerators
and the internal pull-up resistors are also disabled. The disable time (tdis) indicates the delay between the time
when OE goes low and when the outputs are disabled (Hi-Z). The enable time (ten) indicates the amount of time
the user must allow for the one-shot circuitry to become operational after OE is taken high.
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8.3.3 Pull up resistors on I/O Lines
I3C Controllers manage an active (such as, dynamic) pull-up resistance on SDA, which they can enable and
disable as the bus transitions between open drain and push-pull mode. The continuous DC current sourcing or
sinking capability is determined by the external system-level open-drain or push-pull drivers that are interfaced to
the TCA39416 I/O pins.
In TCA39416, each A-port I/O has an internal 10-kΩpull up resistor to VCCA, and each B-port I/O has an internal
10-kΩpull up resistor to VCCB. The internal pull ups of the TCA39416 are controlled by their respective supplies.
The resistors have back-biasing protection, so that if a supply is off, the current cannot flow through the resistors
back into the supply. When both A and B side supply is above VUVLO_RISE and OE is high, the pull up resistors
are enabled when the bus is high.
8.3.4 Input Driver Requirements
The continuous dc-current "sinking" capability is determined by the external system-level open-drain (or push-
pull) drivers that are interfaced to the TCA39416 I/O pins. Since the high bandwidth of these bidirectional I/O
circuits is used to facilitate this fast change from an input to an output and an output to an input, they have a
modest dc-current "sourcing" capability of hundreds of micro-Amps, as determined by the internal 10-kΩ pullup
resistors.
The fall time (tfA, tfB) of a signal depends on the edge-rate and output impedance of the external device driving
TCA39416 data I/Os, as well as the capacitive loading on the data lines.
Similarly, the tPHL and max data rates also depend on the output impedance of the external driver. The values for
tfA, tfB, tPHL, and maximum data rates in the data sheet assume that the output impedance of the external driver
is below VOL on both sides.
8.4 Device Functional Modes
The TCA39416 device has two functional modes, enabled and disabled. To disable the device, set the OE input
low, which disables the rise time and fall time accelerators, and prevents signals from propagating across the
channels. The internal pull up resistors are also affected by the OE input and are disabled when OE input is low.
Setting the OE input high enables the device. The internal pull-up resistors act has High-Keeper and are enabled
based on respective VCC voltage when bus is high. 表8-1 provides functional description for TCA39416.
表8-1. Functional table
Supply voltage(4)
Input(1)
I/O
VCCA
VCCB
OE(2)
0.72 V to 1.98 V
0.72 V to 1.98 V
GND(3)
0.72 V to 1.98 V
0.72 V to 1.98 V
GND(3)
L
H
X
disconnected
A1 = B1; A2 = B2
disconnected
(1) H = HIGH voltage level; L = LOW voltage level; X = don’t care
(2) OE is referenced to VCCA. Pull OE low to place all outputs in 3-state mode.
(3) When either VCCA or VCCB is at GND level, the device goes into power-down mode.
(4) CCA ≤VCCB
V
.
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TCA39416 can be used to bridge the digital-switching compatibility gap between two voltage nodes to
successfully interface logic threshold levels found in electronic systems. It should be used in a point-to-point
topology for interfacing devices or systems operating at different interface voltages with one another. The
primary target application use is for interfacing with I3C push-pull drivers or open-drain drivers on the data I/Os
such as I2C or SMBus, where the data is bidirectional and no control signal is available.
9.2 Typical Application
1.2 V
1.8 V
0.1 ꢀF
0.1 ꢀF
VCCA
A2
VCCB
B2
SDA
SCL
SDA
SCL
A1
B1
Controller
13C Bus
13C Bus
Devices
OE
OE is referenced to VCCA
图9-1. Typical Application
9.2.1 Design Requirements
For this design example, use the parameters listed in 表9-1.
表9-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
0.72 V to 1.98 V
0.72 V to 1.98 V
Input voltage range
Output voltage range
9.2.2 Detailed Design Procedure
To begin the design process, determine the following:
• Input voltage range
– Use the supply voltage of the device that is driving the TCA39416 device to determine the input voltage
range. For a valid logic high, the value must exceed the VIH of the input port. For a valid logic low, the
value must be less than the VIL of the input port.
• Output voltage range
– Use the supply voltage of the device that the TCA39416 device is driving to determine the output voltage
range
– The TCA39416 device has 10-kΩinternal pull up resistors that act as high-keepers when the I/O lines are
high.
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9.2.3 Application Curve
图9-2. Level-Translation of a 12.5-MHz Signal
9.3 Power Supply Recommendations
The TCA39416 has no supply restrictions outside of the 0.72 V to 1.98 V range. VCCA must be ≤ VCCB for
proper operation.
The sequencing of each power supply does not damage the device during the power up operation, so either
power supply can be ramped up first. The output-enable (OE) input circuit is designed so that when the (OE)
input is low, the outputs are disabled. No signals may propagate the rise time and fall time accelerators, and the
internal pull up resistors are disabled. To make sure the signals do not pass through during power up or power
down, the OE input pin must be tied to GND through a pull down resistor. The OE input pin should not be
enabled until VCCA and VCCB are fully ramped and stable. If OE is tied to VCCA, this is OK, but might result in a
glitch on the bus during power up depending on the capacitive load and ramp rates. The minimum value of the
pull down resistor to ground is determined by the current-sourcing capability of the driver.
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9.4 Layout
9.4.1 Layout Guidelines
For reliability of the device, the following common printed-circuit board layout guidelines are recommended:
1. Bypass capacitors should be used on power supplies and should be placed as close as possible to the
VCCA, VCCB pin, and GND pin.
2. Short trace lengths should be used to avoid excessive loading.
3. Keep Ax and Bx lengths close to prevent skewing the signals.
4. PCB signal trace-lengths must be kept short enough so that the round-trip delay of any reflection is less than
the one-shot duration, approximately <30 ns. Making sure that any reflection encounters low impedance at
the source driver.
9.4.2 Layout Example
B2
GND
VCCA
A2
B1
VCCB
OE
VCCB
GND
GND
CAP
TCA39416
CAP
VCCA
To MCU
A1
图9-3. Layout Example (DDF)
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10 Device and Documentation Support
10.1 Documentation Support
For related documentation see the following:
• Texas Instruments, I3C - Next Generation Serial Communication Interface
10.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTCA39416DTWR
TCA39416DDFR
ACTIVE
X2SON
DTW
DDF
8
8
5000
TBD
Call TI
Call TI
-40 to 125
-40 to 125
Samples
Samples
ACTIVE SOT-23-THIN
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
2VIF
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TCA39416DDFR
SOT-23-
THIN
DDF
8
3000
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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7-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOT-23-THIN DDF
SPQ
Length (mm) Width (mm) Height (mm)
210.0 185.0 35.0
TCA39416DDFR
8
3000
Pack Materials-Page 2
PACKAGE OUTLINE
DDF0008A
SOT-23 - 1.1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE
C
2.95
2.65
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
6X 0.65
8
1
2.95
2.85
NOTE 3
2X
1.95
4
5
0.38
0.22
8X
0.1
C A B
1.65
1.55
B
1.1 MAX
0.20
0.08
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.1
0.0
0 - 8
0.6
0.3
DETAIL A
TYPICAL
4222047/C 10/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
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EXAMPLE BOARD LAYOUT
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
1
8
8X (0.45)
SYMM
6X (0.65)
5
4
(R0.05)
TYP
(2.6)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222047/C 10/2022
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DDF0008A
SOT-23 - 1.1 mm max height
PLASTIC SMALL OUTLINE
8X (1.05)
SYMM
(R0.05) TYP
8
1
8X (0.45)
SYMM
6X (0.65)
5
4
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4222047/C 10/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
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PLETRONICS
TCA4027036AB010000-FREQ
Clipped Sine Output Oscillator, 10MHz Min, 40MHz Max, ROHS COMPLIANT, CERAMIC, LCC-4
PLETRONICS
TCA4027036AB010008-FREQ
Clipped Sine Output Oscillator, 10MHz Min, 26MHz Max, ROHS COMPLIANT, CERAMIC, LCC-4
PLETRONICS
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