TAS5101_技术文档

TAS5101

SLES039 – JUNE 2002

TRUE DIGITAL STEREO AUDIO AMPLIFIER

WITH PWM STEREO POWER OUTPUT STAGE

D

Internet Music Appliance

Mini/Micro Component Systems

FEATURES

D

2 × 15 W High-Quality Digital Amplifier Power

Stage

DESCRIPTION

D

Single-Ended Output

>95-dB Dynamic Range (TDAA System)

The TAS5101 is a high-performance true digital stereo

audio amplifier (TDAA) Power Stage, designed to drive

2 × 15 watts per channel. The TAS5101 incorporates

TI’s equibitt technology and is used in conjunction with

a Digital Audio PWM processor (TAS50xx) to deliver

high-power, true digital audio amplification. The

efficiency of this digital amplifier can be greater than

90%, reducing the size of both the power supplies and

heat sinks needed. The TAS5101 accepts a stereo

PWM 3.3V input and controls the switching of an

internal CMOS H-bridge.

THD+N < 0.1% (1 kHz, 1 W to 15 W RMS

Into 4 Ω)

D

Power Efficiency > 90% Into 4-Ω to 8-Ω Load

D

Low Profile, SMD 32-Pin PowerPAD Package

Requires No Heat-Sink When Using

Recommended Layout

D

2 × 15-W RMS Continuous Power Into 4 Ω

Self-Protecting Design

3.3-V Digital Interface

When used with the TAS50xx PWM Processor, system

performance of less than 0.09% THD is attainable.

Over-current protection, over-temperature, and

under-voltage protections are built into the TAS5101,

safeguarding the H-bridge and speakers against output

shorts, over-voltage conditions, and other fault

conditions that could damage the system.

EMI Compliant When Used With

Recommended System Design

APPLICATIONS

D

Digital TV Audio Amplifier

D

Car Audio Amplifiers and Head Units

TYPICAL TDAA STEREO AUDIO SYSTEM

L-C

Filter

Digital Audio

• TAS3001

• TAS3103

• DSP

TAS5010

TAS5101

• DIR1703

• 1394

L-C

Filter

• Volume

• EQ

• DRC

• Bass

• Treble

• Serial Audio Input Port

• Internal PLL

• PCM–PWM Modulator

• 2 × 15 W Single-Ended

H-Bridge Power Devices

NOTE:

The TAS5000 in NOT recommended for use with the TAS5101

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD and Equibit are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1

www.ti.com

TAS5101

SLES039 – JUNE 2002

terminal assignments

The TAS5101 is offered in a thermally enhanced 32-pin HTSSOP surface-mount package (DAP).

DAP PACKAGE

(TOP VIEW)

1

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

PWM_AP

PWM_AM

ERR1

PVDDA2

2

LDROUTA

BOOTSTRAPA

PVDDA1

3

4

ERR0

SHUTDOWN

DVDD

5

PVDDA1

6

OUTPUTA

PVSS

7

DVSS

8

9

PVSS

10

11

12

13

14

15

16

VRFILT

BIAS_A

BIAS_B

HiZ

RESET

PWM_BM

PWM_BP

OUTPUTB

PVDDB1

BOOTSTRAPB

LDROUTB

PVDDB2

ordering information

T

PACKAGE

TAS5101DAP

TAS5101IDAP

TAPE and Reel

TAS5101DAPR

TAS5101IDAPR

A

0°C to 70°C

–40°C to 85°C

references

TAS5010 Digital Audio PWM Processor Data Manual – TI Literature Number SLAS328

System Design Considerations for True Digital Audio Power Amplifiers – TI Literature Number SLAA117

Digital Audio Measurements – TI Literature Number SLAA114

PowerPAD Thermally Enhanced Package – TI Literature Number SLMA002

TAS5101_SE Application Report – TI Literature Number SLEA001

suggested system block diagrams

See application note SLAA117 for more details.

L-C

Filter

Digital Audio

• TAS3001

• TAS3103

• DSP

TAS5010

TAS5101

• DIR1703

• 1394

L-C

Filter

• Digital Parametric EQ • Serial Audio Input Port

• 2 × 1/2 H-Bridge

• Volume

• DRC

• Internal PLL

• Bass

• Treble

Figure 1. System #1: Stereo Configuration With TAS3001 Digital Audio Processor

2

www.ti.com

TAS5101

SLES039 – JUNE 2002

functional block diagram

1/2 H-Bridge

LDR

OUTPUTA

PWM_AP

PWM_AM

DIFF

RCVR

OUTPUTA

Boot Strap

Gate Drive

PVSS

BIAS_A

HiZ

RESET

Control/Sense

Circuit

Bandgap

Reference

SHUTDOWN

ERR1

ERR0

LDROUTB

PVDDB2

VRFILT

BOOTSTRAPB

PVDDB1

1/2 H-Bridge

PVDDB1

BIAS_B

LDR

DIFF

PWM_BM

PWM_BP

OUTPUTB

Boot Strap

Gate Drive

RCVR

3

www.ti.com

TAS5101

SLES039 – JUNE 2002

Terminal Functions

TERMINAL

NAME

I/O

DESCRIPTION

NO.

11

BIAS_A

I

Connect external resistor to DVSS. See application note SLAA117

Bootstrap capacitor pin for H-bridge A

BIAS_B

12

BOOTSTRAPA

BOOTSTRAPB

DVDD

30

O

I

19

Bootstrap capacitor pin for H-bridge B

6

3.3-V digital voltage supply for logic

DVSS

7, 8, 9

I

Digital ground for logic is internally connected to PVSS. All three pins must be tied together but not

connected externally to PVSS. See Figure 5.

ERR1

3

4

O

I

Error/warning report indicator. This output is open drain with internal pullup resistor.

Low voltage drop-out regulator output A (not to be used to supply current to external circuitry)

Low voltage drop-out regulator output B (not to be used to supply current to external circuitry)

H-bridge output A

ERR0

LDROUTA

LDROUTB

OUTPUTA

OUTPUTB

PVDDA1

PVDDA2

PVDDB1

PVDDB2

PVSS

31

18

26, 27

22, 23

28, 29

32

H-bridge output B

High voltage power supply, H-bridge A

I

High voltage power supply for low-dropout voltage regulator A-side

High voltage power supply, H-bridge B

20, 21

17

I

High voltage power supply for low-dropout voltage regulator B-side

High voltage power supply ground

24, 25

13

I

HiZ

I

HiZ = 0, when asserted, the H-bridge output is set to high-impedance mode

PWM input A(+)

PWM_AP

PWM_AM

PWM_BP

PWM_BM

RESET

1

I

2

I

PWM input A(–)

16

I

PWM input B(+)

15

I

PWM input B(–)

14

I

Reset and mute mode = 0, normal mode = 1, when in reset mode, H-bridge MOSFETs are in low-low

output state. Asserting the RESET signal low causes all fault conditions to be cleared.

SHUTDOWN

5

O

Device is in shutdown due to fault condition, normal mode = 1, shutdown = 0. The shutdown

condition can be cleared by asserting the RESET signal. This output is open drain with internal

pullup resistor.

VRFILT

10

O

A filter capacitor should be added between VRFILT and DVSS pins.

NOTE: The four PWM inputs: PWM_AP, PWM_AM, PWM_BP, and PWM_BM must always be connected to the TAS5010 output pins, and never

left floating. Floating PWM input pins will cause an illegal PWM input state signal to be asserted.

Dualpins:OUTPUTA, OUTPUTB, PVDDA1andPVDDB1musthavebothpinsconnectedexternallytothesamepointonthecircuitboard,

respectively. Both PVSS pins must also be connected together externally. These multiple pins are for the high current DMOS output

devices. Failure to connect all the multiple pins to the same respective node will result in excessive current flow in the internal bond wires

andcan cause the device to fail. All electrical characteristics arespecifiedandmeasuredwithallofthemultiplepinsconnectedtothesame

node, respectively.

4

www.ti.com

TAS5101

SLES039 – JUNE 2002

functional description

PWM H-bridge state control

The digital interface control signals consists of PWM_AP, PWM_AM, PWM_BP, and PWM_BM. These signals

are a complementary differential signal format for the A-side H-bridge and the B-side H-bridge.

bootstrapped gate drive

The TAS5101 includes 2 dedicated bootstrapped power supplies. A bootstrap capacitor is connected between

the individual bootstrap pin and the associated output as described in the application note SLAA117. For

example, a capacitor will be connected between the BOOTSTRAPA pin and OUTPUTA pin, and another

capacitor will be connected between the BOOTSTRAPB pin and the OUTPUTB pin. The bootstrap power

supply minimizes the number of high voltage power supply levels externally supplied to the system while

providing a low noise supply level for driving the high-side N-channel DMOS transistors. See application note

SLAA117 for details.

low-dropout voltage regulator

Two on-chip low-dropout voltage regulators (LDO) are provided to minimize the number of external power

supplies needed for the system. These voltage regulators are for internal circuits only and cannot be used for

external circuitry. Each LDO is dedicated to an H-bridge and its gate driver. An LDO output capacitor is

connected between the individual LDO output pin and the associated output return as described in the

application note SLAA117. For example, a capacitor will be connected between the LDROUTA pin and PVSS

pin, and another capacitor will be connected between the LDROUTB pin and PVSS pin. This capacitor is usually

0.1 µF.

high-current H-bridge output stage

The positive outputs of the H-bridge are the two OUTPUTA pins. The negative outputs of the H-bridge are the

two OUTPUTB pins. The logic for the input command to H-bridge outputs is described in the H-bridge output

mapping section below. When the TAS5101 is in the normal mode, as seen in the H-bridge output mapping

tables, the outputs are decoded from the inputs. However, the TAS5101 is immediately shut down if any of the

followingerror conditions occur: over-current, over-temperature, low regulator output voltage, or an illegal PWM

input state is applied. For these conditions, the outputs are set to the appropriate disabled state as specified

in the H-bridge output mapping section, and the SHUTDOWN pin is set low.

H-bridge output mapping

The A-side and B-side H-bridge output is designed to the following truth table:

INPUTS

OUTPUTS

OUTPUTA/B

DESCRIPTION

RESET

HiZ

X

0

PWM_AP/BP PWM_AM/BM SHUTDOWN

†

X

0

1

X

0

1

X

0

1

0

1

0

1

0

1

0

0 or Hi-Z

Shutdown

High Impedance

Low

Hi-Z

0

1

0

Low

1

0

Normal

1

Normal

1

0

Low

†

Output is 0 for low voltage, over temperature, and illegal input. Hi-Z is for over current.

5

www.ti.com

TAS5101

SLES039 – JUNE 2002

control/sense circuitry

The control/sense circuitry consists of the following 3.3-V logic level pins: HiZ, RESET, ERR0, ERR1, and

SHUTDOWN. The active-low HiZ input pin powers down all internal circuitry and forces the H-bridge outputs

to the Hi-Z state. When the HiZ pin is low, the open drain ERR0, ERR1, and SHUTDOWN pins are also disabled

so that their outputs can be pulled high. The active-low RESET input pin forces the H-bridge outputs to the

low-low state and resets the over-current shutdown latch. The HiZ pin overrides the RESET pin. The ERR0,

ERR1, and SHUTDOWN outputs indicate the following conditions in the TAS5101 as shown in the table below.

These three outputs are open-drain connections with internal pullup resistors so that wire-ORed connections

can be made by the user with other external control devices. The short circuit protect error condition will latch

the TAS5101 in this shutdown state and force the H-bridge outputs to the Hi-Z state until the device is reset by

means of the RESET pin. The illegal PWM input state, over-temperature, and low regulator voltage error

conditions will not latch the device in the shutdown condition. Instead the H-bridge outputs are forced to the

low-low state and the TAS5101 will return to normal operation as soon as the error condition ends. Loss of

clocking PWM signal is also considered an illegal PWM input state.

SHUTDOWN

ERR1

ERR0

FUNCTION

Illegal PWM input state

Short circuit protect (latch)

Over temperature protect

Low regulator voltage protect

Reserved

OUTPUTA

Low

OUTPUTB

Low

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Hi-Z

Low

—

Reserved

—

High temperature – warning

Normal operation

Normal

6

www.ti.com

TAS5101

SLES039 – JUNE 2002

device operation

power sequences

system power-up/power-down sequencing

The recommended power-up/power-down sequence is shown in Figure 3. For proper operation the RESET

signal should be kept LOW when both DVDD and output power (PVDDA1, PVDDA2, PVDDB1, and PVDDB2)

are being applied. The RESET signal should remain LOW for at least 1 ms after output power is applied.

DVDD

> 1 ms

PVDDA1

PVDDA2

PVDDB1

PVDDB2

> 100 ms

RESET/HiZ

NOTE: This power-up/power-down sequence will ensure that there are no device reliability issues. However, audio artifacts during power cycling

may occur (see TAS5101_SE Application Report (SLEA001) for more information).

Figure 2. Power-Up/Power-Down Sequence

RESET function

The device is put into a reset condition when the (active low) RESET signal is asserted. While in the reset state,

the input H-bridge control signals consisting of PWM_AP, PWM_AM, PWM_BP, and PWM_BM are ignored, and

the H-bridge MOSFETs are placed in a state where OUTPUTA and OUTPUTB are both low. Asserting the

RESET signal low also causes the short circuit protection latch to be reset. The RESET and HiZ signals are

normally connected to the VALID signal from the TAS5010, when used in a single-ended configuration.

HiZ function

The HiZ function places the output MOSFETs in a high-impedance state when this function is asserted by

placing pin 13 at logic low. This function is usually used in conjunction with the RESET function during power

on and off to reduce or eliminate “pops and clicks” associated with powering the amplifier.

reinitialization sequence

Proper initial conditions for this device include asserting the RESET and HiZ signals until the reset operation

has completed (1 ms). Additionally, when using this device with the TAS5010 controller, this function can be

accomplished by asserting the reset pin on the TAS5010 during the reset sequence (see Figure 3).

audio application considerations

power supply decoupling

Power supply decoupling and layout optimization information should be obtained by following the detailed

information in the application note SLEA005.

optimal power transfer for H-bridge

The TAS5101 is a power H-bridge that is designed to deliver 2 × 15 W/rms into loads of 4 Ω in a single-ended

configuration. Rather than requiring the usual heatsink, the package is designed to deliver this wattage by

careful layout as described in the application note SLAA117. Careful attention must be given to the value of the

high-voltage power supply level for a given load resistance. See recommended operating conditions.

7

www.ti.com

TAS5101

SLES039 – JUNE 2002

audio application considerations (continued)

reconstruction output filter

An output reconstruction filter is required between the H-bridge outputs and the loudspeaker load. This second

order low-pass filter passes the audio information to the loudspeaker, while filtering out the high frequency

out-of-band information contained in the H-bridge output PWM pulses. The values of the L and C components

selected are dependent on the loudspeaker load impedance. See application note SLAA117.

fault indicator usage

TheTAS5101isaself-protectingdevicethatprovidesdevicefaultreporting, includingover-temperatureprotect,

under-voltage lockout (low-regulator voltage), and short circuit protection. The short circuit protection protects

against short circuits that may occur at the loudspeaker load when configured according to the application note

SLAA117. The TAS5101 is not recommended for driving loads less than 4 Ω, since the internal current limit

protection might be activated.

An under-voltage lockout signal occurs when an insufficient voltage level is present on the LDROUTA or

LDROUTBpins. During this condition gate drive levels are not sufficient for driving the power MOSFETs. Normal

operationisresumedwhentheminimumproperLDROUTAorLDROUTBlevelisobtained, andthelowregulator

voltage protect signal is de-asserted. See the control/sense circuitry section for error and warning conditions.

A high temperature warning signal is asserted on pin ERR0 when the device temperature exceeds 125°C

typical.

If the internal device temperature exceeds 150°C typical, the over temperature protect signal is asserted and

the TAS5101 is shut down. The device will re-enable once the temperature drops to 125°C typical. See the

control/sense circuitry section for error and warning conditions.

Detection of an illegal PWM input state or the loss of a clocking PWM input signal will cause an illegal PWM input

state signal to be asserted on the ERR1and ERR0 pins and will set the SHUTDOWN pin to the low state.

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

DC supply voltage range: DVDD to DVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 5.5 V

PWM_AP, PWM_AM, PWM_BP, PWM_BM . . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V

RESET, HiZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V

PVDDA1 to PVSS, PVDDB1 to PVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 28 V

PVDDA2 to PVSS, PVDDB2 to PVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 28 V

Output DMOS drain-to-source breakdown voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 V

Operating junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 150°C

J

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

8

www.ti.com

TAS5101

SLES039 – JUNE 2002

recommended operating conditions (nominal output power = 2 × 15 W (RMS), T = 25°C)

A

†

thermal data

PARAMETER

MIN NOM

150

MAX

UNIT

°C

Shutdown junction temperature, T

J(SD)

Warning junction temperature, T

125

°C

J(W)

Commercial

0

25

70

85

Operating ambient temperature, T

°C

A

Industrial

–40

Thermal resistance junction-to-ambient, θ

2 oz. trace and copper pad with solder

2 oz. trace and copper pad without solder

23.5

0.32

44.3

°C/W

ja

Thermal resistance junction-to-case, θ

jc

Thermal resistance junction-to-ambient, θ

†

One of the most influential components on the thermal performance of a package is board design. In order to take full advantage of the heat

dissipating abilities of the PowerPAD packages, a board must be used that acts similar to a heat sink and allows for the use of the exposed (and

solderable),deepdownsetpad. SeeAppendixAofthePowerPADThermallyEnhancedPackageapplicationnote, TIliteraturenumberSLMA002

and the Thermal Design of the PowerPad PCB Layout section of the System Design Considerations for True Digital Audio Power Amplifiers

application note, TI literature number SLAA117.

R = 4 Ω to 8 Ω

L

PARAMETER

MIN NOM

MAX

3.6

UNIT

Digital

DVDD to DVSS

3

16.5

10.5

3.3

26.5

V

PVDDA2 to PVSS

PVDDB2 to PVSS

PVDDA2 to PVSS

PVDDB2 to PVSS

28

Supply voltage

Regulator

V

}

16.5

†

‡

If PVDD is greater than 26.5 V, 15 Watts per channel is still the maximum specified continuous output power.

If using a PVVD power supply less than 16.5 V, connect LDROUTA to PVDDA2 and connect LDROUTB to PVDDB2. Under this condition

H-Bridge forward on-state resistance is increased. This will increase internal power dissipation. Maximum output power may need to be reduced

to meet thermal conditions.

maximum available power at common load impedance for DAP package unclipped (0 dB) level

LOAD IMPEDANCE

PVDAA1/PVDDB1

(VDC)

APPROXIMATE MAX OUTPUT POWER

(W)

†

THD+N AT MAX POWER AND 1 kHz INPUT

(Ω)

4

6

8

26.5

27

15

< 0.1%

< 0.09%

12.85

9.64

27

†

Dependent on board design and component selection.

9

www.ti.com

TAS5101

SLES039 – JUNE 2002

static digital specifications

RESET, HiZ, PWM_AP, PWM_AM, PWM_BP, PWM_BM, T = 25°C, DVDD = 3.3 V

A

PARAMETERS

MIN

MAX

UNIT

V

High-level input voltage, V

IH

2

Low-level input voltage, V

Input leakage current

0.8

10

V

IL

–10

µA

ERR0, ERR1, SHUTDOWN, (open drain with internal pullup resistor) T = 25°C, DVDD = 3.3 V)

A

PARAMETERS

MIN

MAX

UNIT

kΩ

Internal pullup resistors from SHUTDOWN, ERR0, ERR1 to DVDD

15

Low-level output voltage (I = 4 mA), V

0.4

V

O

OL

TAS5010/TAS5101 system performance measured at the speaker terminals

See the TI Literature Number SLAA117 for TAS5010/TAS5101 system performance.

electrical characteristics

supply, T = 25°C (F

= 384 kHz, OUTPUTA and OUTPUTB not connected, DVDD = 3.3 V,

A

switching

PVDDA1 = 26.5 V, PVDDB1 = 26.5 V, PVDDA2 = 26.5 V, PVDDB2 = 26.5 V, 50% input duty cycle)

PARAMETER

TYP

MAX

UNIT

DVDD

Operating

2

mA

Supply current

PVDDA1+PVDDB1+

PVDDA2+PVDDB2

†

Operating

20

mA

†

13-kΩ resistor from BIAS_A (pin 11) to DVSS and 13-kΩ resistor from BIAS_B (pin 12) to DVSS.

H-Bridge transistors, PVDDA2 = PVDDB2 = 22 V, DVDD = 3.3 V, T = 25°C (unless otherwise noted)

A

PARAMETER

TEST CONDITIONS

HiZ = 0, Hi-Z state

= 2.5 A, PWM_AP = PWM_BP = 0,

MIN

TYP

MAX

UNIT

Drain-to-source breakdown voltage

I

= 1 mA,

28

V

D

Forward on-state resistance, low-side drivers

OUTPUTA and OUTPUTB to PVSS

SINK

0.2

Ω

See Notes 2, 3, and 4, PWM_AM = PWM_BM = 1

= 2.5 A, PWM_AP = PWM_BP = 1,

See Notes 2, 3, and 5, PWM_AM = PWM_BM = 0

Forward on-state resistance, high-side drivers

PVDDA1 to OUTPUTA, PVDDB1 to OUTPUTB

I

SOURCE

On-state resistance matching low side

On-state resistance matching high side

98%

NOTES: 1. Test time should be < 1 ms to avoid temperature change.

2. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.

3. Connect PVDDA2 and PVDDB2 to 26.5-V power supply with respect to PVSS. LDROUTA, LDROUTB, BOOTSTRAPA, and

BOOTSTRAPB pins open.

4. Connect PVDDA2 to 26.5-V power supply with respect to PVSS. LDROUTA, LDROUTB, BOOTSTRAPA and BOOTSTRAPB

capacitorsareconnectedrespectively. ClockPWMinputstoallowbootstrapcapacitorstocharge. 93–99%modulationmustbeused

on PWM_AP, PWM_AM, PWM_BP, and PWM_BM inputs to prevent the activity detector from shutting down the device during this

measurement. Note that F

= 384 kHz.

switching

electrical characteristics, voltage regulator, T = 25°C (unless otherwise noted)

A

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I

= 5 mA,

PVDDA2=PVDDB2 = 18 V to 28 V,

DVDD = 3.3 V

O

Output voltage (LDROUTA, LDROUTB)

14.5

15.3

16

V

See Note 6,

NOTE 5: These voltage regulators are for internal gate drive circuits only and are not to be used under any circumstances to supply current to

external circuity.

10

www.ti.com

TAS5101

SLES039 – JUNE 2002

THERMAL INFORMATION

The thermally enhanced DAP package is based on the 32-pin HTSSOP, but includes a thermal pad (see

Figure 4) to provide an effective thermal contact between the IC and the PWB.

Traditionally, surface mount and power have been mutually exclusive terms. A variety of scaled-down TO-220

type packages have leads formed as gull wings to make them applicable for surface-mount applications. These

packages, however, have two shortcomings: they do not address the very low profile requirements (<2 mm) of

many of today’s advanced systems, and they do not offer a terminal-count high enough to accommodate

increasing integration. On the other hand, traditional low-power surface-mount packages require

power-dissipation derating that severely limits the usable range of many high-performance analog circuits.

The PowerPAD package (thermally enhanced HTSSOP) combines fine-pitch surface-mount technology with

thermal performance comparable to much larger power packages.

The PowerPAD package is designed to optimize the heat transfer to the PWB. Because of the very small size

and limited mass of a HTSSOP package, thermal enhancement is achieved by improving the thermal

conduction paths that remove heat from the component. The thermal pad is formed using a patented lead-frame

design and manufacturing technique to provide a direct connection to the heat-generating IC. When this pad

is soldered or otherwise thermally coupled to an external heat dissipater, high power dissipation in the ultrathin,

fine-pitch, surface-mount package can be reliably achieved.

DIE

Thermal

Side View (a)

Pad

DIE

End View (b)

Bottom View (c)

Figure 3. Views of Thermally Enhanced DAP Package

11

www.ti.com

TAS5101

SLES039 – JUNE 2002

APPLICATION INFORMATION

TAS5010

C11

TAS5101

1

32

31

30

29

28

27

PWM_AP

PWM_AM

26.5 V

PWM_BP

PWM_BM

PVDDA2

LDROUTA

2

3

4

BOOTSTRAPA

ERR1

ERR0

C8 C7

Error

Reporting

RESET

PVDDA1

Snubber

Circuit

5

SHUTDOWN

DVDD

PVDDA1

VALID_L

PWM_AM

PWM_AP

6

7

8

9

L1

OUTPUTA

26

25

C1

DVSS

OUTPUTA

C10

C9

DVSS

PVSS

24

23

22

21

DVSS

C2

10

11

OUTPUTB

VRFILT

BIAS_A

R1

R2

OUTPUTB

PVDDB1

L2

12

13

BIAS_B

HiZ

Snubber

Circuit

20

19

18

17

PVDDB1

14

15

16

C5

C6

RESET

BOOTSTRAPB

LDROUTB

PVDDB2

PWM_BM

PWM_BP

R3

R4

26.5 V

C3

C4

26.5 V

NOTE: C1, C2 = 1.0 µF

C3, C4 = 470 µF

C5, C8 = 0.033 µF

C6, C7 = 0.1 µF

C9, C10 = 0.1 µF

C11, C12 = 0.1 µF

R1, R2 = 13 kΩ

R3, R4 =4.7 kΩ

L1, L2 = 10 µH

Figure 4. Typical TAS5101 Application (One Channel Shown)

See the application note, TI literature number SLEA001 for detailed application information.

12

www.ti.com

TAS5101

SLES039 – JUNE 2002

MECHANICAL DATA

DAP (R-PDSO-G**)

PowerPAD PLASTIC SMALL-OUTLINE PACKAGE

38 PINS SHOWN

0,30

0,19

0,65

38

M

0,13

20

Thermal Pad

(see Note D)

6,20

8,40

NOM 7,80

0,15 NOM

Gage Plane

1

19

0,25

A

0°–ā8°

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

28

30

32

38

DIM

9,80

9,60

11,10

10,90

11,10

10,90

12,60

12,40

A MAX

A MIN

4073257/A 07/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion.

D. Thepackagethermalperformancemaybeenhancedbybondingthethermalpadtoanexternalthermalplane.Thispadiselectrically

and thermally connected to the backside of the die and possibly selected leads. Thermal pad size is 3,86 mm X 3,91 mm for the

32-pin TAS5101 device.

E. Falls within JEDEC MO-153

PowerPAD is a trademark of Texas Instruments.

13

www.ti.com

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

copyright, maskworkright, orotherTIintellectualpropertyrightrelatingtoanycombination, machine, orprocess

in which TI products or services are used. Information published by TI regarding third–party products or services

does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.

Use of such information may require a license from a third party under the patents or other intellectual property

of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without

alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction

of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for

such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that

product or service voids all express and any implied warranties for the associated TI product or service and

is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Mailing Address:

Texas Instruments

Post Office Box 655303

Dallas, Texas 75265


型号：	TAS5101
厂家：	TEXAS INSTRUMENTS
描述：	TRUE DIGITAL STEREO AUDIO AMPLIFIER WITH PWM STEREO POWER OUTPUT STAGE 与PWM立体声功率输出级真正的数字立体声音频放大器音频放大器输出元件
文件：	总14页 (文件大小：187K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TAS5101 [TI]

相关型号：

TAS5101DAP

TAS5101DAPR

TAS5101IDAP

TAS5101IDAPR

TAS5102

TAS5102DAD

TAS5102DADG4

TAS5102DADR

TAS5102DADRG4

TAS5102_1

TAS5103

TAS5103DAP