SN75LBC171DB [TI]
TRIPLE DIFFERENTIAL TRANSCEIVERS; 三重微分收发器
| 型号： | SN75LBC171DB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TRIPLE DIFFERENTIAL TRANSCEIVERS |
| 文件： | 总18页 (文件大小：289K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LBC171, SN75LBC171
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS460A – NOVEMBER 2000 – REVISED FEBRUARY 2001
SN65LBC171DB (Marked as BL171)
SN75LBC171DB (Marked as LB171)
SN65LBC171DW (Marked as 65LBC171)
SN75LBC171DW (Marked as 75LBC171)
Three Differential Transceivers in One
Package
1
Signaling Rates Up to 30 Mbps
(TOP VIEW)
Low Power and High Speed
Designed for TIA/EIA-485, TIA/EIA-422, ISO
8482, and ANSI X3.277 (HVD SCSI Fast–20)
Applications
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1R
1DE
1D
1B
1A
RE
CDE
Common-Mode Bus Voltage Range
–7 V to 12 V
GND
GND
2R
V
CC
2B
2A
3B
3A
3D
ESD Protection on Bus Terminals
Exceeds 12 kV
2DE
2D
Driver Output Current up to ±60 mA
3R
Thermal Shutdown Protection
3DE
Driver Positive and Negative Current
Limiting
logic diagram
Power-Up, Power-Down Glitch-Free
Operation
CDE
Pin-Compatible With the SN75ALS171
1DE
1D
1A
1B
Available in Shrink Small-Outline Package
RE
1R
description
The SN65LBC171 and SN75LBC171 are
monolithic integrated circuits designed for
bidirectional data communication on multipoint
bus-transmission lines. Potential applications
include serial or paralleldatatransmission, cabled
peripheral buses with twin axial, ribbon, or
twisted-pair cabling. These devices are suitable
for FAST–20 SCSI and can transmit or receive
data pulses as short as 25 ns, with skew less than
3 ns.
2DE
2D
2A
2B
2R
3DE
3D
3A
3B
These devices combine three 3-state differential
line drivers and three differential input line
receivers, all of which operate from a single 5-V
power supply.
3R
The driver differential outputs and the receiver differential inputs are connected internally to form three
differentialinput/output(I/O)busportsthataredesignedtoofferminimumloadingtothebuswheneverthedriver
is disabled or V
party-line applications over long cable runs.
= 0. These ports feature a wide common-mode voltage range making the device suitable for
CC
The SN75LBC171 is characterized for operation over the temperature range of 0°C to 70°C. The SN65LBC171
is characterized for operation over the temperature range of –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC171, SN75LBC171
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS460A – NOVEMBER 2000 – REVISED FEBRUARY 2001
AVAILABLE OPTIONS
PACKAGE
PLASTIC SHRINK SMALL-OUTLINE
T
PLASTIC SMALL-OUTLINE
(JEDEC MS-013)
A
(JEDEC MO-150)
SN75LBC171DB
SN65LBC171DB
0°C to 70°C
SN75LBC171DW
SN65LBC171DW
–40°C to 85°C
†
Add R suffix for taped and reel
Function Tables
EACH DRIVER
EACH RECEIVER
INPUT
D
ENABLE
DE CDE
OUTPUTS
DIFFERENTIAL INPUT ENABLE OUTPUT
(V –V )
RE
R
A
B
A
B
H
L
OPEN
X
X
X
X
H
H
H
L
X
H
H
H
X
L
H
L
V
≥ 0.2 V
L
L
L
H
L
H
?
ID
–0.2 V < V < 0.2 V
L
L
Z
Z
Z
Z
H
H
Z
Z
Z
Z
ID
≤ –0.2 V
V
ID
L
X
Z
H
OPEN
OPEN
X
X
OPEN
H = high level, L = low level, X = irrelevant,
Z = high impedance (off), ? = indeterminate
equivalent input and output schematic diagrams
D, DE,CDE INPUTS
RE INPUT
R OUTPUT
V
V
CC
CC
V
CC
100 kΩ
1 kΩ
40 Ω
1 kΩ
Output
Input
Input
8 V
100 kΩ
8 V
A INPUT
B INPUT
A AND B OUTPUT
V
V
V
CC
CC
CC
4 kΩ
4 kΩ
100 kΩ
18 kΩ
16 V
16 V
16 V
4 kΩ
4 kΩ
18 kΩ
18 kΩ
Input
Input
Output
100 kΩ
4 kΩ
16 V
16 V
4 kΩ
16 V
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC171, SN75LBC171
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS460A – NOVEMBER 2000 – REVISED FEBRUARY 2001
†
absolute maximum ratings
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
CC
Voltage range at any bus I/O terminal (steady state) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –10 V to 15 V
Voltage input range, A and B, (transient pulse through 100 Ω, see Figure 12) . . . . . . . . . . . . . . –30 V to 30 V
Voltage range at any DE, RE, or CDE terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to V
+ 0.5 V
CC
Electrostatic discharge: Human body model (A, B, GND) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . 12 kV
All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 kV
Charged-device model (all pins) (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Power Dissipation Rating Table
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with JEDEC Standard 22, Test Method A114–A.
3. Tested in accordance with JEDEC Standard 22, Test Method C101.
POWER DISSIPATION RATING TABLE
‡
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T = 85°C
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
A
DB
995 mW
8.0 mW/°C
11.8 mW/°C
635 mW
950 mW
515 mW
770 mW
DW
1480 mW
‡
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
recommended operating conditions
MIN NOM
MAX
5.25
12
UNIT
V
Supply voltage, V
CC
4.75
–7
2
5
Voltage at any bus I/O terminal
A, B
V
High-level input voltage, V
V
CC
0.8
IH
DE, CDE, RE
V
V
Low-level input voltage, V
0
IL
Differential input voltage, V
A with respect to B
Driver
–12
–60
–8
0
12
60
8
ID
Output current
mA
Receiver
SN75LBC171
SN65LBC171
70
85
Operating free-air temperature, T
°C
A
–40
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC171, SN75LBC171
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS460A – NOVEMBER 2000 – REVISED FEBRUARY 2001
DRIVER SECTION
electrical characteristics over recommended operating conditions
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
Input clamp voltage
D, DE, CDE
I = 18 mA
–1.5
0
–0.7
V
V
V
V
V
IK
I
Open-circuit output voltage (single-ended)
A or B, No load
No load
V
V
O
CC
3.8
1
4.3
1.6
1.6
CC
2.4
Steady-state differential output voltage
|V
|
R
= 54 Ω,
See Figure 1
OD(SS)
L
‡
magnitude
With common-mode loading, See Figure 2
1
2.4
0.2
2.8
0.2
Change in differential output voltage
magnitude, | V | – |V
∆V
–0.2
2
V
V
V
OD
|
OD(H) OD(L)
R
C
= 54 Ω,
= 50 pF
L
L
V
Steady-state common-mode output voltage
See Figure 1
2.4
OC(SS)
Change in steady-state common-mode
∆V
–0.2
OC(SS)
output voltage (V
Input current
– V )
OC(L)
OC(H)
I
I
I
D, DE, CDE
–100
–700
–250
100
900
250
µA
µA
I
Output current with power off
Short-circuit output current
V
V
= 0 V,
V
O
= –7 V to 12 V
O
CC
= –7 V to 12 V, See Figure 7
O
mA
OS
CDE, DE, RE at
I
Supply current (driver enabled)
D at 0 V or V
CC
,
14
20
mA
CC
V
CC
, No load
†
‡
All typical values are at V
= 5 V and T = 25°C.
A
CC
The minimum V
may not fully comply with TIA/EIA-485-A at operating temperatures below 0°C. System designers should take the possibly
lower output signal into account in determining the maximum signal-transmission distance.
OD
switching characteristics over recommended operating conditions
PARAMETER
TEST CONDITIONS
MIN
4
TYP
8.5
8.5
7.5
7.5
MAX
12
11
11
11
2
UNIT
t
Differential output propagation delay, low-to high
Differential output propagation delay, high-to-low
Differential output rise time
PLH
t
4
PHL
t
r
t
f
3
R
= 54 Ω,
C = 50 pF,
L
L
ns
Differential output fall time
3
See Figure 3
t
Pulse skew | (t ) |
– t
sk(p)
PLH PHL
§
t
Output skew
Part-to-part skew
1.5
2
sk(o)
¶
t
sk(pp)
t
Differential output propagation delay, low-to high
Differential output propagation delay, high-to-low
Differential output rise time
3
3
3
3
7
7.5
7.5
7.5
10
10
12
12
3
PLH
t
PHL
t
r
t
f
See Figure 4,
(HVD SCSI double-terminated load)
ns
Differential output fall time
t
Pulse skew | (t ) |
– t
sk(p)
PLH PHL
§
t
Output skew
Part-to-part skew
1.5
2.5
25
25
25
25
sk(o)
¶
t
sk(pp)
t
Output enable time to high level
Output disable time from high level
Output enable time to low level
Output disable time from low level
15
18
10
17
PZH
See Figure 5
See Figure 6
ns
ns
t
PHZ
t
PZL
t
PLZ
§
¶
Output skew (t
sk(o)
) is the magnitude of the time delay difference between the outputs of a single device with all of the inputs connected together.
) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when
Part-to-part skew (t
sk(pp)
both devices operate with the same input signals, the same supply voltages, at the same temperature, and have identical packages and test
circuits.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC171, SN75LBC171
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS460A – NOVEMBER 2000 – REVISED FEBRUARY 2001
RECEIVER SECTION
electrical characteristics over recommended operating conditions
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
V
V
V
Positive-going differential input voltage threshold
Negative-going differential input voltage threshold
0.2
IT+
IT–
hys
OH
OL
–0.2
Hysteresis voltage (V
IT+
– V
)
40
4.7
0.2
mV
V
IT–
High-level output voltage
Low-level output voltage
V
V
= 200 mV, I
OH
= –8 mA, see Figure 10
= –8 mA, see Figure 10
V = 12 V
4
0
V
ID
CC
0.4
= –200 mV, I
OL
ID
0.9
I
I
Line input current
Other input = 0 V
mA
I
I
V = –7 V
I
–0.7
–100
12
I
Input current
RE
100
16
µA
kΩ
mA
R
Input resistance
A, B
I
I
Supply current (receiver enabled)
= 5 V and T = 25°C.
A, B, D open, RE, DE, and CDE at 0 V
CC
†
All typical values are at V
CC
A
switching characteristics over recommended operating conditions
PARAMETER
TEST CONDITIONS
MIN
7
TYP
MAX
16
16
3
UNIT
ns
t
Propagation delay time, low-to-high level output
Propagation delay time, high-to-low level output
Receiver output rise time
PLH
t
7
ns
PHL
V
ID
= –3 V to 3 V, See Figure 9
t
r
1.3
1.3
26
ns
t
f
Receiver output fall time
3
ns
t
Receiver output enable time to high level
Receiver output disable time from high level
Receiver output enable time to low level
Receiver output enable time to high level
40
40
40
40
2
PZH
See Figure 10
See Figure 11
ns
ns
t
PHZ
t
29
PZL
t
PLZ
t
Pulse skew (| ( t
– t
PLH PHL
|)
ns
ns
ns
sk(p)
t
Output skew
1.5
3
sk(o)
t
Part-to-part skew
sk(pp)
‡
§
Output skew (t
sk(o)
Part-to-part skew (t
) is the magnitude of the time delay difference between the outputs of a single device with all of the inputs connected together.
) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when
sk(pp)
both devices operate with the same input signals, the same supply voltages, at the same temperature, and have identical packages and test
circuits.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC171, SN75LBC171
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS460A – NOVEMBER 2000 – REVISED FEBRUARY 2001
PARAMETER MEASUREMENT INFORMATION
I
O
27 Ω
27 Ω
I
I
V
OD
50 pF
0 V or 3 V
I
O
V
O
V
OC
V
O
†
Includes probe and jig capacitance
Figure 1. Driver Test Circuit, V
and V
Without Common-Mode Loading
OC
OD
375 Ω
V
OD
V
TEST
= –7 V to 12 V
Input
60 Ω
375 Ω
V
TEST
Figure 2. Driver Test Circuit, V
With Common-Mode Loading
OD
R
= 54 Ω
L
C
= 50 pF
V
OD
L
Signal
50 Ω
Generator
† PRR = 1 MHz, 50% Duty Cycle, t < 6 ns, t < 6 ns, Z = 50 Ω
r
f
o
‡ Includes Probe and Jig Capacitance
3 V
0 V
Input
1.5 V
1.5 V
t
t
PHL
PLH
V
OD(H)
90% 90%
Output
0 V
10%
10%
V
OD(L)
t
t
f
r
Figure 3. Driver Switching Test Circuit and Waveforms, 485-Loading
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC171, SN75LBC171
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS460A – NOVEMBER 2000 – REVISED FEBRUARY 2001
PARAMETER MEASUREMENT INFORMATION
5 V
0 V
S1
375 Ω
75 Ω
60 pF
3 V
0 V
165 Ω
165 Ω
Input
1.5 V
10%
1.5 V
t
t
PHL
PLH
V
OD
V
OD(H)
Signal
Generator
90% 90%
Output
50 Ω
0 V
V
10%
OD(L)
60 pF
375 Ω
t
t
f
r
5 V
0 V
S2
† PRR = 1 MHz, 50% Duty Cycle, t < 6 ns, t < 6 ns, Z = 50 Ω
r
f
o
‡ Includes Probe and Jig Capacitance
Figure 4. Driver Switching Test Circuit and Waveforms, HVD SCSI-Loading (double terminated)
A
S1
Output
0 V or 3 V
B
R
= 110 Ω
C
= 50 pF
L
L
Input
Generator
50 Ω
† 3 V if testing A output, 0 V if testing B output
‡ PRR = 1 MHz, 50% Duty Cycle, t < 6 ns, t < 6 ns, Z = 50 Ω
r
f
o
Includes Probe and Jig Capacitance
3 V
0 V
Input
1.5 V
1.5 V
0.5 V
t
PZH
V
OH
Output
2.3 V
0 V
t
PHZ
Figure 5. Driver Enable/Disable Test, High Output
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC171, SN75LBC171
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS460A – NOVEMBER 2000 – REVISED FEBRUARY 2001
PARAMETER MEASUREMENT INFORMATION
5 V
R
= 110 Ω
A
B
L
S1
3 V
0 V
Input
t
0 V or 3 V
1.5 V
1.5 V
Output
C
= 50 pF
L
t
PZH
PHZ
Input
5 V
Output
2.3 V
Generator
50 Ω
V
OL
0.5 V
† 0 V if testing A output, 3 V if testing B output
‡ PRR = 1 MHz, 50% Duty Cycle, t < 6 ns, t < 6 ns, Z = 50 Ω
r
f
o
Includes Probe and Jig Capacitance
Figure 6. Driver Enable/Disable Test, Low Output
I
OS
I
O
V
O
V
ID
Voltage
Source
V
O
Figure 7. Driver Short-Circuit Test
Figure 8. Receiver DC Parameters
Generator
Input B
50 Ω
50 Ω
3 V
0 V
A
B
1.5 V
I
O
Input A
R
V
ID
t
t
PHL
PLH
V
O
V
OH
‡
C
= 15 pF
Generator
90% 90%
L
Output
1.5 V
10%
1.5 V
10%
V
OL
t
t
f
r
† PRR = 1 MHz, 50% Duty Cycle, t < 6 ns, t < 6 ns, Z = 50 Ω
r
f
o
‡ Includes Probe and Jig Capacitance
Figure 9. Receiver Switching Test Circuit and Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC171, SN75LBC171
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS460A – NOVEMBER 2000 – REVISED FEBRUARY 2001
PARAMETER MEASUREMENT INFORMATION
V
CC
A
B
3 V
0 V
1.5 V
1 kΩ
R
1.5 V
1.5 V
C
= 15 pF
L
t
t
PHZ
PZH
EN
V
OH
V
OH
–0.5 V
1.5 V
Generator
GND
50 Ω
† PRR = 1 MHz, 50% Duty Cycle, t < 6 ns, t < 6 ns, Z = 50 Ω
r
f
o
‡ Includes Probe and Jig Capacitance
Figure 10. Receiver Enable/Disable Test, High Output
V
CC
A
B
3 V
0 V
–1.5 V
1 kΩ
1.5 V
R
1.5 V
C
= 15 pF
EN
L
t
t
PLZ
PZL
V
CC
1.5 V
V
OL
+ 0.5 V
V
Generator
OL
50 Ω
† PRR = 1 MHz, 50% Duty Cycle, t < 6 ns, t < 6 ns, Z = 50 Ω
r
f
o
‡ Includes Probe and Jig Capacitance
Figure 11. Receiver Enable/Disable Test, Low Output
100 Ω
Pulse
V
TEST
0 V
15 µs
Generator,
–V
TEST
1.5 ms
15-µs Duration,
1% Duty Cycle
Figure 12. Test Circuit and Waveform, Transient Over Voltage Test
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC171, SN75LBC171
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS460A – NOVEMBER 2000 – REVISED FEBRUARY 2001
TYPICAL CHARACTERISTICS
DIFFERENTIAL OUTPUT VOLTAGE
DIFFERENTIAL OUTPUT VOLTAGE
vs
vs
OUTPUT CURRENT
FREE-AIR TEMPERATURE
4
2.5
3.5
3
V
CC
= 5.25 V
2
V
CC
= 5 V
V
CC
= 5.25 V
2.5
2
1.5
V
CC
= 5 V
V
CC
= 4.75 V
1
0.5
0
1.5
1
V
= 4.75 V
CC
0.5
0
0
20
40
60
80
100
–60 –40 –20
0
20
40
60
80
100
I
O
– Output Current – mA
T
A
– Free-Air Temperature – °C
Figure 13
Figure 14
DRIVER PROPAGATION DELAY
vs
SUPPLY CURRENT
vs
SIGNALING RATE
FREE-AIR TEMPERATURE
12
11
10
165
160
155
All 3 Channels Driving
R
C
= 54 Ω,
= 50 pF (Each Channel),
L
L
Pseudorandom NRZ Data
SCSI Load
9
8
7
6
5
4
150
145
140
135
RS–485 Load
–40
–20
0
20
40
60
80
0.1
1
10
100
T
– Free-Air Temperature – °C
A
Signaling Rate – Mbps
Figure 15
Figure 16
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC171, SN75LBC171
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS460A – NOVEMBER 2000 – REVISED FEBRUARY 2001
TYPICAL CHARACTERISTICS
BUS INPUT CURRENT
vs
BUS INPUT VOLTAGE
RECEIVER PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
800
600
12
11
10
V
= 0 V
V
CC
t
t
PHL
PLH
400
200
0
= 5 V
CC
9
8
7
6
5
4
–200
–400
–600
–10
–5
0
5
10
15
–40
–20
0
20
40
60
80
Bus Input Voltage – V
T
A
– Free-Air Temperature °C
Figure 17
Figure 18
SN65LBC171
(as Driver)
SN65LBC171
(as Receiver)
15 Meters, Cat. 5
Twisted-Pair Cable
Signal
Generator
100 Ω
15 pF
Figure 19. Circuit Diagram for Signaling Characteristics
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC171, SN75LBC171
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS460A – NOVEMBER 2000 – REVISED FEBRUARY 2001
TYPICAL CHARACTERISTICS
Driver Input
(5 V/div)
Driver Output
(2 V/div)
Receiver Input
(2 V/div)
25 ns
Receiver Output
(5 V/div)
Figure 20. Signal Waveforms at 30 Mbps
Driver Input
(5 V/div)
Driver Output
(2 V/div)
Receiver Input
(2 V/div)
12.5 ns
Receiver Output
(5 V/div)
Figure 21. Eye Patterns, Pseudorandom Data at 30 Mbps
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC171, SN75LBC171
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS460A – NOVEMBER 2000 – REVISED FEBRUARY 2001
TYPICAL CHARACTERISTICS
Driver Input
(5 V/div)
Driver Output
(2 V/div)
Receiver Input
(2 V/div)
25 ns
Receiver Output
(5 V/div)
Figure 22. Signal Waveforms at 50 Mbps
Driver Input
(5 V/div)
Driver Output
(2 V/div)
Receiver Input
(2 V/div)
12.5 ns
Receiver Output
(5 V/div)
Figure 23. Eye Patterns, Pseudorandom Data at 50 Mbps
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC171, SN75LBC171
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS460A – NOVEMBER 2000 – REVISED FEBRUARY 2001
MECHANICAL DATA
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,15 NOM
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /D 09/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC171, SN75LBC171
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS460A – NOVEMBER 2000 – REVISED FEBRUARY 2001
MECHANICAL DATA
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PINS SHOWN
0.050 (1,27)
16
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
M
9
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.291 (7,39)
Gage Plane
0.010 (0,25)
1
8
0°–8°
0.050 (1,27)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.012 (0,30)
0.004 (0,10)
0.104 (2,65) MAX
PINS **
16
20
24
28
0.710
DIM
0.410
0.510
0.610
A MAX
A MIN
(10,41) (12,95) (15,49) (18,03)
0.400
0.500
0.600
0.700
(10,16) (12,70) (15,24) (17,78)
4040000/D 01/00
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
4-Dec-2006
PACKAGING INFORMATION
Orderable Device
SN65LBC171DB
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP
DB
20
20
20
20
20
20
20
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN65LBC171DBR
SN65LBC171DW
SN65LBC171DWG4
SN65LBC171DWR
SN65LBC171DWRG4
SN75LBC171DB
SSOP
SOIC
SOIC
SOIC
SOIC
SSOP
DB
DW
DW
DW
DW
DB
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75LBC171DBR
SN75LBC171DBRG4
SN75LBC171DW
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SOIC
DB
DB
DW
20
20
20
2500
2500
TBD
TBD
Call TI
Call TI
Call TI
Call TI
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75LBC171DWG4
ACTIVE
SOIC
DW
20
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75LBC171DWR
ACTIVE
ACTIVE
SOIC
SOIC
DW
DW
20
20
2500
2500
TBD
TBD
Call TI
Call TI
Call TI
Call TI
SN75LBC171DWRG4
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Dec-2006
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
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