SN75C3243DWG4 [TI]

TRIPLE LINE TRANSCEIVER, PDSO28, GREEN, PLASTIC, SOIC-28;
SN75C3243DWG4
型号: SN75C3243DWG4
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

TRIPLE LINE TRANSCEIVER, PDSO28, GREEN, PLASTIC, SOIC-28

驱动 光电二极管 接口集成电路 驱动器
文件: 总23页 (文件大小:938K)
中文:  中文翻译
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SN65C3243, SN75C3243  
www.ti.com ................................................................................................................................................. SLLS353HJUNE 1999REVISED SEPTEMBER 2008  
3-V TO 5.5-V MULTICHANNEL RS-232 COMPATIBLE LINE DRIVER/RECEIVER  
1
FEATURES  
DB, DW, OR PW PACKAGE  
Operates With 3-V to 5.5-V VCC Supply  
(TOP VIEW)  
Always-Active Noninverting Receiver Output  
(ROUT2B)  
C2+  
C2−  
V−  
C1+  
1
28  
2
27 V+  
Low Standby Current . . . 1 µA Typ  
3
26 VCC  
25 GND  
24 C1−  
External Capacitors . . . 4 × 0.1 µF  
RIN1  
RIN2  
RIN3  
RIN4  
RIN5  
DOUT1  
DOUT2  
DOUT3  
DIN3  
DIN2  
DIN1  
4
Accepts 5-V Logic Input With 3.3-V Supply  
Inter-Operable With SN65C3238, SN75C3238  
5
6
23  
22  
21  
20  
19  
18  
17  
16  
15  
FORCEON  
FORCEOFF  
INVALID  
ROUT2B  
ROUT1  
Supports Operation From 250 kbit/s to  
1 Mbit/s  
7
8
9
RS-232 Bus-Pin ESD Protection Exceeds  
±15 kV Using Human-Body Model (HBM)  
10  
11  
12  
13  
14  
ROUT2  
ROUT3  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
ROUT4  
ROUT5  
APPLICATIONS  
Battery-Powered Systems  
PDAs  
Notebooks  
Laptops  
Palmtop PCs  
Hand-Held Equipment  
DESCRIPTION/ORDERING INFORMATION  
The SN65C3243 and SN75C3243 consist of three line drivers, five line receivers, and a dual charge-pump circuit  
with ±15-kV ESD protection pin to pin (serial-port connection pins, including GND). This device provides the  
electrical interface between an asynchronous communication controller and the serial-port connector. The charge  
pump and four small external capacitors allow operation from a single 3-V to 5.5-V supply. In addition, this device  
includes an always-active noninverting output (ROUT2B), which allows applications using the ring indicator to  
transmit data while the device is powered down. The device operates at data signaling rates up to 1 Mbit/s and  
an increased slew-rate range of 24 V/µs to 150 V/µs.  
Flexible control options for power management are available when the serial port is inactive. The  
auto-powerdown feature functions when FORCEON is low and FORCEOFF is high. During this mode of  
operation, if the device does not sense a valid RS-232 signal, the driver outputs are disabled. If FORCEOFF is  
set low, both drivers and receivers (except ROUT2B) are shut off, and the supply current is reduced to 1 µA.  
Disconnecting the serial port or turning off the peripheral drivers causes the auto-powerdown condition to occur.  
Auto-powerdown can be disabled when FORCEON and FORCEOFF are high and should be done when driving  
a serial mouse. With auto-powerdown enabled, the device is activated automatically when a valid signal is  
applied to any receiver input. The INVALID output is used to notify the user if an RS-232 signal is present at any  
receiver input. INVALID is high (valid data) if any receiver input voltage is greater than 2.7 V or less than –2.7 V  
or has been between –0.3 V and 0.3 V for less than 30 µs. INVALID is low (invalid data) if all receiver input  
voltages are between –0.3 V and 0.3 V for more than 30 µs. Refer to Figure 5 for receiver input levels.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1999–2008, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
SN65C3243, SN75C3243  
SLLS353HJUNE 1999REVISED SEPTEMBER 2008 ................................................................................................................................................. www.ti.com  
ORDERING INFORMATION  
TA  
PACKAGE(1)(2)  
ORDERABLE PART NUMBER  
SN75C3243DW  
TOP-SIDE MARKING  
75C3243  
Tube of 20  
SOIC – DW  
SSOP – DB  
TSSOP – PW  
Reel of 1000  
Reel of 2000  
Tube of 50  
SN75C3243DWR  
SN75C3243DBR  
SN75C3243PW  
0°C to 70°C  
75C3243  
CA3243  
Reel of 2000  
Tube of 20  
SN75C3243PWR  
SN65C3243DW  
SOIC – DW  
SSOP – DB  
TSSOP – PW  
65C3243  
65C3243  
CB3243  
Reel of 1000  
Reel of 2000  
Tube of 50  
SN65C3243DWR  
SN65C3243DBR  
SN65C3243PW  
–40°C to 85°C  
Reel of 2000  
SN65C3243PWR  
(1) Package drawings, thermal data, symbolization are available at www.ti.com/sc/packaging.  
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
website at www.ti.com.  
FUNCTION TABLES  
EACH DRIVER(1)  
INPUTS  
OUTPUT  
DOUT  
DRIVER STATUS  
VALID RIN  
RS-232 LEVEL  
DIN  
FORCEON  
FORCEOFF  
X
L
X
H
H
L
L
X
X
Z
H
L
Powered off  
H
H
H
H
H
H
Normal operation with auto-powerdown disabled  
H
L
X
Yes  
Yes  
No  
No  
H
L
Normal operation with auto-powerdown enabled  
Powered off by auto-powerdown feature  
H
L
L
L
Z
Z
H
L
(1) H = high level, L = low level, X = irrelevant, Z = high impedance  
EACH RECEIVER(1)  
INPUTS  
OUTPUTS  
VALID RIN  
RS-232  
LEVEL  
RECEIVER STATUS  
RIN1,  
RIN3–RIN5  
ROUT1,  
ROUT3–5  
RIN2  
FORCEOFF  
ROUT2B ROUT2  
L
H
X
X
L
L
X
L
H
L
Z
Z
H
L
Z
Z
H
L
Powered off while  
ROUT2B is active  
X
L
L
H
H
H
H
H
YES  
YES  
YES  
YES  
YES  
L
H
L
Normal operation with  
auto-powerdown  
disabled/enabled  
H
L
H
H
L
H
L
H
L
H
H
Open  
Open  
H
H
(1) H = high level, L = low level, X = irrelevant, Z = high impedance (off), Open = input disconnected or connected driver off  
2
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Copyright © 1999–2008, Texas Instruments Incorporated  
Product Folder Link(s): SN65C3243 SN75C3243  
SN65C3243, SN75C3243  
www.ti.com ................................................................................................................................................. SLLS353HJUNE 1999REVISED SEPTEMBER 2008  
LOGIC DIAGRAM (POSITIVE LOGIC)  
14  
13  
12  
9
10  
11  
DIN1  
DIN2  
DIN3  
DOUT1  
DOUT2  
DOUT3  
22  
23  
FORCEOFF  
FORCEON  
21  
INVALID  
Auto-Powerdown  
19  
20  
4
5
ROUT1  
RIN1  
RIN2  
ROUT2B  
18  
17  
16  
15  
ROUT2  
6
7
8
ROUT3  
ROUT4  
ROUT5  
RIN3  
RIN4  
RIN5  
Copyright © 1999–2008, Texas Instruments Incorporated  
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Product Folder Link(s): SN65C3243 SN75C3243  
SN65C3243, SN75C3243  
SLLS353HJUNE 1999REVISED SEPTEMBER 2008 ................................................................................................................................................. www.ti.com  
ABSOLUTE MAXIMUM RATINGS(1)  
over operating free-air temperature range (unless otherwise noted)  
MIN  
–0.3  
–0.3  
0.3  
MAX  
6
UNIT  
VCC  
V+  
Supply voltage range(2)  
Positive-output supply voltage range(2)  
Negative-output supply voltage range(2)  
V
V
V
V
7
V–  
–7  
V+ – V– Supply voltage difference(2)  
13  
6
Driver (FORCEOFF, FORCEON)  
Receiver  
–0.3  
–25  
VI  
Input voltage range  
Output voltage range  
V
V
25  
13.2  
62  
46  
62  
150  
150  
VO  
Driver  
–13.2  
DB package  
θJA  
Package thermal impedance(3)(4)  
DW package  
°C/W  
PW package  
TJ  
Operating virtual junction temperature  
Storage temperature range  
°C  
°C  
Tstg  
–65  
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating  
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) All voltages are with respect to network GND.  
(3) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient  
temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.  
(4) The package thermal impedance is calculated in accordance with JESD 51-7.  
RECOMMENDED OPERATING CONDITIONS(1)  
see Figure 6  
MIN  
3
NOM  
3.3  
5
MAX UNIT  
VCC = 3.3 V  
VCC = 5 V  
VCC = 3.3 V  
VCC = 5 V  
3.6  
V
Supply voltage  
4.5  
2
5.5  
VIH  
Driver and control high-level input voltage DIN, FORCEOFF, FORCEON  
Driver and control low-level input voltage DIN, FORCEOFF, FORCEON  
V
2.4  
VIL  
VI  
0.8  
5.5  
25  
85  
70  
V
V
V
Driver and control input voltage  
Receiver input voltage  
DIN, FORCEOFF, FORCEON  
0
–25  
–40  
0
VI  
SN65C3243  
SN75C3243  
TA  
Operating free-air temperature  
°C  
(1) Test conditions are C1–C4 = 0.1 µF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 µF, C2–C4 = 0.33 µF at VCC = 5 V ± 0.5 V.  
ELECTRICAL CHARACTERISTICS(1)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 6)  
PARAMETER  
TEST CONDITIONS  
MIN TYP(2)  
MAX UNIT  
II  
Input leakage current  
FORCEOFF, FORCEON  
±0.01  
±1  
µA  
No load,  
Auto-powerdown disabled  
Powered off  
0.3  
1
1
mA  
FORCEOFF and FORCEON = VCC  
No load, FORCEOFF = GND  
10  
ICC  
Supply current  
No load, FORCEOFF = VCC  
,
µA  
FORCEON = GND,  
All RIN are open or grounded,  
All DIN are grounded  
Auto-powerdown enabled  
1
10  
(1) Test conditions are C1–C4 = 0.1 µF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 µF, C2–C4 = 0.33 µF at VCC = 5 V ± 0.5 V.  
(2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.  
4
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Copyright © 1999–2008, Texas Instruments Incorporated  
Product Folder Link(s): SN65C3243 SN75C3243  
SN65C3243, SN75C3243  
www.ti.com ................................................................................................................................................. SLLS353HJUNE 1999REVISED SEPTEMBER 2008  
DRIVER SECTION  
Electrical Characteristics(1)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 6)  
PARAMETER  
TEST CONDITIONS  
All DOUT at RL = 3 kto GND  
MIN TYP(2)  
MAX UNIT  
High-level output  
voltage  
VOH  
VOL  
VO  
5
–5  
±5  
5.4  
V
Low-level output  
voltage  
All DOUT at RL = 3 kto GND  
–5.4  
V
V
Output voltage  
(mouse driveability)  
DIN1 = DIN2 = GND, DIN3 = VCC, 3-kto GND at DOUT3,  
DOUT1 = DOUT2 = 2.5 mA  
IIH  
IIL  
High-level input current VI = VCC  
Low-level input current VI = GND  
±0.01  
±0.01  
±35  
±1  
±1  
µA  
µA  
VCC = 3.6 V,  
VCC = 5.5 V,  
VO = 0 V  
VO = 0 V  
±60  
±90  
Short-circuit output  
current(3)  
IOS  
ro  
mA  
±35  
Output resistance  
VCC, V+, and V– = 0 V, VO = ±2 V  
VO = ±12 V,  
300  
10M  
VCC = 3 V to 3.6 V  
±25  
±25  
Ioff  
Output leakage current FORCEOFF = GND  
µA  
VO = ±10 V,  
VCC = 4.5 V to 5.5 V  
(1) Test conditions are C1–C4 = 0.1 µF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 µF, C2–C4 = 0.33 µF at VCC = 5 V ± 0.5 V.  
(2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.  
(3) Short-circuit durations should be controlled to prevent exceeding the device absolute power dissipation ratings, and not more than one  
output should be shorted at a time.  
Switching Characteristics(1)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 6)  
PARAMETER  
TEST CONDITIONS  
CL = 1000 pF  
MIN TYP(2)  
MAX UNIT  
250  
1000  
1000  
25  
Maximum data rate  
(see Figure 1)  
RL = 3 k,  
One DOUT switching  
CL = 250 pF,  
VCC = 3 V to 4.5 V  
VCC = 4.5 V to 5.5 V  
See Figure 2  
kbit/s  
CL = 1000 pF,  
tsk(p)  
Pulse skew(3)  
Slew rate,  
SR(tr) transition region  
(see Figure 1)  
CL = 150 pF to 2500 pF, RL = 3 kto 7 k,  
CL = 150 pF to 1000 pF, RL = 3 kto 7 k,  
ns  
VCC = 3.3 V  
18  
150 V/µs  
(1) Test conditions are C1–C4 = 0.1 µF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 µF, C2–C4 = 0.33 µF at VCC = 5 V ± 0.5 V.  
(2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.  
(3) Pulse skew is defined as |tPLH – tPHL| of each channel of the same device.  
Copyright © 1999–2008, Texas Instruments Incorporated  
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Product Folder Link(s): SN65C3243 SN75C3243  
SN65C3243, SN75C3243  
SLLS353HJUNE 1999REVISED SEPTEMBER 2008 ................................................................................................................................................. www.ti.com  
RECEIVER SECTION  
Electrical Characteristics(1)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 6)  
PARAMETER  
High-level output voltage  
Low-level output voltage  
TEST CONDITIONS  
IOH = –1 mA  
IOL = 1.6 mA  
VCC = 3.3 V  
VCC = 5 V  
MIN  
TYP(2)  
MAX  
UNIT  
V
VOH  
VOL  
VCC – 0.6  
VCC – 0.1  
0.4  
2.4  
2.4  
V
1.6  
1.9  
VIT+  
Positive-going input threshold voltage  
Negative-going input threshold voltage  
V
V
VCC = 3.3 V  
VCC = 5 V  
0.6  
0.8  
1.1  
VIT–  
1.4  
Vhys  
Ioff  
ri  
Input hysteresis (VIT+ – VIT–  
)
0.5  
V
Output leakage current (except ROUT2B)  
Input resistance  
FORCEOFF = 0 V  
VI = ±3 V to ±25 V  
±0.05  
5
±10  
7
µA  
kΩ  
3
(1) Test conditions are C1–C4 = 0.1 µF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 µF, C2–C4 = 0.33 µF at VCC = 5 V ± 0.5 V.  
(2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.  
Switching Characteristics(1)  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)  
PARAMETER  
Propagation delay time, low- to high-level output  
Propagation delay time, high- to low-level output  
Output enable time  
TEST CONDITIONS  
CL = 150 pF, See Figure 3  
TYP(2)  
150  
150  
200  
200  
50  
UNIT  
ns  
tPLH  
tPHL  
ten  
CL = 150 pF, See Figure 3  
CL = 150 pF, RL = 3 k, See Figure 4  
CL = 150 pF, RL = 3 k, See Figure 4  
See Figure 3  
ns  
ns  
tdis  
Output disable time  
Pulse skew(3)  
ns  
tsk(p)  
ns  
(1) Test conditions are C1–C4 = 0.1 µF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 µF, C2–C4 = 0.33 µF at VCC = 5 V ± 0.5 V.  
(2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.  
(3) Pulse skew is defined as |tPLH – tPHL| of each channel of the same device.  
6
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Copyright © 1999–2008, Texas Instruments Incorporated  
Product Folder Link(s): SN65C3243 SN75C3243  
SN65C3243, SN75C3243  
www.ti.com ................................................................................................................................................. SLLS353HJUNE 1999REVISED SEPTEMBER 2008  
AUTO-POWERDOWN SECTION  
Electrical Characteristics  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5)  
PARAMETER  
TEST CONDITIONS  
MIN  
MAX  
UNIT  
Receiver input threshold  
for INVALID high-level output voltage  
VT+(valid)  
VT–(valid)  
VT(invalid)  
VOH  
FORCEON = GND, FORCEOFF = VCC  
2.7  
V
Receiver input threshold  
for INVALID high-level output voltage  
FORCEON = GND, FORCEOFF = VCC  
FORCEON = GND, FORCEOFF = VCC  
–2.7  
–0.3  
V
V
V
V
Receiver input threshold  
for INVALID low-level output voltage  
0.3  
0.4  
IOH = –1 mA, FORCEON = GND,  
FORCEOFF = VCC  
INVALID high-level output voltage  
INVALID low-level output voltage  
VCC – 0.6  
IOL = 1.6 mA, FORCEON = GND,  
FORCEOFF = VCC  
VOL  
Switching Characteristics  
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5)  
PARAMETER  
Propagation delay time, low- to high-level output  
TYP(1)  
1
UNIT  
µs  
tvalid  
tinvalid  
ten  
Propagation delay time, high- to low-level output  
Supply enable time  
30  
µs  
100  
µs  
(1) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.  
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Product Folder Link(s): SN65C3243 SN75C3243  
SN65C3243, SN75C3243  
SLLS353HJUNE 1999REVISED SEPTEMBER 2008 ................................................................................................................................................. www.ti.com  
PARAMETER MEASUREMENT INFORMATION  
3 V  
Input  
RS-232  
Output  
0 V  
Generator  
(see Note B)  
50 Ω  
C
L
t
t
TLH  
THL  
R
L
(see Note A)  
V
V
OH  
3 V  
−3 V  
3 V  
FORCEOFF  
3 V  
−3 V  
Output  
OL  
6 V  
tTHL or tTLH  
SR(tr) +  
TEST CIRCUIT  
NOTES: A. C includes probe and jig capacitance.  
VOLTAGE WAVEFORMS  
L
B. The pulse generator has the following characteristics: PRR = 1 Mbit/s, Z = 50 , 50% duty cycle, t 10 ns, t 10 ns.  
O
r
f
Figure 1. Driver Slew Rate  
3 V  
0 V  
Input  
1.5 V  
1.5 V  
RS-232  
Output  
Generator  
(see Note B)  
50 Ω  
C
L
t
t
PHL  
PLH  
R
L
(see Note A)  
V
V
OH  
3 V  
FORCEOFF  
50%  
50%  
Output  
OL  
TEST CIRCUIT  
NOTES: A. C includes probe and jig capacitance.  
VOLTAGE WAVEFORMS  
L
B. The pulse generator has the following characteristics: PRR = 1 Mbit/s, Z = 50 , 50% duty cycle, t 10 ns, t 10 ns.  
O
r
f
Figure 2. Driver Pulse Skew  
3 V or 0 V  
FORCEON  
3 V  
Input  
1.5 V  
1.5 V  
−3 V  
Output  
Generator  
(see Note B)  
t
t
PLH  
PHL  
50  
C
L
(see Note A)  
3 V  
FORCEOFF  
V
V
OH  
50%  
50%  
Output  
OL  
TEST CIRCUIT  
NOTES: A. C includes probe and jig capacitance.  
VOLTAGE WAVEFORMS  
L
B. The pulse generator has the following characteristics: Z = 50 , 50% duty cycle, t 10 ns, t 10 ns.  
O
r
f
Figure 3. Receiver Propagation Delay Times  
8
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Copyright © 1999–2008, Texas Instruments Incorporated  
Product Folder Link(s): SN65C3243 SN75C3243  
SN65C3243, SN75C3243  
www.ti.com ................................................................................................................................................. SLLS353HJUNE 1999REVISED SEPTEMBER 2008  
PARAMETER MEASUREMENT INFORMATION (continued)  
3 V  
Input  
1.5 V  
1.5 V  
V
CC  
GND  
0 V  
3 V or 0 V  
FORCEON  
S1  
t
t
PZH  
PHZ  
(S1 at GND)  
(S1 at GND)  
R
L
V
OH  
±3 V  
Output  
50%  
Output  
0.3 V  
C
L
(see Note A)  
FORCEOFF  
50 Ω  
t
t
PZL  
(S1 at V  
PLZ  
(S1 at V  
)
CC  
)
CC  
Generator  
(see Note B)  
0.3 V  
Output  
50%  
V
OL  
TEST CIRCUIT  
NOTES: A. C includes probe and jig capacitance.  
VOLTAGE WAVEFORMS  
L
B. The pulse generator has the following characteristics: Z = 50 , 50% duty cycle, t 10 ns, t 10 ns.  
O
r
f
C.  
D.  
t
t
and t  
and t  
are the same as t  
.
dis  
.
PLZ  
PZL  
PHZ  
PZH  
are the same as t  
en  
Figure 4. Receiver Enable and Disable Times  
Copyright © 1999–2008, Texas Instruments Incorporated  
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Product Folder Link(s): SN65C3243 SN75C3243  
SN65C3243, SN75C3243  
SLLS353HJUNE 1999REVISED SEPTEMBER 2008 ................................................................................................................................................. www.ti.com  
PARAMETER MEASUREMENT INFORMATION (continued)  
3 V  
2.7 V  
2.7 V  
0 V  
0 V  
Receiver  
Input  
−2.7 V  
−2.7 V  
t
ROUT  
−3 V  
Generator  
(see Note B)  
50  
t
valid  
invalid  
V
CC  
50% V  
50% V  
CC  
CC  
INVALID  
Output  
0 V  
t
en  
Auto-  
powerdown  
INVALID  
C = 30 pF  
V+  
V+  
L
(see Note A)  
0.3 V  
Supply  
Voltages  
V
CC  
FORCEOFF  
FORCEON  
0 V  
0.3 V  
DIN  
DOUT  
V−  
V−  
TEST CIRCUIT  
VOLTAGE WAVEFORMS  
Valid RS-232 Level, INVALID High  
2.7 V  
0.3 V  
Indeterminate  
If Signal Remains Within This Region  
for More Than 30 µs, INVALID Is Low  
0 V  
−0.3 V  
Indeterminate  
−2.7 V  
Valid RS-232 Level, INVALID High  
Auto-powerdowndisables drivers and reduces supply  
current to 1 µA.  
NOTES: A. C includes probe and jig capacitance.  
L
B. The pulse generator has the following characteristics: PRR = 5 kbit/s, Z = 50 , 50% duty cycle, t 10 ns, t 10 ns.  
O
r
f
Figure 5. INVALID Propagation Delay Times and Supply Enabling Time  
10  
Submit Documentation Feedback  
Copyright © 1999–2008, Texas Instruments Incorporated  
Product Folder Link(s): SN65C3243 SN75C3243  
SN65C3243, SN75C3243  
www.ti.com ................................................................................................................................................. SLLS353HJUNE 1999REVISED SEPTEMBER 2008  
PARAMETER MEASUREMENT INFORMATION (continued)  
28  
C1+  
27  
1
V+  
C2+  
C2−  
+
+
C3  
C2  
+
2
3
C1  
26  
V
CC  
+
C
BYPASS  
= 0.1 µF  
25  
24  
23  
V−  
GND  
C1−  
+
C4  
4
5
6
7
8
RIN1  
FORCEON  
FORCEOFF  
RIN2  
RIN3  
22  
Serial-Port Inputs  
RIN4  
RIN5  
21  
20  
INVALID  
ROUT2B  
9
DOUT1  
DOUT2  
19  
18  
17  
10  
ROUT1  
ROUT2  
Serial-Port Outputs  
5 kΩ  
11  
DOUT3  
5 kΩ  
Logic Outputs  
12  
13  
14  
DIN3  
DIN2  
DIN1  
ROUT3  
5 kΩ  
16  
15  
Logic Inputs  
ROUT4  
ROUT5  
5 kΩ  
5 kΩ  
C3 can be connected to V or GND.  
CC  
NOTE A: Resistor values shown are nominal.  
V
CC  
vs CAPACITOR VALUES  
V
CC  
C1  
C2, C3, and C4  
3.3 V ± 0.3 V  
5 V ± 0.5 V  
3 V to 5.5 V  
0.1 µF  
0.047 µF  
0.1 µF  
0.1 µF  
0.33 µF  
0.47 µF  
Figure 6. Typical Operating Circuit and Capacitor Values  
Copyright © 1999–2008, Texas Instruments Incorporated  
Submit Documentation Feedback  
11  
Product Folder Link(s): SN65C3243 SN75C3243  
PACKAGE OPTION ADDENDUM  
www.ti.com  
24-Jan-2013  
PACKAGING INFORMATION  
Orderable Device  
SN65C3243DBR  
Status Package Type Package Pins Package Qty  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
0 to 70  
Top-Side Markings  
Samples  
Drawing  
(1)  
(2)  
(3)  
(4)  
ACTIVE  
SSOP  
SSOP  
SSOP  
SOIC  
DB  
28  
28  
28  
28  
28  
28  
28  
28  
28  
28  
28  
28  
28  
28  
28  
28  
28  
2000  
2000  
2000  
20  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
65C3243  
SN65C3243DBRE4  
SN65C3243DBRG4  
SN65C3243DW  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
DB  
DB  
Green (RoHS  
& no Sb/Br)  
65C3243  
65C3243  
65C3243  
65C3243  
65C3243  
65C3243  
65C3243  
65C3243  
CB3243  
CB3243  
CB3243  
CB3243  
CB3243  
CB3243  
75C3243  
75C3243  
Green (RoHS  
& no Sb/Br)  
DW  
DW  
DW  
DW  
DW  
DW  
PW  
PW  
PW  
PW  
PW  
PW  
DB  
Green (RoHS  
& no Sb/Br)  
SN65C3243DWE4  
SN65C3243DWG4  
SN65C3243DWR  
SN65C3243DWRE4  
SN65C3243DWRG4  
SN65C3243PW  
SOIC  
20  
Green (RoHS  
& no Sb/Br)  
SOIC  
20  
Green (RoHS  
& no Sb/Br)  
SOIC  
1000  
1000  
1000  
50  
Green (RoHS  
& no Sb/Br)  
SOIC  
Green (RoHS  
& no Sb/Br)  
SOIC  
Green (RoHS  
& no Sb/Br)  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
SSOP  
SSOP  
Green (RoHS  
& no Sb/Br)  
SN65C3243PWE4  
SN65C3243PWG4  
SN65C3243PWR  
SN65C3243PWRE4  
SN65C3243PWRG4  
SN75C3243DBR  
50  
Green (RoHS  
& no Sb/Br)  
50  
Green (RoHS  
& no Sb/Br)  
2000  
2000  
2000  
2000  
2000  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
SN75C3243DBRE4  
DB  
Green (RoHS  
& no Sb/Br)  
0 to 70  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
24-Jan-2013  
Orderable Device  
Status Package Type Package Pins Package Qty  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
0 to 70  
0 to 70  
0 to 70  
0 to 70  
0 to 70  
0 to 70  
0 to 70  
0 to 70  
0 to 70  
0 to 70  
0 to 70  
0 to 70  
0 to 70  
Top-Side Markings  
Samples  
Drawing  
(1)  
(2)  
(3)  
(4)  
SN75C3243DBRG4  
SN75C3243DW  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SSOP  
SOIC  
DB  
DW  
DW  
DW  
DW  
DW  
DW  
PW  
PW  
PW  
PW  
PW  
PW  
28  
28  
28  
28  
28  
28  
28  
28  
28  
28  
28  
28  
28  
2000  
20  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
75C3243  
Green (RoHS  
& no Sb/Br)  
75C3243  
75C3243  
75C3243  
75C3243  
75C3243  
75C3243  
CA3243  
CA3243  
CA3243  
CA3243  
CA3243  
CA3243  
SN75C3243DWE4  
SN75C3243DWG4  
SN75C3243DWR  
SN75C3243DWRE4  
SN75C3243DWRG4  
SN75C3243PW  
SOIC  
20  
Green (RoHS  
& no Sb/Br)  
SOIC  
20  
Green (RoHS  
& no Sb/Br)  
SOIC  
1000  
1000  
1000  
50  
Green (RoHS  
& no Sb/Br)  
SOIC  
Green (RoHS  
& no Sb/Br)  
SOIC  
Green (RoHS  
& no Sb/Br)  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
TSSOP  
Green (RoHS  
& no Sb/Br)  
SN75C3243PWE4  
SN75C3243PWG4  
SN75C3243PWR  
SN75C3243PWRE4  
SN75C3243PWRG4  
50  
Green (RoHS  
& no Sb/Br)  
50  
Green (RoHS  
& no Sb/Br)  
2000  
2000  
2000  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Addendum-Page 2  
PACKAGE OPTION ADDENDUM  
www.ti.com  
24-Jan-2013  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) Only one of markings shown within the brackets will appear on the physical device.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 3  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
5-Feb-2013  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
SN65C3243DBR  
SN65C3243DWR  
SN65C3243PWR  
SN65C3243PWR  
SN75C3243DBR  
SN75C3243DWR  
SN75C3243PWR  
SSOP  
SOIC  
DB  
DW  
PW  
PW  
DB  
28  
28  
28  
28  
28  
28  
28  
2000  
1000  
2000  
2000  
2000  
1000  
2000  
330.0  
330.0  
330.0  
330.0  
330.0  
330.0  
330.0  
16.4  
32.4  
16.4  
16.4  
16.4  
32.4  
16.4  
8.2  
10.5  
2.5  
3.1  
1.8  
1.8  
2.5  
3.1  
1.8  
12.0  
16.0  
12.0  
12.0  
12.0  
16.0  
12.0  
16.0  
32.0  
16.0  
16.0  
16.0  
32.0  
16.0  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
11.35 18.67  
TSSOP  
TSSOP  
SSOP  
SOIC  
6.9  
6.9  
8.2  
10.2  
10.2  
10.5  
DW  
PW  
11.35 18.67  
6.9 10.2  
TSSOP  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
5-Feb-2013  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
SN65C3243DBR  
SN65C3243DWR  
SN65C3243PWR  
SN65C3243PWR  
SN75C3243DBR  
SN75C3243DWR  
SN75C3243PWR  
SSOP  
SOIC  
DB  
DW  
PW  
PW  
DB  
28  
28  
28  
28  
28  
28  
28  
2000  
1000  
2000  
2000  
2000  
1000  
2000  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
367.0  
38.0  
55.0  
38.0  
38.0  
38.0  
55.0  
38.0  
TSSOP  
TSSOP  
SSOP  
SOIC  
DW  
PW  
TSSOP  
Pack Materials-Page 2  
MECHANICAL DATA  
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001  
DB (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE  
28 PINS SHOWN  
0,38  
0,22  
0,65  
28  
M
0,15  
15  
0,25  
0,09  
5,60  
5,00  
8,20  
7,40  
Gage Plane  
1
14  
0,25  
A
0°ā8°  
0,95  
0,55  
Seating Plane  
0,10  
2,00 MAX  
0,05 MIN  
PINS **  
14  
16  
20  
24  
28  
30  
38  
DIM  
6,50  
5,90  
6,50  
5,90  
7,50  
8,50  
7,90  
10,50  
9,90  
10,50 12,90  
A MAX  
A MIN  
6,90  
9,90  
12,30  
4040065 /E 12/01  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-150  
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