SN75164B [TI]
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER; 八路通用接口总线收发器
| 型号： | SN75164B |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER |
| 文件： | 总12页 (文件大小：230K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN75164B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS011A – OCTOBER 1985 – REVISED FEBRUARY 1993
8-Channel Bidirectional Transceiver
N PACKAGE
(TOP VIEW)
Power-Up/Power-Down Protection
(Glitch Free)
ATN+EOI (OR Function) Output to Simplify
Board Layout
SC
TE
1
V
CC
ATN + EOI
REN
22
21
20
19
18
17
16
15
14
13
12
2
3
REN
IFC
Designed to Implement Control Bus
Interface for Multiple Controllers
4
IFC
5
NDAC
NRFD
DAV
EOI
NDAC
NRFD
Low-Power Dissipation . . . 72 mW Max Per
Channel
6
GPIB
I/O Ports
Terminal
I/O Ports
7
DAV
EOI
ATN
SRQ
DC
Fast Propagation Times . . . 22 ns Max
High-impedance PNP Inputs
8
9
ATN
Receiver Hysteresis . . . 650 mV Typ
10
11
SRQ
GND
Bus-Terminating Resistors Provided on
Driver Outputs
NC – No internal connection
No Loading of Bus When Device Is
Powered Down (V
= 0)
CC
NOT RECOMMENDED FOR NEW DESIGN
description
CHANNEL IDENTIFICATION TABLE
The SN75164B eight-channel general-purpose
interface bus transceiver is monolithic,
high-speed, low-power Schottky device designed
to meet the requirements of IEEE Standard
488-1978. Each transceiver is designed to
provide the bus-management and data-transfer
NAME
IDENTITY
CLASS
a
DC
TE
SC
Direction Control
Talk Enable
System Control
Control
ATN
SRQ
REN
IFC
Attention
Service Request
Remote Enable
Interface Clear
End or Identify
Bus
Management
signals between operating units of
a
multiple-controller instrumentation system. When
combined with the SN75160B octal bus
transceiver, the SN75164B provides the complete
16-wire interface for the IEEE-488 bus.
EOI
ATN Logical or EOI
Logic
ATN + EOI
DAV
NDAC
NRFD
Data Valid
Not Data Accepted
Not Ready for Data
Data
Transfer
The SN75164B features eight driver-receiver
pairs connected in a front-to-back configuration to
form input/output (I/O) ports at both the bus and terminal sides. All outputs are disabled (at a high-impedance
state) during V
power-up and power-down transitions for glitch-free operation. The direction of data flow
CC
through these driver-receiver pairs is determined by the DC, TE, and SC enable signals. The SN75164B is
identical to the SN75162B with the addition of an OR gate to help simplify board layouts in several popular
applications. The ATN and EOI signals are ORed to pin 21, which is a standard totem-pole output.
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75164B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS011A – OCTOBER 1985 – REVISED FEBRUARY 1993
description (contInued)
The driver outputs (GPIB I/O ports) feature active bus-terminating resistor circuits designed to provide a high
impedance to the bus when supply voltage V
is 0. The drivers are designed to handle loads up to 48 mA of
CC
sink current. Each receiver features pnp transistor inputs for high input impedance and an ensured hysteresis
of 400 mV for increased noise immunity. All receivers have 3-state outputs to present a high impedance to the
terminal when disabled.
The SN75164B is characterized for operation from 0°C to 70°C.
†
logic symbol
logic diagram (positive logic)
12
2
1
DC
TE
SC
ENI/G4
EN2/G5
EN3
12
DC
≥1
2
5
4
TE
EN6
14
15
ATN
EOI
9
1
ATN
1
SC
1
1
14
9
ATN
ATN
21
8
ATN+EOI
EOI
≥1
6
6
1
3
3
1
1
1
1
13
20
19
16
18
17
10
3
SRQ
REN
SRQ
REN
IFC
21
8
1
ATN+EOI
EOI
3
3
2
2
15
EOI
4
IFC
7
DAV
DAV
13
10
3
SRQ
REN
IFC
SRQ
2
2
1
1
5
NDAC
NRFD
NDAC
NRFD
6
2
20
REN
2
1
†
ThissymbolisinaccordancewithANSI/IEEEStd91-1984
and IEC Publication 617-12
19
4
7
IFC
16
DAV
DAV
18
5
6
NDAC
NRFD
NDAC
17
NRFD
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75164B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS011A – OCTOBER 1985 – REVISED FEBRUARY 1993
RECEIVE/TRANSMIT FUNCTION TABLE
CONTROLS
BUS-MANAGEMENT CHANNELS
DATA-TRANSFER CHANNELS
†
ATN
†
ATN
SC
DC
TE
SRQ
REN
IFC
EOI
DAV
NDAC
NRFD
(controlled by DC)
(controlled by SC)
(controlled by TE)
H
H
L
H
H
L
H
L
T
R
R
T
R
T
T
T
R
R
T
H
L
R
R
T
L
L
H
L
L
X
X
R
T
T
R
T
R
T
T
T
H
R
R
R
H
L
T
T
R
R
H = high level, L = low level, R = receive, T = transmit, X = irrelevant
Direction of data transmission is from the terminal side to the bus side, and the direction of data receiving is from the bus side to the
terminal side. Data transfer is noninverting in both directions.
†
ATN is a normal transceiver channel that functions additionally as an internal direction control or talk enable for EOI whenever the DC
and TE inputs are in the same state. When DC and TE are in opposite states, the ATN channel functions as an independent transceiver
only.
ATN + EOI FUNCTION TABLE
INPUTS
OUTPUT
ATN+EOI
ATN
EOI
X
H
X
L
H
H
L
H
L
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75164B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS011A – OCTOBER 1985 – REVISED FEBRUARY 1993
schematics of inputs and outputs
EQUIVALENT OF ALL CONTROL INPUTS
TYPICAL OF SRQ, NDAC, AND NRFD GPIB I/O PORT
V
CC
V
CC
1.7 kΩ
NOM
10 kΩ
NOM
9 kΩ
NOM
Input
GND
4 kΩ
NOM
GND
Input/Output Port
Circuit inside dashed lines is on GPIB I/O ports only.
TYPICAL OF ALL I/O PORTS
EXCEPT SRQ, NDAC, AND NRFD GPIB I/O PORTS
ATN+EOI OUTPUT
V
CC
V
CC
R
eq
8 kΩ
200 Ω
1.7 kΩ
NOM
10 kΩ
NOM
4.6 kΩ
4 kΩ
NOM
Output
GND
4 kΩ
NOM
1.3 kΩ
2.5 kΩ
GND
Input/Output Port
Driver output R = 30 Ω NOM
eq
Receiver output R = 110 Ω NOM
eq
Circuit inside dashed lines is on GPIB I/O ports only.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
I
Low-level driver output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2) . . . . . . . . . . . . . . 1700 mW
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package . . . . . . . . . . . . . . . 260°C
NOTES: 1. All voltage values are with respect to network ground terminal.
2. For operation above 25°C free-air temperature, derate the N package at the rate of 13.6 mW/°C.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75164B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS011A – OCTOBER 1985 – REVISED FEBRUARY 1993
recommended operating conditions
MIN NOM
MAX
UNIT
V
Supply voltage, V
4.75
2
5
5.25
CC
High-level Input voltage, V
V
IH
Low-level Input voltage, V
0.8
–5.2
–800
–400
48
V
IL
Bus ports with 3-state outputs
Terminal ports
ATN+EOI
mA
High-level output current, I
OH
µA
Bus ports
Low-level output current, I
Terminal ports
ATN+EOI
16
mA
OL
4
Operating free-air temperature, T
0
70
°C
A
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
Input clamp voltage
I = –18 mA
I
–1.5
IK
Hysteresis (V + – V –)
Bus
See Figure 8
0.4
2.7
2.5
2.7
V
hys
T
T
Terminal
Bus
I
I
I
I
I
I
= –800 µA
OH
OH
OH
OL
OL
OL
‡
V
V
High-level output voltage
Low-level output voltage
V
= –5.2 mA
= –400 µA
= 16 mA
= 48 mA
= 4 mA
OH
ATN+EOI
Terminal
Bus
0.5
0.5
V
OL
ATN+EOI
0.4
§
V = 5.5 V
100
200
Terminal
Input current at maximum
input voltage
I
I
I
µA
µA
I
ATN+EOI V = 5.5 V
I
Terminal,
V = 2.7 V
I
20
40
control
High-level input current
IH
IL
ATN, EOI V = 2.7 V
I
Terminal,
V = 0.5 V
I
–100
control
I
Low-level input current
Voltage at bus port
µA
ATN, EOI V = 0.5 V
–500
3.7
I
I
I
= 0
2.5
I(bus)
V
I/O(bus)
Driver disabled
V
= –12 mA
–1.5
I(bus)
V
V
= –1.5 V to 0.4 V
= 0.4 V to 2.5 V
–1.3
0
I(bus)
I(bus)
–3.2
+2.5
–3.2
2.5
Power on Driver disabled
V
I(bus)
= 2.5 V to 3.7 V
mA
I
Current into bus port
I/O(bus)
V
I(bus)
V
I(bus)
V
I(bus)
= 3.7 V to 5 V
= 5 V to 5.5 V
= 0 V to 2.5 V
0
0.7
2.5
Power off
Terminal
Bus
V
= 0,
–40
–75
–125
–100
120
µA
CC
–15
–25
–10
I
I
Short-circuit output current
mA
OS
ATN+EOI
Supply current
No load,
= 5 V to 0 V,
TE, DE, and SC low
= 0 to 2 V, f = 1 MHz
mA
pF
CC
C
Bus-port capacitance
V
CC
V
I/O
30
I/O(bus)
†
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
applies for 3-state outputs only.
V
OH
Except ATN and EOI terminal pins
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75164B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS011A – OCTOBER 1985 – REVISED FEBRUARY 1993
switching characteristics, V
= 5 V, C = 15 pF, T = 25°C (unless otherwise noted)
L A
CC
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
PARAMETER
MIN TYP
MAX
UNIT
t
t
Propagation delay time, low-to-high level output
14
14
20
20
PLH
C = 30 pF,
L
Terminal
Terminal
Bus
Bus
ns
See Figure 1
Propagation delay time, high-to-low level output
PHL
Bus
(SRQ,
NDAC, NRFD)
C
= 30 pF,
L
t
Propagation delay time, low-to-high level output
29
35
ns
ns
ns
PLH
See Figure 1
C = 30 pF,
L
t
t
Propagation delay time, low-to-high level output
Propagation delay time, high-to-low level output
10
15
20
22
PLH
Terminal
See Figure 2
PHL
Terminal ATN
or
Terminal EOI
t
Propagation delay time, low-to-high level output
Propagation delay time, high-to-low level output
ATN+EOI
See Figure 3
14
14
PLH
PHL
Terminal ATN
or
Terminal EOI
t
ATN+EOI
See Figure 3
See Figure 4
ns
ns
t
t
t
t
t
t
t
t
Output enable time to high level
Output disable time from high level
Output enable time to low level
Output disable time from low level
Output enable time to high level
Output disable time from high level
Output enable time to low level
Output disable time from low level
60
45
60
55
55
50
45
55
PZH
PHZ
PZL
PLZ
PZH
PHZ
PZL
PLZ
Bus
TE, DC,
or SC
(ATN, EOI,
REN, IFC,
and DAV)
TE,DC,
or SC
Terminal
See Figure 5
ns
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75164B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS011A – OCTOBER 1985 – REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
5 V
4.3 V
200 Ω
240 Ω
From (bus)
Output Under
Test
From (terminal)
Output Under Test
Test Point
Test Point
C
= 30 pF
L
C
= 30 pF
480 Ω
L
3 kΩ
(see Note A)
(see Note A)
LOAD CIRCUIT
LOAD CIRCUIT
3 V
0 V
3 V
0 V
Terminal
Input
1.5 V
1.5 V
Bus
Input
1.5 V
1.5 V
(see Note B)
(see Note B)
t
t
PHL
t
PLH
t
PLH
PHL
1.5 V
V
OH
OL
V
OH
OL
2.2 V
Bus
Output
Terminal
Output
1.5 V
1.0 V
V
V
VOLTAGE WAVEFORMS
C includes probe and jig capacitance.
L
VOLTAGE WAVEFORMS
C includes probe and jig capacitance.
L
NOTES: A.
NOTES: A.
B. The input pulse is supplied by a generator
B. The input pulse is supplied by a generator
having the following characteristics: PRR ≤ 1 MHz,
havingthefollowingcharacteristics:PRR≤ 1 MHz,
50% duty cycle,
= 50 Ω.
t
≤
6
ns,
t
≤
ns,
50% duty cycle,
= 50 Ω.
t
≤
6
ns,
t
≤
ns,
r
f
r
f
Z
Z
O
O
Figure 1. Terminal-to-Bus
Load Circuit and Voltage Waveforms
Figure 2. Bus-to-Terminal
Load Circuit and Voltage Waveforms
3 V
V
CC
Test Point
Terminal
ATN+EOI
1.5 V
1.5 V
0 V
2 kΩ
t
t
PHL
PLH
V
OH
OL
ATN+EOI
1.5 V
1.5 V
V
From
ATN+EOI
VOLTAGE WAVEFORMS
C
(see Note B)
L
(see Note A)
LOAD CIRCUIT
C includes probe and jig capacitance.
L
NOTES: A.
B. All diodes are 1N916 or 1N3064.
Figure 3. ATN+EOI Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75164B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS011A – OCTOBER 1985 – REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
S1
5 V
S1
240 Ω
4.3 V
200 Ω
From (bus)
Output Under
Test
Test Point
From (terminal)
Output Under Test
Test Point
C
= 15 pF
L
C
= 15 pF
480 Ω
L
3 kΩ
(see Note A)
(see Note A)
LOAD CIRCUIT
LOAD CIRCUIT
3 V
0 V
3 V
Control
Input
1.5 V
1.5 V
Control
Input
1.5 V
1.5 V
(see Note B)
(see Note B)
0 V
t
t
PHZ
PZH
t
t
PHZ
PZH
V
OH
90%
V
OH
Terminal
Output
S1 Open
t
Bus Output
S1 Open
90%
2 V
1.5 V
1.0 V
0 V
0 V
4 V
t
t
PLZ
PZL
t
PZL
PLZ
≈3.5 V
Bus Output
S1 Closed
Terminal
Output
S1 Closed
1.0 V
VOLTAGE WAVEFORMS
C includes probe and jig capacitance.
L
0.5 V
V
OL
0.7 V
V
OL
VOLTAGE WAVEFORMS
NOTES: A.
NOTES: A.
C
L
includes probe and jig capacitance.
B. The input pulse is supplied by a generator
B. The input pulse is supplied by a generator
havingthe following characteristics: PRR ≤ 1 MHz,
havingthe following characteristics: PRR ≤ 1 MHz,
50% duty cycle,
= 50 Ω.
t
≤
6
ns,
t
f
≤ 6 ns,
50% duty cycle,
= 50 Ω.
t
≤
6
ns,
t
f
≤ 6 ns,
r
r
Z
Z
O
O
Figure 4. Bus Enable and Disable Times
Load Circuit and Voltage Waveforms
Figure 5. Terminal Enable and Disable
Times Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75164B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS011A – OCTOBER 1985 – REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
TERMINAL LOW-LEVEL OUTPUT VOLTAGE
TERMINAL HIGH-LEVEL OUTPUT VOLTAGE
vs
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT CURRENT
0.6
0.5
0.4
0.3
0.2
0.1
0
4
3.5
3
V
T
= 5 V
V
T
= 5 V
CC
= 25°C
CC
= 25°C
A
A
2.5
2
1.5
1
0.5
0
0
10
20
30
40
50
60
0
–5 –10 –15 –20 –25 –30 –35 –40
I
– Low-Level Output Current – mA
OL
I
– High-Level Output Current – mA
OH
Figure 6
Figure 7
TERMINAL OUTPUT VOLTAGE
vs
BUS INPUT VOLTAGE
4
3.5
3
V
= 5 V
CC
No Load
T
A
= 25°C
2.5
2
V
T–
V
T+
1.5
1
0.5
0
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
V – Input Voltage – V
I
Figure 8
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75164B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS011A – OCTOBER 1985 – REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
BUS LOW-LEVEL OUTPUT VOLTAGE
BUS HIGH-LEVEL OUTPUT VOLTAGE
vs
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT CURRENT
0.6
0.5
0.4
0.3
0.2
0.1
0
0
3
2
1
0
V
= 5 V
CC
V
= 5 V
CC
T
A
= 25°C
T
A
= 25°C
0
10
30 40 50 60 70 80 90 100
20
0
–10
–20
–40
–30
–50
–60
I
Ol
– Low-Level Output Current – mA
I
– High-Level Output Current – mA
OH
Figure 9
Figure 10
BUS OUTPUT VOLTAGE
vs
BUS CURRENT
vs
THERMAL INPUT VOLTAGE
BUS VOLTAGE
4
V
= 5 V
V
T
= 5 V
CC
No Load
= 25°C
CC
= 25°C
2
A
T
A
1
0
3
2
1
0
–1
–2
–3
–4
–5
–6
–7
The Unshaded
Area Conforms to
Paragraph 3.5.3 of
IEEE Standard 488-1978
–2
–1
0
1
2
3
4
5
6
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
V
I/O
(bus) – Bus Voltage – V
V – Input Voltage – V
I
Figure 11
Figure 12
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SN75164BN
OBSOLETE
PDIP
N
22
TBD
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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