SN75162BDWG4 [TI]
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS; 八路通用接口总线收发器
| 型号： | SN75162BDWG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS |
| 文件： | 总22页 (文件大小：980K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
SN75161B . . . DW OR N PACKAGE
Meets IEEE Standard 488-1978 (GPIB)
(TOP VIEW)
8-Channel Bidirectional Transceivers
Power-Up/Power-Down Protection
(Glitch Free)
TE
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
DC
Designed to Implement Control Bus
Interface
GPIB
I/O Ports
SN75161B Designed for Single Controller
Terminal
I/O Ports
SN75162B Designed for Multiple
Controllers
High-Speed, Low-Power Schottky Circuitry
Low Power Dissipation . . . 72 mW Max Per
Channel
Fast Propagation Times . . . 22 ns Max
High-Impedance pnp Inputs
SN75162B . . . DW PACKAGE
(TOP VIEW)
Receiver Hysteresis . . . 650 mV Typ
SC
TE
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
NC 11
GND 12
V
CC
NC
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
14
13
Bus-Terminating Resistors Provided on
Driver Outputs
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRQ
NC
No Loading of Bus When Device Is
Powered Down (V
= 0)
CC
Terminal
I/O Ports
GPIB
I/O Ports
description
The SN75161B and SN75162B eight-channel,
general-purpose interface bus transceivers are
monolithic, high-speed, low-power Schottky
devices designed to meet the requirements of
IEEE Standard 488-1978. Each transceiver is
designed to provide the bus-management and
data-transfer signals between operating units of
a single- or multiple-controller instrumentation
system. WhencombinedwiththeSN75160Boctal
bus transceiver, the SN75161B or SN75162B
provides the complete 16-wire interface for the
IEEE-488 bus.
DC
SN75162B . . . N PACKAGE
(TOP VIEW)
SC
TE
REN
IFC
NDAC
NRFD
DAV
EOI
V
CC
NC
REN
1
22
21
20
2
3
The SN75161B and SN75162B feature eight
driver-receiver pairs connected in a front-to-back
configuration to form input/output (I/O) ports at
both the bus and terminal sides. A power-
up/-down disable circuit is included on all bus and
receiver outputs. This provides glitch-free opera-
4
19 IFC
5
18 NDAC
17 NRFD
16 DAV
15 EOI
14 ATN
13 SRQ
12 DC
Terminal
I/O Ports
GPIB
I/O Ports
6
7
8
ATN
SRQ
GND
9
tion during V
power up and power down.
CC
10
11
NC–No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
description (continued)
The direction of data through these driver-receiver pairs is determined by the DC, TE, and SC (on SN75162B)
enable signals. The SC input on the SN75162B allows the REN and IFC transceivers to be controlled
independently.
The driver outputs (GPIB I/O ports) feature active bus-terminating resistor circuits designed to provide a high
impedance to the bus when supply voltage V
is 0. The drivers are designed to handle loads up to 48 mA of
CC
sink current. Each receiver features pnp transistor inputs for high input impedance and hysteresis of 400 mV
for increased noise immunity. All receivers have 3-state outputs to present a high impedance to the terminal
when disabled.
The SN75161B and SN75162B are characterized for operation from 0°C to 70°C.
Function Tables
SN75161B RECEIVE/TRANSMIT
CONTROLS
TE
BUS-MANAGEMENT CHANNELS
DATA-TRANSFER CHANNELS
†
ATN
†
ATN
DC
SRQ
REN
IFC
EOI
DAV
NDAC
NRFD
(Controlled by DC)
(Controlled by TE)
H
H
L
H
H
L
H
L
T
R
R
T
R
T
T
R
T
R
T
T
R
T
R
T
H
L
R
R
L
L
H
L
L
X
X
R
T
T
R
T
R
T
R
T
R
T
T
T
H
R
R
R
H = high level, L = low level, R = receive, T = transmit, X = irrelevant
Direction of data transmission is from the terminal side to the bus side, and the direction of data receiving is from the bus side to the terminal side.
Data transfer is noninverting in both directions.
†
ATN is a normal transceiver channel that functions additionally as an internal direction control or talk enable for EOI whenever the DC and TE
inputs are in the same state. When DC and TE are in opposite states, the ATN channel functions as an independent transceiver only.
SN75162B RECEIVE/TRANSMIT
CONTROLS
BUS-MANAGEMENT CHANNELS
SRQ REN IFC
(Controlled by DC) (Controlled by SC)
DATA-TRANSFER CHANNELS
†
ATN
†
ATN
SC
DC
TE
EOI
DAV
NDAC
NRFD
(Controlled by TE)
H
H
L
H
H
L
H
L
T
R
R
T
R
T
T
T
R
R
T
H
L
R
R
T
L
L
H
L
L
X
X
R
T
T
R
T
R
T
T
T
H
R
R
R
H
L
T
T
R
R
H = high level, L = low level, R = receive, T = transmit, X = irrelevant
Direction of data transmission is from the terminal side to the bus side, and the direction of data receiving is from the bus side to the terminal side.
Data transfer is noninverting in both directions.
†
ATN is a normal transceiver channel that functions additionally as an internal direction control or talk enable for EOI whenever the DC and TE
inputs are in the same state. When DC and TE are in opposite states, the ATN channel functions as an independent transceiver only.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
CHANNEL-IDENTIFICATION TABLE
NAME
DC
IDENTITY
Direction Control
CLASS
TE
Talk Enable
Control
SC
System Control (SN75162B only)
Attention
ATN
SRQ
REN
IFC
Service Request
Remote Enable
Interface Clear
Bus
Management
EOI
End of Identity
DAV
NDAC
NRFD
Data Valid
Not Data Accepted
Not Ready for Data
Data
Transfer
†
SN75161B logic symbol
SN75161B logic diagram (positive logic)
11
DC
TE
EN1/G4
EN2/G5
11
1
DC
1
5
1
TE
EN3
4
13
ATN
EOI
8
7
ATN
EOI
1
3
1
1
1
2
2
2
13
14
12
19
18
15
17
16
8
7
9
2
3
6
4
5
ATN
EOI
ATN
EOI
1
3
1
1
1
2
2
2
1
1
1
1
1
1
1
1
14
12
19
18
15
17
16
9
2
3
6
4
5
SRQ
REN
IFC
SRQ
REN
SRQ
REN
IFC
SRQ
REN
IFC
IFC
DAV
DAV
NDAC
NRFD
NDAC
NRFD
This symbol is in accordance with IEEE Std 91-1984 and
IEC Publication 617-12.
Designates 3-state outputs
DAV
DAV
NDAC
NRFD
Designates passive-pullup outputs
NDAC
NRFD
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
†
SN75162B logic symbol
SN75162B logic diagram (positive logic)
12
EN1/G4
EN2/G5
EN3
DC
12
2
DC
TE
TE
SC
1
2
1
≥ 1
5
EN3
SC
4
14
14
9
8
ATN
ATN
ATN
EOI
9
8
1
6
1
3
3
2
2
2
ATN
EOI
1
6
1
3
3
2
2
2
1
1
1
1
1
1
1
1
15
13
20
19
16
18
17
EOI
SRQ
REN
15
13
EOI
SRQ
REN
10
3
SRQ
REN
IFC
10
SRQ
REN
IFC
4
7
IFC
3
4
20
19
16
18
DAV
DAV
NDAC
NRFD
5
6
NDAC
NRFD
IFC
7
5
6
DAV
DAV
NDAC
NRFD
This symbol is in accordance with IEEE Std 91-1984 and
IEC Publication 617-12.
Designates 3-state outputs
Designates passive-pullup outputs
NDAC
NRFD
17
Pin numbers shown are for the N package.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
schematics of inputs and outputs
EQUIVALENT OF ALL CONTROL INPUTS
TYPICAL OF SRQ, NDAC, AND NRFD GPIB I/O PORT
V
CC
V
CC
1.7 kΩ
NOM
10 kΩ
NOM
9 kΩ
NOM
Input
GND
4 kΩ
NOM
GND
Input/Output Port
Circuit inside dashed lines is on the driver outputs only.
TYPICAL OF ALL I/O PORTS EXCEPT SRQ, NDAC,
AND NRFD GPIB I/O PORTS
V
CC
R
(eq)
1.7 kΩ
NOM
10 kΩ
NOM
4 kΩ
NOM
4 kΩ
NOM
GND
Input/Output Port
Driver output R
Receiver output R
(eq)
= 30 Ω NOM
(eq)
= 110 Ω NOM
Circuit inside dashed lines is on the driver outputs only.
= equivalent resistor
R
(eq)
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
I
Low-level driver output current, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
OL
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Lead temperature 1,6 mm (1/16) inch from the case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to network ground terminal.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T = 70°C
A
POWER RATING
A
PACKAGE
POWER RATING
ABOVE T = 25°C
A
DW (20 pin)
DW (24 pin)
N (20 pin)
1125 mW
9.0 mW/°C
10.8 mW/°C
9.2 mW/°C
13.6 mW/°C
720 mW
1350 mW
864 mW
1150 mW
736 mW
N (22 pin)
1700 mW
1088 mW
recommended operating conditions
MIN NOM
MAX
UNIT
V
Supply voltage, V
4.75
2
5
5.25
CC
High-level input voltage, V
V
IH
Low-level input voltage, V
0.8
–5.2
–800
48
V
IL
Bus ports with 3-state outputs
Terminal ports
mA
µA
High-level output current, I
OH
Bus ports
Low-level output current, I
mA
OL
Terminal ports
16
Operating free-air temperature, T
0
70
°C
A
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
†
PARAMETER
Input clamp voltage
Hysteresis voltage
TEST CONDITIONS
MIN
MAX
UNIT
TYP
V
V
I = –18 mA
–0.8
0.65
–1.5
V
IK
I
Bus
See Figure 7
0.4
V
V
hys
(V – V
)
IT+
IT–
Terminal
Bus
I
I
I
I
= –800 µA
= –5.2 mA
= 16 mA
2.7
2.5
3.5
3.3
OH
OH
OL
OL
‡
High-level output voltage
Low-level output voltage
V
OH
OL
Terminal
Bus
0.3
0.5
0.5
V
V
= 48 mA
0.35
Input current at maximum
input voltage
I
I
Terminal
V = 5.5 V
I
0.2
100
µA
I
I
High-level input current
Low-level input current
V = 2.7 V
0.1
20
µA
µA
IH
Terminal and
control inputs
I
V = 0.5 V
I
–10 –100
IL
I
I
= 0
2.5
3.0
3.7
I(bus)
V
Voltage at bus port
Driver disabled
Driver disabled
V
I/O(bus)
I/O(bus)
= –12 mA
–1.5
I(bus)
V
= –1.5 V to 0.4 V
= 0.4 V to 2.5 V
–1.3
0
I(bus)
I(bus)
V
–3.2
2.5
Power on
V
= 2.5 V to 3.7 V
mA
I(bus)
I
Current into bus port
–3.2
2.5
V
V
V
= 3.7 V to 5 V
= 5 V to 5.5 V
= 0 V to 2.5 V
0
I(bus)
I(bus)
I(bus)
0.7
2.5
Power off
Terminal
Bus
V
CC
= 0,
–40
–75
µA
mA
mA
pF
–15
–25
–35
I
I
Short-circuit output current
Supply current
OS
–50 –125
110
No load,
TE, DE, and SC low
CC
V
CC
V
I/O
= 5 V to 0,
C
Bus-port capacitance
16
I/O(bus)
= 0 to 2 V, f = 1 MHz
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
applies for 3-state outputs only.
V
OH
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
switching characteristics, V
= 5 V, C = 15 pF, T = 25°C (unless otherwise noted)
L A
CC
FROM
TO
TEST
PARAMETER
MIN
TYP
MAX
20
UNIT
(INPUT)
(OUTPUT)
CONDITIONS
Propagation delay time,
low- to high-level output
t
t
14
PLH
C
= 30 pF,
See Figure 1
L
Terminal
Bus
ns
Propagation delay time,
high- to low-level output
14
20
PHL
Bus
Propagation delay time,
low- to high-level output
C = 30 pF,
L
See Figure 1
t
Terminal (SRQ,NDAC,
NRFD)
29
35
ns
ns
PLH
Propagation delay time,
low- to high-level output
t
t
10
15
20
22
PLH
C
= 30 pF,
L
Bus
Terminal
See Figure 2
Propagation delay time,
high- to low-level output
PHL
t
t
t
t
t
t
t
t
Output enable time to high level
60
45
60
55
55
50
45
55
PZH
PHZ
PZL
PLZ
PZH
PHZ
PZL
PLZ
Bus (ATN,
EOI, REN,
IFC, and
DAV)
TE,DC,
or
SC
Output disable time from high level
Output enable time to low level
Output disable time from low level
Output enable time to high level
Output disable time from high level
Output enable time to low level
Output disable time from low level
See Figure 3
ns
ns
TE,DC,
or
SC
Terminal
See Figure 4
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
PARAMETER MEASUREMENT INFORMATION
5 V
200 Ω
From (Bus)
Test Point
Output Under
Test
C
= 30 pF
L
480 Ω
(see Note A)
LOAD CIRCUIT
3 V
0 V
Terminal
Input
1.5 V
1.5 V
See Note B
t
t
PHL
PLH
V
OH
OH
2.2 V
Bus
Output
1.0 V
VOLTAGE WAVEFORMS
V
NOTES: A.
C
L
includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, t ≤ 6 ns,
r
t ≤ 6 ns, Z = 50 Ω.
f
O
Figure 1. Terminal-to-Bus Load Circuit and Voltage Waveforms
4.3 V
240 Ω
From (Terminal)
Output Under
Test
Test Point
C
= 30 pF
L
3 kΩ
(see Note A)
LOAD CIRCUIT
3 V
0 V
Bus
Input
1.5 V
1.5 V
See Note B
t
t
PHL
PLH
V
V
OH
Terminal
Output
1.5 V
VOLTAGE WAVEFORMS
1.5 V
OL
NOTES: A.
C
L
includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, t ≤ 6 ns,
r
t ≤ 6 ns, Z = 50 Ω.
f
O
Figure 2. Bus-to-Terminal Load Circuit and Voltage Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
PARAMETER MEASUREMENT INFORMATION
S1
5 V
200 Ω
From (Bus)
Output Under
Test
Test Point
C
= 15 pF
L
480 Ω
(see Note A)
LOAD CIRCUIT
3 V
Control
Input
1.5 V
1.5 V
See Note B
0 V
t
t
PHZ
PZH
V
OH
90%
Bus
Output
2 V
S1 Open
0 V
t
t
PLZ
PZL
3.5 V
Bus
Output
S1 Closed
1 V
VOLTAGE WAVEFORMS
0.5 V
V
OL
NOTES: A.
C
L
includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, t ≤ 6 ns,
r
t ≤ 6 ns, Z = 50 Ω.
f
O
Figure 3. Bus Enable and Disable Times Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
PARAMETER MEASUREMENT INFORMATION
S1
4.3 V
240 Ω
From (Terminal)
Test Point
Output Under
Test
C
= 15 pF
L
3 kΩ
(see Note A)
LOAD CIRCUIT
3 V
0 V
Control
Input
1.5 V
1.5 V
See Note B
t
t
PHZ
PZH
V
OH
Output
Terminal
S1 Open
90%
1.5 V
0 V
4 V
V
t
t
PLZ
PZL
Terminal
Output
S1 Closed
1 V
VOLTAGE WAVEFORMS
0.7 V
OL
NOTES: A.
C
L
includes probe and jig capacitance.
B. The Input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle,
t ≤ 6 ns, t ≤ 6 ns, Z = 50 Ω.
r
f
O
Figure 4. Terminal Enable and Disable Times Load Circuit and Voltage Waveforms
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
TYPICAL CHARACTERISTICS
TERMINAL I/O PORTS
LOW-LEVEL OUTPUT VOLTAGE
vs
TERMINAL I/O PORTS
HIGH-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT CURRENT
0.6
0.5
0.4
0.3
0.2
0.1
0
4
3.5
3
V
= 5 V
CC
V
= 5 V
CC
= 25°C
T
A
= 25°C
T
A
2.5
2
1.5
1
0.5
0
0
10
20
30
40
50
60
0
–5 –10 –15 –20 –25 –30 –35 –40
I
– Low-Level Output Current – mA
OL
I
– High-Level Output Current – mA
OH
Figure 5
Figure 6
TERMINAL I/O PORTS
OUTPUT VOLTAGE
vs
BUS INPUT VOLTAGE
4
V
= 5 V
CC
No Load
= 25°C
3.5
3
T
A
2.5
2
V
IT–
V
IT+
1.5
1
0.5
0
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
V – Bus Input Voltage – V
I
Figure 7
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS005B – OCTOBER 1980 – REVISED MAY 1995
TYPICAL CHARACTERISTICS
GPIB I/O PORTS
HIGH-LEVEL OUTPUT VOLTAGE
vs
GPIB I/O PORTS
LOW-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
0
3
2
1
0
0.6
0.5
0.4
0.3
0.2
0.1
0
V
T
= 5 V
V
T
= 5 V
CC
CC
= 25°C
= 25°C
A
A
0
10 20 30 40 50 60 70 80 90 100
0
–10
–20
–40
–30
–50
–60
I
– Low-Level Output Current – mA
I
– High-Level Output Current – mA
OL
OH
Figure 8
Figure 9
GPIB I/O PORTS
OUTPUT VOLTAGE
vs
GPIB I/O PORTS
CURRENT
vs
THERMAL INPUT VOLTAGE
VOLTAGE
4
3
2
1
0
V
= 5 V
V
T
A
= 5 V
= 25°C
CC
No Load
= 25°C
CC
2
1
T
A
0
–1
–2
–3
–4
–5
–6
–7
The Unshaded
Area Conforms to
Paragraph 3.5.3 of
IEEE Standard 488-1978
–2
–1
0
1
2
3
4
5
6
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
V – Input Voltage – V
I
V
I/O
– Voltage – V
Figure 10
Figure 11
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
SN75161BDW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
OBSOLETE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
DW
20
20
20
20
20
20
20
24
24
24
24
24
24
22
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75161BDWG4
SN75161BDWR
SN75161BDWRE4
SN75161BDWRG4
SN75161BN
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
DW
DW
DW
DW
N
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN75161BNE4
SN75162BDW
N
20
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
DW
DW
DW
DW
DW
DW
N
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75162BDWE4
SN75162BDWG4
SN75162BDWR
SN75162BDWRE4
SN75162BDWRG4
SN75162BN
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TBD
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN75161BDWR
SN75161BDWR
SN75162BDWR
SOIC
SOIC
SOIC
DW
DW
DW
20
20
24
2000
2000
2000
330.0
330.0
330.0
24.4
24.4
24.4
10.8
10.8
13.3
13.0
2.7
2.7
2.7
12.0
12.0
12.0
24.0
24.0
24.0
Q1
Q1
Q1
10.75 15.7
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jan-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN75161BDWR
SN75161BDWR
SN75162BDWR
SOIC
SOIC
SOIC
DW
DW
DW
20
20
24
2000
2000
2000
367.0
367.0
367.0
367.0
367.0
367.0
45.0
45.0
45.0
Pack Materials-Page 2
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