SN75160B_13 [TI]
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER; 八路通用接口总线收发器
| 型号： | SN75160B_13 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER |
| 文件： | 总17页 (文件大小：917K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN75160B
OCTAL GENERAL-PURPOSE
INTERFACE BUS TRANSCEIVER
SLLS004B – OCTOBER 1985 – REVISED MAY 1995
Meets IEEE Standard 488-1978 (GPIB)
8-Channel Bidirectional Transceiver
DW OR N PACKAGE
(TOP VIEW)
Power-Up/Power-Down Protection
(Glitch Free)
TE
B1
VCC
D1
D2
D3
D4
D5
D6
D7
D8
PE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
High-Speed, Low-Power Schottky Circuitry
Low Power Dissipation . . . 72 mW Max Per
Channel
B2
B3
GPIB
I/O Ports
Fast Propagation Times . . . 22 ns Max
High-Impedance pnp Inputs
Terminal
I/O Ports
B4
B5
B6
Receiver Hysteresis . . . 650 mV Typ
Open-Collector Driver Output Option
No Loading of Bus When Device Is
B7
B8
GND
Powered Down (V
= 0)
CC
description
The SN75160B 8-channel general-purpose interface bus (GPIB) transceiver is a monolithic, high-speed,
low-power Schottky device designed for two-way data communications over single-ended transmission lines.
It is designed to meet the requirements of IEEE Standard 488-1978. The transceiver features driver outputs that
can be operated in either the passive-pullup or 3-state mode. If talk enable (TE) is high, these ports have the
characteristics of passive-pullup outputs when pullup enable (PE) is low and of 3-state outputs when PE is high.
Taking TE low places these ports in the high-impedance state. The driver outputs are designed to handle loads
up to 48 mA of sink current.
Output glitches during power up and power down are eliminated by an internal circuit that disables both the bus
and receiver outputs. The outputs do not load the bus when V
= 0. When combined with the SN75161B or
CC
SN75162B management bus transceivers, the pair provides the complete 16-wire interface for the IEEE-488
bus.
The SN75160B is characterized for operation from 0°C to 70°C.
Function Tables
EACH DRIVER
INPUTS
TE
EACH RECEIVER
INPUTS
OUTPUT
OUTPUT
D
H
L
PE
H
X
B
H
L
B
L
TE
L
PE
X
D
L
H
H
X
L
H
X
L
X
H
Z
†
H
X
L
Z
Z
H
X
†
X
H = high level, L = low level, X = irrelevant, Z = high impedance
†
This is the high-impedance state of a normal 3-state output modified by the internal resistors
to V and GND.
CC
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75160B
OCTAL GENERAL-PURPOSE
INTERFACE BUS TRANSCEIVER
SLLS004B – OCTOBER 1985 – REVISED MAY 1995
†
logic diagram (positive logic)
logic symbol
11
11
PE
PE
TE
M1[3S]
1
M2[0C]
TE
1
EN3[XMT]
19
EN4[RCV]
D1
19
D1
2
2
3
3(1 /2
)
B1
B1
B2
4
1
18
18
17
3
4
D2
D2
D3
B2
B3
16
15
5
6
D4
D5
B4
B5
17
14
13
7
8
D3
D6
D7
B6
B7
12
4
5
9
D8
B8
B3
B4
16
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
Designates 3-state outputs
D4
Terminal
I/O Ports
Designates passive-pullup outputs
15
D5
GPIB
I/O Ports
6
7
B5
B6
14
D6
13
D7
8
9
B7
B8
12
D8
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75160B
OCTAL GENERAL-PURPOSE
INTERFACE BUS TRANSCEIVER
SLLS004B – OCTOBER 1985 – REVISED MAY 1995
schematics of inputs and outputs
EQUIVALENT OF ALL CONTROL INPUTS
EQUIVALENT OF ALL INPUT/OUTPUT PORTS
V
CC
R
9 kΩ
NOM
(eq)
1.7 kΩ
NOM
10 kΩ
NOM
Input
GND
4 kΩ
NOM
4 kΩ
NOM
Input/Output Port
Driver output R
(eq)
= 30 Ω NOM
Receiver output R
= 110 Ω NOM
(eq)
Circuit inside dashed lines is on the driver outputs only.
= equivalent resistor
R
(eq)
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
I
Low-level driver output current, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
OL
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
≤ 25°C DERATING FACTOR
T
A
T = 70°C
A
POWER RATING
PACKAGE
POWER RATING
ABOVE T = 25°C
A
DW
N
1125 mW
9.0 mW/°C
9.2 mW/°C
720 mW
1150 mW
736 mW
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75160B
OCTAL GENERAL-PURPOSE
INTERFACE BUS TRANSCEIVER
SLLS004B – OCTOBER 1985 – REVISED MAY 1995
recommended operating conditions
MIN NOM
MAX
UNIT
V
Supply voltage, V
4.75
2
5
5.25
CC
High-level input voltage, V
V
IH
Low-level input voltage, V
0.8
–5.2
–800
48
V
IL
Bus ports with pullups active
Terminal ports
mA
µA
High-level output current, I
OH
Bus ports
Low-level output current, I
mA
OL
Terminal ports
16
Operating free-air temperature, T
0
70
°C
A
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
†
PARAMETER
Input clamp voltage
Hysteresis voltage
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
I = –18 mA
I
–0.8
0.65
–1.5
V
IK
Bus
See Figure 8
0.4
V
V
hys
(V
– V
)
IT+
IT–
Terminal
Bus
I
I
I
I
= –800 µA, TE at 0.8 V
2.7
2.5
3.5
3.3
OH
OH
OL
OL
V
OH
V
OL
High-level output voltage
Low-level output voltage
= –5.2 mA, PE and TE at 2 V
Terminal
Bus
= 16 mA,
= 48 mA,
TE at 0.8 V
TE at 2 V
0.3
0.5
0.5
V
0.35
Input current at maximum
input voltage
I
I
Terminal
V = 5.5 V
I
0.2
100
µA
I
I
High-level input current
Low-level input current
Terminal
Terminal
V = 2.7 V
0.1
20
µA
µA
IH
I
V = 0.5 V
I
–10 –100
IL
I
I
= 0
2.5
3.0
3.7
I(bus)
V
Voltage at bus port
Driver disabled
V
I/O(bus)
I/O(bus)
= –12 mA
–1.5
I(bus)
V
= –1.5 V to 0.4 V
= 0.4 V to 2.5 V
–1.3
0
I(bus)
I(bus)
V
–3.2
2.5
Power on Driver disabled
V
= 2.5 V to 3.7 V
I(bus)
I
Current into bus port
–3.2
2.5
mA
V
V
V
= 3.7 V to 5 V
= 5 V to 5.5 V
= 0 to 2.5 V
0
I(bus)
I(bus)
I(bus)
0.7
2.5
Power off
Terminal
Bus
V
CC
= 0,
–40
–75
–15
–25
–35
I
I
Short-circuit output current
Supply current
mA
mA
pF
OS
–50 –125
Receivers low and enabled
Drivers low and enabled
70
85
90
No load
CC
110
V
= 0 to 5 V,
V
= 0 to 2 V,
CC
f = 1 MHz
I/O
C
Bus-port capacitance
16
I/O(bus)
†
All typical values are at V
= 5 V, T = 25°C.
A
CC
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75160B
OCTAL GENERAL-PURPOSE
INTERFACE BUS TRANSCEIVER
SLLS004B – OCTOBER 1985 – REVISED MAY 1995
switching characteristics, V
= 5 V, C = 15 pF, T = 25°C (unless otherwise noted)
L A
CC
FROM
(INPUT) (OUTPUT)
TO
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
20
UNIT
Propation delay time,
low- to high-level output
t
t
t
t
14
PLH
PHL
PLH
PHL
C
= 30 pF,
L
Terminal
Bus
Bus
ns
See Figure 1
Propagation delay time,
high- to low-level output
14
20
Propagation delay time,
low- to high-level output
10
20
C
= 30 pF,
L
Terminal
ns
ns
See Figure 2
Propagation delay time,
high- to low-level output
15
22
t
t
t
t
t
t
t
t
t
t
Output enable time to high level
25
13
22
22
20
12
23
19
15
13
35
22
35
32
30
20
32
30
22
20
PZH
PHZ
PZL
PLZ
PZH
PHZ
PZL
PLZ
en
Output disable time from high level
Output enable time to low level
Output disable time from low level
Output enable time to high level
Output disable time from high level
Output enable time to low level
Output disable time from low level
Output pullup enable time
TE
BUS
See Figure 3
TE
PE
Terminal
Bus
See Figure 4
See Figure 5
ns
ns
Output pullup disable time
dis
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75160B
OCTAL GENERAL-PURPOSE
INTERFACE BUS TRANSCEIVER
SLLS004B – OCTOBER 1985 – REVISED MAY 1995
PARAMETER MEASUREMENT INFORMATION
5 V
PE
D
3 V
3 V
0 V
Output
200 Ω
480 Ω
D Input
1.5 V
1.5 V
Generator
(see Note A)
B
t
PLH
t
PHL
V
OH
OH
50 Ω
C
= 30 pF
L
2.2 V
B Output
(see Note B)
1.0 V
V
TE
3 V
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, t ≤ 6 ns,
r
t ≤ ns, Z = 50 Ω.
f
O
B.
C
L
includes probe and jig capacitance.
Figure 1. Terminal-to-Bus Test Circuit and Voltage Waveforms
TE
B
4.3 V
3 V
0 V
B Input
t
1.5 V
1.5 V
Output
240 Ω
t
PLH
Generator
(see Note A)
PHL
D
V
OH
OH
D Output
1.5 V
1.5 V
3 kΩ
50 Ω
C
= 30 pF
L
V
(see Note B)
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, t ≤ 6 ns,
r
t ≤ ns, Z = 50 Ω.
f
O
B.
C
L
includes probe and jig capacitance.
Figure 2. Bus-to-Terminal Test Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75160B
OCTAL GENERAL-PURPOSE
INTERFACE BUS TRANSCEIVER
SLLS004B – OCTOBER 1985 – REVISED MAY 1995
PARAMETER MEASUREMENT INFORMATION
5 V
3 V
3 V
0 V
200 Ω
Output
PE
1.5 V
1.5 V
TE Input
t
S1
S2
t
PHZ
D
B
PZH
V
OH
B Output
S1 to 3 V
S2 Open
90%
480 Ω
= 30 pF
2 V
0.8 V
3.5 V
C
L
t
PLZ
t
PZL
(see Note B)
B Output
S1 to GND
S2 Closed
Generator
(see Note A)
TE
1.0 V
0.5 V
V
OL
50 Ω
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, t ≤ 6 ns,
r
t ≤ ns, Z = 50 Ω.
f
O
B.
C
L
includes probe and jig capacitance.
Figure 3. TE-to-Bus Test Circuit and Voltage Waveforms
4.3 V
3 V
1.5 V
1.5 V
90%
TE
Generator
(see Note A)
TE Input
S2
Output
0 V
V
t
t
PHZ
PZH
240 Ω
50 Ω
D Output
S1 TO 3 V
S2 Open
OH
D
1.5 V
3 kΩ
= 15 pF
0 V
4 V
S1
B
3 V
t
t
PLZ
PZL
C
L
(see Note B)
D Output
1.0 V
S1 TO GND
S2 Closed
0.7 V
V
OL
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, t ≤ 6 ns, t ≤ ns,
r
f
Z
C
= 50 Ω.
O
L
B.
includes probe and jig capacitance.
Figure 4. TE-to-Terminal Test Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75160B
OCTAL GENERAL-PURPOSE
INTERFACE BUS TRANSCEIVER
SLLS004B – OCTOBER 1985 – REVISED MAY 1995
PARAMETER MEASUREMENT INFORMATION
Generator
(see Note A)
PE
D
Output
3 V
0 V
PE Input
1.5 V
1.5 V
B
50 Ω
t
t
en
dis
R
L
= 480 Ω
L
V
OH
OL
C
= 15 pF
(see Note B)
90%
B Output
2 V
V
= 0.8 V
3 V
TE
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, t ≤ 6 ns, t ≤ ns,
r
f
Z
C
= 50 Ω.
O
L
B.
includes probe and jig capacitance.
Figure 5. PE-to-Bus Pullup Test Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75160B
OCTAL GENERAL-PURPOSE
INTERFACE BUS TRANSCEIVER
SLLS004B – OCTOBER 1985 – REVISED MAY 1995
TYPICAL CHARACTERISTICS
TERMINAL I/O PORTS
TERMINAL I/O PORTS
HIGH-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
4
3.5
3
0.6
0.5
0.4
0.3
0.2
0.1
0
V
T
= 5 V
= 25°C
V
T
= 5 V
= 25°C
CC
A
CC
A
2.5
2
1.5
1
0.5
0
0
10
20
30
40
50
60
0
–5 –10 –15 –20 –25 –30 –35 –40
I
– Low-Level Output Current – mA
I
– High-Level Output Current – mA
OL
OH
Figure 6
Figure 7
TERMINAL I/O PORTS
OUTPUT VOLTAGE
vs
BUS INPUT VOLTAGE
4
V
= 5 V
CC
No Load
= 25°C
3.5
3
T
A
2.5
2
V
IT–
V
IT+
1.5
1
0.5
0
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
V – Bus Input Voltage – V
I
Figure 8
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75160B
OCTAL GENERAL-PURPOSE
INTERFACE BUS TRANSCEIVER
SLLS004B – OCTOBER 1985 – REVISED MAY 1995
TYPICAL CHARACTERISTICS
GPIB I/O PORTS
GPIB I/O PORTS
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0
3
2
1
0
0.6
0.5
0.4
0.3
0.2
0.1
0
V
T
A
= 5 V
= 25°C
CC
V
T
A
= 5 V
= 25°C
CC
0
–10
–20
–40
–30
–50
–60
0
10 20 30 40 50 60 70 80 90 100
I
– High-Level Output Current – mA
I
– Low-Level Output Current – mA
OH
OL
Figure 9
Figure 10
GPIB I/O PORTS
GPIB I/O PORTS
CURRENT
vs
VOLTAGE
OUTPUT VOLTAGE
vs
THERMAL INPUT VOLTAGE
4
3
2
1
0
V
T
A
= 5 V
V
= 5 V
CC
= 25°C
CC
No Load
= 25°C
2
1
T
A
0
–1
–2
–3
–4
–5
–6
–7
The Unshaded
Area Conforms to
Paragraph 3.5.3 of
IEEE Standard 488-1978
–2
–1
0
1
2
3
4
5
6
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
V
I/O
– Voltage – V
V – Thermal Input Voltage – V
I
Figure 11
Figure 12
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
SN75160BDW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
DW
20
20
20
20
20
20
20
20
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN75160BDWE4
SN75160BDWG4
SN75160BDWR
SN75160BDWRE4
SN75160BDWRG4
SN75160BN
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
DW
DW
DW
DW
DW
N
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN75160BNE4
N
20
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN75160BDWR
SN75160BDWR
SOIC
SOIC
DW
DW
20
20
2000
2000
330.0
330.0
24.4
24.4
10.8
10.8
13.0
13.3
2.7
2.7
12.0
12.0
24.0
24.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jan-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN75160BDWR
SN75160BDWR
SOIC
SOIC
DW
DW
20
20
2000
2000
367.0
367.0
367.0
367.0
45.0
45.0
Pack Materials-Page 2
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