SN74VMEH22501 [TI]
8 BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1 BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT FEEDBACK PATH AND 3 STATE OUTPUTS; 8位通用总线收发器和具备SPLIT LVTTL端口反馈路径中两个1位总线收发器和3态输出
| 型号： | SN74VMEH22501 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8 BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1 BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT FEEDBACK PATH AND 3 STATE OUTPUTS |
| 文件： | 总25页 (文件大小：439K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCES357E − JULY 2001 − REVISED MARCH 2004
DGG OR DGV PACKAGE
(TOP VIEW)
D
D
Member of the Texas Instruments
Widebus Family
UBT Transceiver Combines D-Type
Latches and D-Type Flip-Flops for
Operation in Transparent, Latched, or
Clocked Modes
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OEBY
1A
1OEAB
2
V
CC
3
1Y
1B
4
GND
2A
2Y
GND
BIAS V
2B
D
OEC Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
(EMI)
5
CC
6
7
V
V
CC
CC
8
D
D
Compliant With VME64, 2eVME, and 2eSST
Protocol
2OEBY
2OEAB
3B1
9
3A1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GND
LE
3A2
3A3
OE
GND
3A4
CLKBA
GND
Bus Transceiver Split LVTTL Port Provides
a Feedback Path for Control and
Diagnostics Monitoring
V
CC
3B2
3B3
D
D
D
D
I/O Interfaces Are 5-V Tolerant
V
CC
GND
3B4
CLKAB
B-Port Outputs (−48 mA/64 mA)
Y and A-Port Outputs (−12 mA/12 mA)
I
, Power-Up 3-State, and BIAS V
CC
off
Support Live Insertion
V
V
CC
CC
3A5
3A6
GND
3A7
3A8
DIR
3B5
3B6
GND
3B7
3B8
D
Bus Hold on 3A-Port Data Inputs
D
26-W Equivalent Series Resistor on
3A Ports and Y Outputs
D
D
D
D
Flowthrough Architecture Facilitates
Printed Circuit Board Layout
V
CC
Distributed V
High-Speed Switching Noise
and GND Pins Minimize
CC
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
TSSOP − DGG
TVSOP − DGV
VFBGA − GQL
Tape and reel
Tape and reel
Tape and reel
SN74VMEH22501DGGR
SN74VMEH22501DGVR
SN74VMEH22501GQLR
VMEH22501
VK501
0°C to 85°C
VK501
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Motorola is a trademark of Motorola, Inc.
OEC, UBT, and Widebus are trademarks of Texas Instruments.
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Copyright 2004, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅ ꢆꢇ ꢈꢈꢉ ꢊ ꢋ
ꢌꢍ ꢎꢏ ꢐ ꢑ ꢁꢏ ꢄ ꢆꢒ ꢀꢓ ꢔ ꢎꢑ ꢀ ꢐꢒ ꢓꢁ ꢀꢕ ꢆꢏ ꢄ ꢆ ꢒ ꢓꢁꢖ ꢐ ꢗ ꢘ ꢋ ꢍꢎꢏ ꢐ ꢎꢑꢀ ꢐ ꢒꢓꢁꢀ ꢕꢆꢏ ꢄꢆꢒꢀ
ꢗꢏ ꢐ ꢇ ꢀꢙ ꢔ ꢏ ꢐ ꢔꢄꢐ ꢐꢔ ꢙ ꢘꢒ ꢐꢚ ꢛꢆ ꢆ ꢖꢎ ꢓꢕꢜ ꢙꢓꢐ ꢇꢚ ꢓꢁꢖ ꢝ ꢍꢀꢐꢓꢐ ꢆ ꢘ ꢑꢐ ꢙꢑꢐ ꢀ
SCES357E − JULY 2001 − REVISED MARCH 2004
description/ordering information (continued)
The SN74VMEH22501 8-bit universal bus transceiver has two integral 1-bit three-wire bus transceivers and is
designed for 3.3-V V operation with 5-V tolerant inputs. The UBT transceiver allows transparent, latched,
CC
and flip-flop modes of data transfer, and the separate LVTTL input and outputs on the bus transceivers provide
a feedback path for control and diagnostics monitoring. This device provides a high-speed interface between
†
cards operating at LVTTL logic levels and VME64, VME64x, or VME320 backplane topologies.
High-speed backplane operation is a direct result of the improved OEC circuitry and high drive that has been
designed and tested into the VME64x backplane model. The B-port I/Os are optimized for driving large
capacitive loads and include pseudo-ETL input thresholds (1/2 V
50 mV) for increased noise immunity.
CC
These specifications support the 2eVME protocols in VME64x (ANSI/VITA 1.1) and 2eSST protocols in
VITA 1.5. With proper design of a 21-slot VME system, a designer can achieve 320-Mbyte transfer rates on
linear backplanes and, possibly, 1-Gbyte transfer rates on the VME320 backplane.
All inputs and outputs are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs.
Active bus-hold circuitry holds unused or undriven 3A-port inputs at a valid logic state. Bus-hold circuitry is not
provided on 1A or 2A inputs, any B-port input, or any control input. Use of pullup or pulldown resistors with the
bus-hold circuitry is not recommended.
This device is fully specified for live-insertion applications using I , power-up 3-state, and BIAS V . The I
off
off
CC
circuitry prevents damaging current to backflow through the device when it is powered off/on. The power-up
3-state circuitry places the outputs in the high-impedance state during power up and power down, which
prevents driver conflict. The BIAS V
circuitry precharges and preconditions the B-port input/output
CC
connections, preventing disturbance of active data on the backplane during card insertion or removal, and
permits true live-insertion capability.
When V
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.5 V, output-enable (OE and OEBY) inputs should be tied
to V through a pullup resistor and output-enable (OEAB) inputs should be tied to GND through a pulldown
CC
resistor; the minimum value of the resistor is determined by the drive capability of the device connected to this
input.
†
VME320 is a patented backplane construction by Arizona Digital, Inc.
GQL PACKAGE
(TOP VIEW)
terminal assignments
1
2
3
4
5
6
1
1OEBY
1Y
2
NC
3
4
5
6
1OEAB
1B
A
B
C
D
E
F
A
B
C
D
E
F
NC
NC
NC
1A
GND
GND
V
CC
2Y
2A
V
V
BIAS V
CC
2B
CC
CC
3A1
3A2
3A3
3A4
3A5
3A7
DIR
2OEBY
LE
GND
GND
2OEAB
3B1
3B2
3B3
3B4
3B5
3B7
V
V
CC
OE
CC
G
H
J
CLKBA
3A6
3A8
NC
GND
GND
CLKAB
3B6
G
H
J
V
V
CC
CC
GND
NC
GND
NC
3B8
K
NC
V
CC
K
NC − No internal connection
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCES357E − JULY 2001 − REVISED MARCH 2004
functional description
The SN74VMEH22501 is a high-drive (–48/64 mA), 8-bit UBT transceiver containing D-type latches and D-type
flip-flops for data-path operation in transparent, latched, or flip-flop modes. Data transmission is true logic. The
device is uniquely partitioned as 8-bit UBT transceivers with two integrated 1-bit three-wire bus transceivers.
functional description for two 1-bit bus transceivers
The OEAB inputs control the activity of the 1B or 2B port. When OEAB is high, the B-port outputs are active.
When OEAB is low, the B-port outputs are disabled.
Separate 1A and 2A inputs and 1Y and 2Y outputs provide a feedback path for control and diagnostics
monitoring. The OEBY inputs control the 1Y or 2Y outputs. When OEBY is low, the Y outputs are active. When
OEBY is high, the Y outputs are disabled.
The OEBY and OEAB inputs can be tied together to form a simple direction control where an input high yields
A data to B bus and an input low yields B data to Y bus.
1-BIT BUS TRANSCEIVER FUNCTION TABLE
INPUTS
OUTPUT
MODE
OEAB OEBY
L
H
L
H
H
L
Z
Isolation
A data to B bus
True driver
B data to Y bus
H
L
A data to B bus, B data to Y bus
True driver with feedback path
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅ ꢆꢇ ꢈꢈꢉ ꢊ ꢋ
ꢌꢍ ꢎꢏ ꢐ ꢑ ꢁꢏ ꢄ ꢆꢒ ꢀꢓ ꢔ ꢎꢑ ꢀ ꢐꢒ ꢓꢁ ꢀꢕ ꢆꢏ ꢄ ꢆ ꢒ ꢓꢁꢖ ꢐ ꢗ ꢘ ꢋ ꢍꢎꢏ ꢐ ꢎꢑꢀ ꢐ ꢒꢓꢁꢀ ꢕꢆꢏ ꢄꢆꢒꢀ
ꢗꢏ ꢐ ꢇ ꢀꢙ ꢔ ꢏ ꢐ ꢔꢄꢐ ꢐꢔ ꢙ ꢘꢒ ꢐꢚ ꢛꢆ ꢆ ꢖꢎ ꢓꢕꢜ ꢙꢓꢐ ꢇꢚ ꢓꢁꢖ ꢝ ꢍꢀꢐꢓꢐ ꢆ ꢘ ꢑꢐ ꢙꢑꢐ ꢀ
SCES357E − JULY 2001 − REVISED MARCH 2004
functional description for 8-bit UBT transceiver
The 3A and 3B data flow in each direction is controlled by the OE and direction-control (DIR) inputs. When OE
is low, all 3A- or 3B-port outputs are active. When OE is high, all 3A- or 3B-port outputs are in the high-impedance
state.
FUNCTION TABLE
INPUTS
OUTPUT
OE
H
DIR
X
Z
L
H
3A data to 3B bus
3B data to 3A bus
L
L
The UBT transceiver functions are controlled by latch-enable (LE) and clock (CLKAB and CLKBA) inputs. For
3A-to-3B data flow, the UBT operates in the transparent mode when LE is high. When LE is low, the 3A data
is latched if CLKAB is held at a high or low logic level. If LE is low, the 3A data is stored in the latch/flip-flop on
the low-to-high transition of CLKAB.
The UBT transceiver data flow for 3B to 3A is similar to that of 3A to 3B, but uses CLKBA.
†
UBT TRANSCEIVER FUNCTION TABLE
INPUTS
OUTPUT
3B
MODE
OE
H
L
LE
X
L
CLKAB
3A
X
X
X
L
X
H
L
Z
Isolation
‡
B
0
§
B
0
Latched storage of 3A data
True transparent
L
L
L
H
H
L
X
X
↑
↑
L
L
H
L
H
L
L
Clocked storage of 3A data
L
L
H
H
†
‡
3A-to-3B data flow is shown; 3B-to-3A data flow is similar, but uses CLKBA.
Output level before the indicated steady-state input conditions were established,
provided that CLKAB was high before LE went low
§
Output level before the indicated steady-state input conditions were established
The UBT transceiver can replace any of the functions shown in Table 1.
Table 1. SN74VMEH22501 UBT Transceiver Replacement Functions
FUNCTION
8 BIT
’245, ’623, ’645
’241, ’244, ’541
’543
Transceiver
Buffer/driver
Latched transceiver
Latch
’373, ’573
’646, ’652
’374, ’574
Registered transceiver
Flip-flop
SN74VMEH22501 UBT transceiver replaces all above functions
4
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SCES357E − JULY 2001 − REVISED MARCH 2004
logic diagram (positive logic)
48
1OEAB
1
1OEBY
2
46
1A
1B
3
1Y
41
2OEAB
8
2OEBY
5
43
2A
2B
6
2Y
14
OE
24
DIR
32
CLKAB
11
LE
17
CLKBA
9
40
3A1
1D
C1
3B1
CLK
1D
C1
CLK
To Seven Other Channels
Pin numbers shown are for the DGG and DGV packages.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅ ꢆꢇ ꢈꢈꢉ ꢊ ꢋ
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ꢗꢏ ꢐ ꢇ ꢀꢙ ꢔ ꢏ ꢐ ꢔꢄꢐ ꢐꢔ ꢙ ꢘꢒ ꢐꢚ ꢛꢆ ꢆ ꢖꢎ ꢓꢕꢜ ꢙꢓꢐ ꢇꢚ ꢓꢁꢖ ꢝ ꢍꢀꢐꢓꢐ ꢆ ꢘ ꢑꢐ ꢙꢑꢐ ꢀ
SCES357E − JULY 2001 − REVISED MARCH 2004
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
and BIAS V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
CC
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
Voltage range applied to any output in the high or low state, V
O
(see Note 1): 3A port or Y output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
CC
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Output current in the low state, I : 3A port or Y output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
O
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Output current in the high state, I : 3A port or Y output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
O
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −100 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
OK
I
Output clamp current, I
(V < 0 or V > V ): B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
O O CC
Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Notes 3 and 4)
MIN
TYP
MAX
UNIT
V
,
CC
BIAS V
Supply voltage
3.15
3.3
3.45
V
CC
Control inputs or A port
B port
V
5.5
5.5
CC
V
V
V
Input voltage
V
V
I
V
CC
Control inputs or A port
B port
2
High-level input voltage
IH
IL
0.5 V
CC
+ 50 mV
Control inputs or A port
B port
0.8
Low-level input voltage
Input clamp current
V
0.5 V
CC
− 50 mV
I
IK
−18
−12
−48
12
mA
3A port and Y output
B port
I
High-level output current
Low-level output current
mA
mA
OH
OL
3A port and Y output
B port
I
64
∆t/∆v
∆t/∆V
Input transition rise or fall rate
Power-up ramp rate
Outputs enabled
10
ns/V
µs/V
°C
20
0
CC
T
A
Operating free-air temperature
85
NOTES: 3. All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application
CC
report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS V
= 3.3 V first, I/O second, and
CC
V
CC
= 3.3 V last, because the BIAS V
precharge circuitry is disabled when any V pin is connected. The control inputs can be
CC
CC
connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection sequence
is acceptable, but generally, GND is connected first.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢉ
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ꢇ
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ꢏ
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ꢛ
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SCES357E − JULY 2001 − REVISED MARCH 2004
electrical characteristics over recommended operating free-air temperature range for A and B
ports (unless otherwise noted)
†
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
V
IK
V
V
= 3.15 V,
I = −18 mA
−1.2
V
CC
I
3A port, any B ports,
and Y outputs
= 3.15 V to 3.45 V,
I
= −100 µA
V
CC
−0.2
CC
OH
I
I
I
I
= −6 mA
2.4
2
OH
OH
OH
OH
3A port and Y outputs
Any B port
V
= 3.15 V
V
OH
V
CC
= −12 mA
= −24 mA
= −48 mA
2.4
2
V
V
= 3.15 V
CC
3A port, any B ports,
and Y outputs
= 3.15 V to 3.45 V,
I
= 100 µA
0.2
CC
OL
I
I
I
I
I
= 6 mA
0.55
0.8
0.4
0.55
0.6
1
OL
OL
OL
OL
OL
3A port and Y outputs
Any B port
V
V
= 3.15 V
= 3.15 V
CC
= 12 mA
= 24 mA
= 48 mA
= 64 mA
V
V
OL
CC
V
V
= 3.45 V,
V = V
CC
or GND
Control inputs,
1A and 2A
CC
I
I
I
µA
µA
I
= 0 or 3.45 V,
V = 5.5 V
5
CC
I
3A port, any B port,
and Y outputs
‡
V
= 3.45 V,
= 3.45 V,
V
= V
CC
or 5.5 V
5
CC
CC
O
O
OZH
−5
−20
10
3A port and Y outputs
Any B port
‡
V
V
= GND
µA
I
OZL
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 0, BIAS V
= 3.15 V,
= 3.15 V,
= 3.45 V,
= 3.45 V,
= 0,
V or V = 0 to 5.5 V
µA
µA
µA
µA
µA
off
CC
I
O
§
3A port
3A port
3A port
3A port
V = 0.8 V
75
−75
BHL
BHH
I
¶
V = 2 V
I
#
V = 0 to V
500
BHLO
I
CC
||
V = 0 to V
−500
BHHO
I
CC
≤ 1.5 V, V = 0.5 V to V
CC
V = GND or V , OE = don’t care
,
O
10
µA
I
k
OZ(PU/PD)
I
CC
†
‡
§
All typical values are at V
For I/O ports, the parameters I
= 3.3 V, T = 25°C.
A
CC
and I include the input leakage current.
OZH
OZL
The bus-hold circuit can sink at least the minimum low sustaining current at V max. I
IL
should be measured after lowering V to GND, then
IN
BHL
raising it to V max.
IL
¶
The bus-hold circuit can source at least the minimum high sustaining current at V min. I
should be measured after raising V to V , then
BHH IN CC
IH
lowering it to V min.
IH
#
||
k
An external driver must source at least I
to switch this node from low to high.
BHLO
to switch this node from high to low.
An external driver must sink at least I
BHHO
High-impedance state during power up or power down
7
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ꢗꢏ ꢐ ꢇ ꢀꢙ ꢔ ꢏ ꢐ ꢔꢄꢐ ꢐꢔ ꢙ ꢘꢒ ꢐꢚ ꢛꢆ ꢆ ꢖꢎ ꢓꢕꢜ ꢙꢓꢐ ꢇꢚ ꢓꢁꢖ ꢝ ꢍꢀꢐꢓꢐ ꢆ ꢘ ꢑꢐ ꢙꢑꢐ ꢀ
SCES357E − JULY 2001 − REVISED MARCH 2004
electrical characteristics over recommended operating free-air temperature range for A and B
ports (unless otherwise noted) (continued)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
30
UNIT
Outputs high
Outputs low
V
= 3.45 V, I = 0,
CC
V = V
O
30
I
mA
CC
or GND
I
CC
Outputs disabled
30
V
= 3.45 V, I = 0,
O
CC
CC
V = V
µA/
Outputs enabled
Outputs disabled
76
19
or GND,
I
clock
MHz/
input
One data input switching at
one-half clock frequency,
50% duty cycle
I
CCD
V
= 3.15 V to 3.45 V, One input at V − 0.6 V,
CC
CC
Other inputs at V
750
µA
∆I
CC
h
or GND
CC
1A and 2A inputs
Control inputs
1Y or 2Y outputs
3A port
2.8
2.6
5.6
7.9
11
C
C
C
V = 3.15 V or 0
pF
pF
pF
i
I
V
O
= 3.15 V or 0
o
V
CC
= 3.3 V,
V
O
= 3.3 V or 0
io
Any B port
12.5
†
h
All typical values are at V
CC
= 3.3 V, T = 25°C.
A
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V
or GND.
CC
live-insertion specifications over recommended operating free-air temperature range for B port
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
5
UNIT
mA
µA
V
V
V
= 0 to 3.15 V,
BIAS V
= 3.15 V to 3.45 V,
I
I
= 0
= 0
CC
CC
CC
CC
CC
CC
O(DC)
I
(BIAS V )
CC
CC
‡
= 3.15 V to 3.45 V , BIAS V
= 3.15 V to 3.45 V,
= 3.15 V to 3.45 V
10
O(DC)
V
O
= 0,
= 0
CC
BIAS V
1.3
−20
20
1.5
1.7
V
V
= 0,
BIAS V
BIAS V
= 3.15 V
= 3.15 V
−100
100
O
O
CC
I
V
CC
µA
O
V
= 3 V,
CC
†
‡
All typical values are at V
− 0.5 V < BIAS V
= 3.3 V, T = 25°C.
A
V
CC
CC
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢉ
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ꢐꢚ
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ꢆ
ꢖ
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ꢓ
ꢐ
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ꢚ
ꢓ
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SCES357E − JULY 2001 − REVISED MARCH 2004
timing requirements over recommended operating conditions for UBT transceiver (unless
otherwise noted) (see Figures 1 and 2)
MIN
MAX
UNIT
f
t
Clock frequency
Pulse duration
120
MHz
clock
LE high
2.5
3
ns
ns
w
CLK high or low
Data high
Data low
CLK high
CLK low
Data high
Data low
CLK high
CLK low
Data high
Data low
2.1
2.2
2
3A before CLK↑
3A before LE↓
3B before CLK↑
3B before LE↓
3A after CLK↑
3A after LE↓
2
t
su
Setup time
2.5
2.7
2
2
0
0
CLK high
CLK low
Data high
Data low
CLK high
CLK low
1
1
0
0
1
1
t
h
Hold time
ns
3B after CLK↑
3B after LE↓
switching characteristics over recommended operating conditions for bus transceiver function
(unless otherwise noted) (see Figures 1 and 2)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
TYP
MAX
UNIT
t
t
t
t
t
t
t
t
5.1
4.5
7.2
6.1
4.6
3.7
3.3
1.8
8.9
7.8
14.5
13
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
1A or 2A
1A or 2A
OEAB
1B or 2B
1Y or 2Y
1B or 2B
1B or 2B
ns
ns
8.1
7.4
9.7
4.8
ns
OEAB
ns
t
4.3
4.3
ns
ns
Transition time, B port (10%−90%)
Transition time, B port (90%−10%)
r
t
t
t
t
t
t
t
f
1.6
1.6
1.2
1.8
1.4
1.7
5.6
5.6
5.6
4.9
5.4
4.5
PLH
PHL
PZH
PZL
PHZ
PLZ
1B of 2B
1Y or 2Y
1Y or 2Y
1Y or 2Y
ns
ns
ns
OEBY
OEBY
9
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SCES357E − JULY 2001 − REVISED MARCH 2004
switching characteristics over recommended operating conditions for UBT transceiver (unless
otherwise noted) (see Figures 1 and 2)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
TYP
MAX
UNIT
f
t
t
t
t
t
t
t
t
t
t
120
5.5
4.7
6
MHz
max
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
9.3
8.3
3A
LE
3B
3B
3B
3B
3B
ns
ns
ns
ns
ns
10.6
8.7
4.9
5.8
4.6
4.6
3.5
4.8
2.4
10.1
8.4
CLKAB
OE
9.3
8.5
9.3
OE
5.7
t
r
t
f
4.3
4.3
ns
ns
Transition time, B port (10%−90%)
Transition time, B port (90%−10%)
t
t
t
t
t
t
t
t
t
t
1.7
1.7
1.7
1.7
1.4
1.4
1.5
2.1
1.8
2.3
5.9
5.9
5.9
5.9
5.5
5.5
6.2
5.5
6.2
5.6
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
3B
3A
3A
3A
3A
3A
ns
ns
ns
ns
ns
LE
CLKBA
OE
OE
skew characteristics for bus transceiver for specific worst-case V
and temperature within the
CC
recommended ranges of supply voltage and operating free-air temperature (see Figures 1 and 2)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
0.8
0.7
0.7
0.6
t
t
t
t
sk(LH)
sk(HL)
sk(LH)
sk(HL)
1A or 2A
1B or 2B
1B or 2B
1Y or 2Y
ns
ns
1A or 2A
1B or 2B
1A or 2A
1B or 2B
1B or 2B
1Y or 2Y
1B or 2B
1Y or 2Y
1.7
1.2
2.8
1.4
†
ns
ns
t
sk(t)
t
sk(pp)
†
t
− Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of the same
sk(t)
packaged device. The specifications are given for specific worst-case V
and temperature and apply to any outputs switching in opposite
CC
directions, both low to high (LH) and high to low (HL) [t
].
sk(t)
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢉ
ꢊ
ꢋ
ꢀ
ꢀ
ꢗ
ꢏ
ꢐ
ꢇ
ꢀ
ꢙꢔ
ꢏ
ꢐ
ꢔꢄ
ꢐ
ꢐ
ꢔ
ꢙ
ꢘ
ꢒ
ꢐꢚ
ꢛ
ꢆ
ꢆ
ꢖ
ꢎ
ꢓ
ꢕ
ꢜ
ꢙ
ꢓ
ꢐ
ꢇ
ꢚ
ꢓ
ꢁ
ꢖ
ꢝ
ꢍ
ꢀ
ꢐ
ꢓ
ꢐ
ꢆ
ꢘ
ꢑ
ꢐ
ꢙ
ꢑ
ꢐ
SCES357E − JULY 2001 − REVISED MARCH 2004
skew characteristics for UBT for specific worst-case V
and temperature within the
CC
recommended ranges of supply voltage and operating free-air temperature (see Figures 1 and 2)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
1.3
1.1
0.8
0.8
0.7
0.6
0.7
0.6
t
t
t
t
t
t
t
t
sk(LH)
sk(HL)
sk(LH)
sk(HL)
sk(LH)
sk(HL)
sk(LH)
sk(HL)
3A
3B
3B
3A
3A
ns
CLKAB
3B
ns
ns
ns
CLKBA
3A
CLKAB
3B
3B
3B
3A
3A
3B
3B
3A
3A
1.9
2.1
1.2
1
†
ns
ns
t
sk(t)
CLKBA
3A
2.8
2.7
1.3
1.2
CLKAB
3B
t
sk(pp)
CLKBA
†
t
− Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of the same
sk(t)
packaged device. The specifications are given for specific worst-case V
and temperature and apply to any outputs switching in opposite
CC
directions, both low to high (LH) and high to low (HL) [t
].
sk(t)
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢗꢏ ꢐ ꢇ ꢀꢙ ꢔ ꢏ ꢐ ꢔꢄꢐ ꢐꢔ ꢙ ꢘꢒ ꢐꢚ ꢛꢆ ꢆ ꢖꢎ ꢓꢕꢜ ꢙꢓꢐ ꢇꢚ ꢓꢁꢖ ꢝ ꢍꢀꢐꢓꢐ ꢆ ꢘ ꢑꢐ ꢙꢑꢐ ꢀ
SCES357E − JULY 2001 − REVISED MARCH 2004
PARAMETER MEASUREMENT INFORMATION
A PORT
6 V
S1
Open
GND
500 Ω
From Output
Under Test
TEST
S1
t
t
/t
Open
6 V
PLH PHL
/t
C
= 50 pF
t
L
PLZ PZL
/t
500 Ω
(see Note A)
GND
Open
PHZ PZH
B-to-A Skew
LOAD CIRCUIT
t
w
3 V
0 V
3 V
0 V
1.5 V
Input
1.5 V
Timing
Input
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
h
su
3 V
0 V
Data
Input
3 V
0 V
V
/2
V
CC
/2
CC
1.5 V
1.5 V
Output Control
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
S1 at 6 V
3 V
V
3 V
0 V
1.5 V
Input
V
V
+ 0.3 V
V
CC
/2
V
CC
/2
OL
(see Note B)
OL
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
− 0.3 V
OH
1.5 V
Output
1.5 V
1.5 V
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, Z = 50 Ω, t ≈ 2 ns, t ≈ 2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢈ
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ꢉ
ꢊ
ꢋ
ꢀ
ꢀ
ꢗ
ꢏ
ꢐ
ꢇ
ꢀ
ꢙꢔ
ꢏ
ꢐ
ꢔꢄ
ꢐ
ꢐ
ꢔ
ꢙ
ꢘ
ꢒ
ꢐꢚ
ꢛ
ꢆ
ꢆ
ꢖ
ꢎ
ꢓ
ꢕ
ꢜ
ꢙ
ꢓ
ꢐ
ꢇ
ꢚ
ꢓ
ꢁ
ꢖ
ꢝ
ꢍ
ꢀ
ꢐ
ꢓ
ꢐ
ꢆ
ꢘ
ꢑ
ꢐ
ꢙ
ꢑ
ꢐ
SCES357E − JULY 2001 − REVISED MARCH 2004
PARAMETER MEASUREMENT INFORMATION
B PORT
6 V
S1
Open
GND
500 Ω
From Output
Under Test
TEST
S1
t
t
/t
Open
6 V
PLH PHL
/t
C
= 50 pF
t
L
PLZ PZL
/t
500 Ω
(see Note A)
GND
Open
PHZ PZH
A-to-B Skew
LOAD CIRCUIT
t
w
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
Timing
Input
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
h
su
3 V
0 V
Data
Input
3 V
0 V
1.5 V
1.5 V
1.5 V
1.5 V
Output Control
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
S1 at 6 V
3 V
V
3 V
0 V
V
/2
CC
Input
1.5 V
1.5 V
V
V
+ 0.3 V
OL
(see Note B)
OL
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
− 0.3 V
OH
V
/2
CC
Output
V
/2
V
/2
CC
CC
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, Z = 50 Ω, t ≈ 2 ns, t ≈ 2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
13
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ꢗꢏ ꢐ ꢇ ꢀꢙ ꢔ ꢏ ꢐ ꢔꢄꢐ ꢐꢔ ꢙ ꢘꢒ ꢐꢚ ꢛꢆ ꢆ ꢖꢎ ꢓꢕꢜ ꢙꢓꢐ ꢇꢚ ꢓꢁꢖ ꢝ ꢍꢀꢐꢓꢐ ꢆ ꢘ ꢑꢐ ꢙꢑꢐ ꢀ
SCES357E − JULY 2001 − REVISED MARCH 2004
DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS
The preceding switching characteristics tables show the switching characteristics of the device into the lumped load
shown in the parameter measurement information (PMI) (see Figures 1 and 2). All logic devices currently are tested
into this type of load. However, the designer’s backplane application probably is a distributed load. For this reason,
this device has been designed for optimum performance in the VME64x backplane as shown in Figure 3.
5 V
5 V
330 Ω
0.42”
330 Ω
0.42”
0.42”
0.84”
0.84”
0.42”
†
Z
O
470 Ω
470 Ω
Conn.
Conn.
Conn.
Conn.
Conn.
Conn.
‡
Z
O
1.5”
1.5”
1.5”
1.5”
1.5”
1.5”
Rcvr
Rcvr
Rcvr
Rcvr
Rcvr
Drvr
Slot 1
Slot 2
Slot 3
Slot 19
Slot 20
Slot 21
†
‡
Unloaded backplane trace natural impedence (Z ) is 45 Ω. 45 Ω to 60 Ω is allowed, with 50 Ω being ideal.
O
Card stub natural impedence (Z ) is 60 Ω.
O
Figure 3. VME64x Backplane
The following switching characteristics tables derived from TI-SPICE models show the switching characteristics of
the device into the backplane under full and minimum loading conditions, to help the designer better understand the
performance of the VME device in this typical backplane. See www.ti.com/sc/etl for more information.
driver in slot 11, with receiver cards in all other slots (full load)
switching characteristics over recommended operating conditions for bus transceiver function
(unless otherwise noted) (see Figure 3)
FROM
(INPUT)
TO
(OUTPUT)
§
PARAMETER
MIN TYP
MAX
UNIT
t
t
t
5.9
5.5
8.5
8.7
PLH
1A or 2A
1B or 2B
ns
PHL
¶
r
9
8.6
9
11.4
ns
ns
Transition time, B port (10%−90%)
Transition time, B port (90%−10%)
= 3.3 V, T = 25°C. All values are derived from TI-SPICE models.
¶
t
f
8.9
10.8
§
¶
All typical values are at V
CC
All t and t times are taken at the first receiver.
A
r
f
14
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ꢉ
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ꢀ
ꢗ
ꢏ
ꢐ
ꢇ
ꢀ
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ꢏ
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ꢔ
ꢄ
ꢐ
ꢐ
ꢔ
ꢙ
ꢘ
ꢒ
ꢐꢚ
ꢛ
ꢆ
ꢆ
ꢖ
ꢎ
ꢓ
ꢕ
ꢜ
ꢙ
ꢓ
ꢐ
ꢇ
ꢚ
ꢓ
ꢁ
ꢖ
ꢝ
ꢍ
ꢀ
ꢐ
ꢓ
ꢐ
ꢆ
ꢘ
ꢑ
ꢐ
ꢙ
ꢑ
ꢐ
SCES357E − JULY 2001 − REVISED MARCH 2004
driver in slot 11, with receiver cards in all other slots (full load) (continued)
switching characteristics over recommended operating conditions for UBT (unless otherwise
noted) (see Figure 3)
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
MIN TYP
MAX
UNIT
t
t
t
t
t
t
t
6.2
5.6
6.1
5.6
6.2
5.7
8.9
9
PLH
PHL
PLH
PHL
PLH
PHL
3A
LE
3B
3B
3B
ns
9.1
9
ns
9.1
9
CLKAB
ns
‡
9
8.6
9
11.4
ns
ns
Transition time, B port (10%−90%)
Transition time, B port (90%−10%)
= 3.3 V, T = 25°C. All values are derived from TI-SPICE models.
r
‡
t
f
8.9
10.8
†
‡
All typical values are at V
CC
All t and t times are taken at the first receiver.
A
r
f
skew characteristics for bus transceiver for specific worst-case V
and temperature within the
CC
recommended ranges of supply voltage and operating free-air temperature (see Figure 3)
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
MIN TYP
MAX
UNIT
2.5
3
t
t
t
t
sk(LH)
1A or 2A
1B or 2B
ns
sk(HL)
§
1A or 2A
1A or 2A
1B or 2B
1B or 2B
1
ns
ns
sk(t)
0.5
3.4
sk(pp)
†
§
All typical values are at V
CC
sk(t)
packaged device. The specifications are given for specific worst-case V
= 3.3 V, T = 25°C. All values are derived from TI-SPICE models.
A
t
− Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of the same
and temperature and apply to any outputs switching in opposite
CC
directions, both low to high (LH) and high to low (HL) [t
].
sk(t)
skew characteristics for UBT for specific worst-case V
and temperature within the
CC
recommended ranges of supply voltage and operating free-air temperature (see Figure 3)
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
MIN TYP
MAX
UNIT
2.4
3.4
2.7
3.4
t
t
t
t
sk(LH)
sk(HL)
sk(LH)
sk(HL)
3A
3B
3B
ns
CLKAB
ns
3A
3B
3B
3B
3B
1
1
§
ns
ns
t
sk(t)
CLKAB
3A
0.5
0.6
3.4
3.5
t
sk(pp)
CLKAB
†
§
All typical values are at V
= 3.3 V, T = 25°C. All values are derived from TI-SPICE models.
A
CC
− Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of the same
t
sk(t)
packaged device. The specifications are given for specific worst-case V
and temperature and apply to any outputs switching in opposite
CC
directions, both low to high (LH) and high to low (HL) [t
].
sk(t)
15
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ꢗꢏ ꢐ ꢇ ꢀꢙ ꢔ ꢏ ꢐ ꢔꢄꢐ ꢐꢔ ꢙ ꢘꢒ ꢐꢚ ꢛꢆ ꢆ ꢖꢎ ꢓꢕꢜ ꢙꢓꢐ ꢇꢚ ꢓꢁꢖ ꢝ ꢍꢀꢐꢓꢐ ꢆ ꢘ ꢑꢐ ꢙꢑꢐ ꢀ
SCES357E − JULY 2001 − REVISED MARCH 2004
driver in slot 1, with one receiver in slot 21 (minimum load)
switching characteristics over recommended operating conditions for bus transceiver function
(unless otherwise noted) (see Figure 3)
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
MIN TYP
MAX
UNIT
t
t
t
5.5
5.3
7.4
7.4
4.4
PLH
1A or 2A
1B or 2B
ns
PHL
‡
r
3.9
3.7
3.4
3.4
ns
ns
Transition time, B port (10%−90%)
Transition time, B port (90%−10%)
= 3.3 V, T = 25°C. All values are derived from TI-SPICE models.
‡
t
f
4.8
†
‡
All typical values are at V
CC
All t and t times are taken at the first receiver.
A
r
f
switching characteristics over recommended operating conditions for UBT (unless otherwise
noted) (see Figure 3)
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
MIN TYP
MAX
UNIT
t
t
t
t
t
t
t
5.8
5.5
5.9
5.5
5.9
5.5
7.9
7.7
8
PLH
PHL
PLH
PHL
PLH
PHL
3A
LE
3B
3B
3B
ns
ns
7.8
8.1
7.7
4.4
CLKAB
ns
‡
3.9
3.7
3.4
3.4
ns
ns
Transition time, B port (10%−90%)
Transition time, B port (90%−10%)
= 3.3 V, T = 25°C. All values are derived from TI-SPICE models.
r
‡
t
f
4.8
†
‡
All typical values are at V
CC
All t and t times are taken at the first receiver.
A
r
f
skew characteristics for bus transceiver for specific worst-case V
and temperature within the
CC
recommended ranges of supply voltage and operating free-air temperature (see Figure 3)
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
MIN TYP
MAX
UNIT
1.7
2.1
1
t
t
t
t
sk(LH)
1A or 2A
1B or 2B
ns
sk(HL)
§
1A or 2A
1A or 2A
1B or 2B
1B or 2B
ns
ns
sk(t)
0.2
2.1
sk(pp)
†
§
All typical values are at V
CC
sk(t)
packaged device. The specifications are given for specific worst-case V
= 3.3 V, T = 25°C. All values are derived from TI-SPICE models.
A
t
− Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of the same
and temperature and apply to any outputs switching in opposite
CC
directions, both low to high (LH) and high to low (HL) [t
].
sk(t)
16
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ꢉ
ꢊ
ꢋ
ꢀ
ꢀ
ꢗ
ꢏ
ꢐ
ꢇ
ꢀ
ꢙ
ꢔ
ꢏ
ꢐ
ꢔꢄ
ꢐ
ꢐ
ꢔ
ꢙ
ꢘ
ꢒ
ꢐꢚ
ꢛ
ꢆ
ꢆ
ꢖ
ꢎ
ꢓ
ꢕ
ꢜ
ꢙ
ꢓ
ꢐ
ꢇ
ꢚ
ꢓ
ꢁ
ꢖ
ꢝ
ꢍ
ꢀ
ꢐ
ꢓ
ꢐ
ꢆ
ꢘ
ꢑ
ꢐ
ꢙ
ꢑ
ꢐ
SCES357E − JULY 2001 − REVISED MARCH 2004
driver in slot 1, with one receiver in slot 21 (minimum load) (continued)
skew characteristics for UBT for specific worst-case V and temperature within the
CC
recommended ranges of supply voltage and operating free-air temperature (see Figure 3)
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
MIN TYP
MAX
UNIT
2
2.3
2.1
2.4
t
t
t
t
sk(LH)
sk(HL)
sk(LH)
sk(HL)
3A
3B
3B
ns
CLKAB
ns
3A
3B
3B
3B
3B
1
1
‡
ns
ns
t
sk(t)
CLKAB
3A
0.2
0.2
2.5
2.9
t
sk(pp)
CLKAB
†
‡
All typical values are at V
= 3.3 V, T = 25°C. All values are derived from TI-SPICE models.
A
CC
− Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of the same
t
sk(t)
packaged device. The specifications are given for specific worst-case V
and temperature and apply to any outputs switching in opposite
CC
directions, both low to high (LH) and high to low (HL) [t
].
sk(t)
By simulating the performance of the device using the VME64x backplane (see Figure 3), the maximum peak current
in or out of the B-port output, as the devices switch from one logic state to another, was found to be equivalent to
driving the lumped load shown in Figure 4.
5 V
165 Ω
From Output
Under Test
235 Ω
390 pF
LOAD CIRCUIT
Figure 4. Equivalent AC Peak Output-Current Lumped Load
17
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ꢗꢏ ꢐ ꢇ ꢀꢙ ꢔ ꢏ ꢐ ꢔꢄꢐ ꢐꢔ ꢙ ꢘꢒ ꢐꢚ ꢛꢆ ꢆ ꢖꢎ ꢓꢕꢜ ꢙꢓꢐ ꢇꢚ ꢓꢁꢖ ꢝ ꢍꢀꢐꢓꢐ ꢆ ꢘ ꢑꢐ ꢙꢑꢐ ꢀ
SCES357E − JULY 2001 − REVISED MARCH 2004
driver in slot 1, with one receiver in slot 21 (minimum load) (continued)
In general, the rise- and fall-time distribution is shown in Figure 5. Since VME devices were designed for use into
distributed loads like the VME64x backplane (B/P), there are significant differences between low-to-high (LH) and
high-to-low (HL) values in the lumped load shown in the PMI (see Figures 1 and 2).
6.4
6.2
6.0
5.8
LH
5.6
5.4
5.2
5.0
HL
Full B/P Load
Minimum B/P Load
PMI Lumped Load
Figure 5
Characterization-laboratory data in Figures 6 and 7 show the absolute ac peak output current, with different supply
voltages, as the devices change output logic state. A typical nominal process is shown to demonstrate the devices’
peak ac output drive capability.
162
137
136
135
134
133
132
131
130
129
128
160
158
156
154
152
150
148
146
144
3.15
3.30
− V
3.45
3.15
3.30
− V
3.45
V
V
CC
CC
Figure 6
Figure 7
18
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ꢉ
ꢊ
ꢋ
ꢀ
ꢀ
ꢗ
ꢏ
ꢐ
ꢇ
ꢀ
ꢙꢔ
ꢏ
ꢐ
ꢔꢄ
ꢐ
ꢐ
ꢔ
ꢙ
ꢘ
ꢒ
ꢐꢚ
ꢛ
ꢆ
ꢆ
ꢖ
ꢎ
ꢓ
ꢕ
ꢜ
ꢙ
ꢓ
ꢐ
ꢇ
ꢚ
ꢓ
ꢁ
ꢖ
ꢝ
ꢍ
ꢀ
ꢐ
ꢓ
ꢐ
ꢆ
ꢘ
ꢑ
ꢐ
ꢙ
ꢑ
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SCES357E − JULY 2001 − REVISED MARCH 2004
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
FREQUENCY
A TO B
FREQUENCY
B TO A
35
30
25
20
15
10
5
30
25
20
15
10
5
V
CC
= 3.15 V
V
= 3.45 V
CC
V
CC
= 3.3 V
V
CC
= 3.3 V
V
CC
= 3.45 V
V
CC
= 3.15 V
20
40
60
80
100
120
20
40
60
80
100
120
f − Switching Frequency − MHz
f − Switching Frequency − MHz
Figure 8
Figure 9
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅ ꢆꢇ ꢈꢈꢉ ꢊ ꢋ
ꢌꢍ ꢎꢏ ꢐ ꢑ ꢁꢏ ꢄ ꢆꢒ ꢀꢓ ꢔ ꢎꢑ ꢀ ꢐꢒ ꢓꢁ ꢀꢕ ꢆꢏ ꢄ ꢆ ꢒ ꢓꢁꢖ ꢐ ꢗ ꢘ ꢋ ꢍꢎꢏ ꢐ ꢎꢑꢀ ꢐ ꢒꢓꢁꢀ ꢕꢆꢏ ꢄꢆꢒꢀ
ꢗ
ꢏ
ꢐ
ꢇ
ꢀ
ꢙ
ꢔ
ꢏ
ꢐ
ꢔ
ꢄ
ꢐ
ꢐ
ꢔ
ꢙ
ꢘ
ꢒ
ꢐꢚ
ꢛ
ꢆ
ꢆ
ꢖ
ꢎ
ꢓ
ꢕ
ꢜ
ꢙ
ꢓ
ꢐ
ꢇ
ꢚ
ꢓ
ꢁ
ꢖ
ꢝ
ꢍ
ꢀ
ꢐ
ꢓ
ꢐ
ꢆ
ꢘ
ꢑ
ꢐ
ꢙ
ꢑ
ꢐ
ꢀ
SCES357E − JULY 2001 − REVISED MARCH 2004
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
300
250
200
150
100
50
V
= 3.15 V
CC
V
CC
= 3.3 V
V
= 3.45 V
CC
0
0
10
20
30
40
50
60
70
80
90
100
I
− High-Level Output Current − mA
OH
Figure 10. V vs I
OL
OL
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
V
CC
= 3.45 V
V
CC
= 3.3 V
V
CC
= 3.15 V
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
I
− Low-Level Output Current − mA
OL
Figure 11. V
vs I
OH
OH
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢈ
ꢌ ꢍꢎꢏ ꢐ ꢑꢁ ꢏ ꢄꢆ ꢒꢀ ꢓꢔ ꢎꢑꢀ ꢐ ꢒꢓꢁꢀ ꢕꢆꢏ ꢄꢆꢒ ꢓꢁꢖ ꢐ ꢗ ꢘ ꢋ ꢍꢎꢏ ꢐ ꢎꢑꢀ ꢐ ꢒꢓꢁꢀ ꢕꢆ ꢏ ꢄꢆ ꢒ
ꢉ
ꢊ
ꢋ
ꢀ
ꢀ
ꢗ
ꢏ
ꢐ
ꢇ
ꢀ
ꢙꢔ
ꢏ
ꢐ
ꢔꢄ
ꢐ
ꢐ
ꢔ
ꢙ
ꢘ
ꢒ
ꢐꢚ
ꢛ
ꢆ
ꢆ
ꢖ
ꢎ
ꢓ
ꢕ
ꢜ
ꢙ
ꢓ
ꢐ
ꢇ
ꢚ
ꢓ
ꢁ
ꢖ
ꢝ
ꢍ
ꢀ
ꢐ
ꢓ
ꢐ
ꢆ
ꢘ
ꢑ
ꢐ
ꢙ
ꢑ
ꢐ
SCES357E − JULY 2001 − REVISED MARCH 2004
VMEbus SUMMARY
In 1981, the VMEbus was introduced as a backplane bus architecture for industrial and commercial applications. The
data-transfer protocols used to define the VMEbus came from the Motorola VERSA bus architecture that owed its
heritage to the then recently introduced Motorola 68000 microprocessor. The VMEbus, when introduced, defined two
basic data-transfer operations: single-cycle transfers consisting of an address and a data transfer, and a block
transfer (BLT) consisting of an address and a sequence of data transfers. These transfers were asynchronous, using
a master-slave handshake. The master puts address and data on the bus and waits for an acknowledgment. The
selected slave either reads or writes data to or from the bus, then provides a data-acknowledge (DTACK*) signal. The
VMEbus system data throughput was 40 Mbyte/s. Previous to the VMEbus, it was not uncommon for the backplane
buses to require elaborate calculations to determine loading and drive current for interface design. This approach
made designs difficult and caused compatibility problems among manufacturers. To make interface design easier
and to ensure compatibility, the developers of the VMEbus architecture defined specific delays based on a 21-slot
terminated backplane and mandated the use of certain high-current TTL drivers, receivers, and transceivers.
In 1989, multiplexing block transfer (MBLT) effectively increased the number of bits from 32 to 64, thereby doubling
the transfer rate. In 1995, the number of handshake edges was reduced from four to two in the double-edge transfer
(2eVME) protocol, doubling the data rate again. In 1997, the VMEbus International Trade Association (VITA)
established a task group to specify a synchronous protocol to increase data-transfer rates to 320 Mbyte/s, or more.
The unreleased specification, VITA 1.5 [double-edge source synchronous transfer (2eSST)], is based on the
asynchronous 2eVME protocol. It does not wait for acknowledgement of the data by the receiver and requires
incident-wave switching. Sustained data rates of 1 Gbyte/s, more than ten times faster than traditional VME64
backplanes, are possible by taking advantage of 2eSST and the 21-slot VME320 star-configuration backplane. The
VME320 backplane approximates a lumped load, allowing substantially higher-frequency operation over the VME64x
distributed-load backplane. Traditional VME64 backplanes with no changes theoretically can sustain 320 Mbyte/s.
From BLT to 2eSST − A Look at the Evolution of VMEbus Protocols by John Rynearson, Technical Director, VITA,
provides additional information on VMEbus and can be obtained at www.vita.com.
maximum data transfer rates
FREQUENCY (MHz)
DATA BITS
PER CYCLE PER CLOCK CYCLE
DATA TRANSFERS
PER SYSTEM
(Mbyte/s)
DATE
TOPOLOGY
PROTOCOL
BACKPLANE
CLOCK
10
1981
1989
1995
1997
1999
BLT
32
64
64
64
64
1
40
80
10
10
10
VMEbus IEEE-1014
VME64
MBLT
1
10
2eVME
2eSST
2eSST
2
160
20
VME64x
2-No Ack
2-No Ack
160−320
320−1000
10−20
20−40
VME64x
20−62.5
40−125
VME320
applicability
Target applications for VME backplanes include industrial controls, telecommunications, simulation,
high-energy physics, office automation, and instrumentation systems.
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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