SN74V3670-10PEU [TI]
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES; 3.3 V的CMOS先入先出MEMORIES
| 型号： | SN74V3670-10PEU |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES |
| 文件： | 总50页 (文件大小：725K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
Choice of Memory Organizations
Empty, Full, and Half-Full Flags Signal FIFO
Status
– SN74V3640 – 1024 × 36 Bit
– SN74V3650 – 2048 × 36 Bit
– SN74V3660 – 4096 × 36 Bit
– SN74V3670 – 8192 × 36 Bit
– SN74V3680 – 16384 × 36 Bit
– SN74V3690 – 32768 × 36 Bit
Programmable Almost-Empty and
Almost-Full Flags; Each Flag Can Default to
One of Eight Preselected Offsets
Selectable Synchronous/Asynchronous
Timing Modes for Almost-Empty and
Almost-Full Flags
166-MHz Operation (6-ns Read/Write Cycle
Time)
Program Programmable Flags by Either
Serial or Parallel Means
User-Selectable Input- and Output-Port Bus
Sizing
– ×36 in to ×36 out
– ×36 in to ×18 out
– ×36 in to ×9 out
Select Standard Timing (Using EF and FF
Flags) or First-Word Fall-Through (FWFT)
Timing (Using OR and IR Flags)
Output Enable Puts Data Outputs in
High-Impedance State
– ×18 in to ×36 out
– ×9 in to ×36 out
Easily Expandable in Depth and Width
Big-Endian/Little-Endian User-Selectable
Byte Representation
Independent Read and Write Clocks Permit
Reading and Writing Simultaneously
5-V-Tolerant Inputs
High-Performance Submicron CMOS
Technology
Fixed, Low, First-Word Latency
Zero-Latency Retransmit
Master Reset Clears Entire FIFO
Available in 128-Pin Thin Quad Flat Pack
(TQFP)
Partial Reset Clears Data, But Retains
Programmable Settings
description
The SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, and SN74V3690 are exceptionally
deep, high-speed CMOS, first-in first-out (FIFO) memories, with clocked read and write controls and a flexible
bus-matching ×36/×18/×9 data flow. These FIFOs offer several key user benefits:
Flexible ×36/×18/×9 bus matching on both read and write ports
The period required by the retransmit operation is fixed and short.
The first-word data-latency period, from the time the first word is written to an empty FIFO to the time it can
be read, is fixed and short.
High-density offerings up to 1 Mbit
Bus-matching synchronous FIFOs are particularly appropriate for network, video, signal processing,
telecommunications, data communications, and other applications that need to buffer large amounts of data
and match buses of unequal sizes.
Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume 36-bit, 18-bit, or
9-bit width, as determined by the state of external control pins’ input width (IW), output width (OW), and bus
matching (BM) during the master-reset cycle.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
PEU PACKAGE
(TOP VIEW)
WEN
SEN
DNC
1
2
3
4
5
6
7
8
102
101
100
99
98
97
OE
V
V
CC
CC
V
CC
Q35
Q34
Q33
Q32
GND
GND
Q31
Q30
Q29
Q28
Q27
Q26
DNC
IW
D35
D34
D33
D32
96
95
9
94
93
92
91
90
89
88
87
86
85
84
83
82
81
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
V
CC
D31
D30
GND
D29
D28
D27
D26
D25
D24
D23
GND
D22
V
CC
Q25
Q24
GND
GND
Q23
Q22
Q21
Q20
Q19
Q18
GND
Q17
Q16
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
V
CC
D21
D20
D19
D18
GND
D17
D16
D15
D14
D13
26
27
28
29
30
31
32
33
34
35
V
V
CC
CC
Q15
Q14
Q13
Q12
GND
Q11
Q10
V
CC
D12
GND
D11
36
37
38
DNC = Do not connect
description (continued)
The input port is controlled by write-clock (WCLK) and write-enable (WEN) inputs. Data is written into the FIFO
on every rising edge of WCLK when WEN is asserted. The output port is controlled by read-clock (RCLK) and
read-enable (REN) inputs. Data is read from the FIFO on every rising edge of RCLK when REN is asserted.
An output-enable (OE) input is provided for 3-state control of the outputs.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
functional block diagram
D0–Dn (×36, ×18, or ×9)
LD SEN
125
2
128
1
Offset
Register
WCLK
WEN
Input
Register
Write-Control
Logic
123
121
108
110
117
124
FF/IR
PAF
EF/OR
PAE
HF
Flag
Logic
Write
Pointer
RAM Array
FWFT/SI
1024 × 36, 2048 × 36,
4096 × 36, 8192 × 36,
16384 × 36, 32768 × 36
109
118
115
PFM
FSEL0
FSEL1
114
113
BE
IP
Control
Logic
Read
Pointer
112
6
BM
IW
Bus
Configuration
103
107
Output
Register
119
Read-Control
Logic
RT
RM
OW
126
127
MRS
PRS
Reset
Logic
102
OE
Q0–Qn (×36, ×18, or ×9)
105
104
REN
RCLK
description (continued)
The frequencies of the RCLK and WCLK signals can vary from 0 to f
are no restrictions on the frequency of one clock input with respect to the other.
, with complete independence. There
MAX
There are two possible timing modes of operation with these devices: first-word fall-through (FWFT) mode and
standard mode.
In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three
transitions of the RCLK signal. REN need not be asserted for accessing the first word. However, subsequent
words written to the FIFO do require a low on REN for access. The state of the FWFT/SI input during master
reset determines the timing mode.
For applications requiring more data-storage capacity than a single FIFO can provide, the FWFT timing mode
permits depth expansion by chaining FIFOs in series (i.e., the data outputs of one FIFO are connected to the
corresponding data inputs of the next). No external logic is required.
In standard mode, the first word written to an empty FIFO does not appear on the data output lines unless a
specific read operation is performed. A read operation, which consists of activating REN and enabling a rising
RCLK edge, shifts the word from internal memory to the data output lines.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
Partial Reset (PRS)
Master Reset (MRS)
Write Clock (WCLK)
Read Clock (RCLK)
Write Enable (WEN)
Load (LD)
Read Enable (REN)
Output Enable (OE)
SN74V3640
SN74V3650
SN74V3660
SN74V3670
SN74V3680
SN74V3690
(×36, ×18, ×9) Data In (D0–Dn)
Serial Enable (SEN)
(×36, ×18, ×9) Data Out (Q0–Qn)
Retransmit (RT)
Empty Flag or Output Ready (EF/OR)
Programmable Almost-Empty Flag (PAE)
Half-Full Flag (HF)
First-Word Fall-Through or Serial Input
(FWFT/SI)
Full Flag or Input Ready (FF/IR)
Big Endian/Little Endian (BE)
Programmable Almost-Full Flag (PAF)
Interspersed/
Noninterspersed Parity (IP)
Output Width (OW)
Input Width (IW)
Bus
Matching
(BM)
Figure 1. Single-Device-Configuration Signal Flow
description (continued)
These FIFOs have five flag pins: empty flag or output ready (EF/OR), full flag or input ready (FF/IR), half-full
flag (HF), programmable almost-empty flag (PAE), and programmable almost-full flag (PAF). The EF and FF
functions are selected in standard mode. The IR and OR functions are selected in FWFT mode. HF, PAE, and
PAF always are available for use, regardless of timing mode.
PAE and PAF can be programmed independently to switch at any point in memory. Programmable offsets
determine the flag-switching threshold and can be loaded by parallel or serial methods. Eight default offset
settings also are provided, so that PAE can be set to switch at a predefined number of locations from the empty
boundary. The PAF threshold also can be set at similar predefined values from the full boundary. The default
offset values are set during master reset by the state of the FSEL0, FSEL1, and LD.
For serial programming, SEN, together with LD, loads the offset registers via the serial input (SI) on each rising
edge of WCLK. For parallel programming, WEN, together with LD, loads the offset registers via Dn on each
rising edge of WCLK. REN, together with LD, can read the offsets in parallel from Qn on each rising edge of
RCLK, regardless of whether serial parallel offset loading has been selected.
During master reset (MRS), the read and write pointers are set to the first location of the FIFO. The FWFT pin
selects standard mode or FWFT mode.
Partial reset (PRS) also sets the read and write pointers to the first location of the memory. However, the timing
mode, programmable-flag programming method, and default or programmed offset settings existing before
partial reset remain unchanged. The flags are updated according to the timing mode and offsets in effect. PRS
is useful for resetting a device in mid-operation, when reprogramming programmable flags would be
undesirable.
Also, the timing modes of PAE and PAF outputs can be selected. Timing modes can be set as either
asynchronous or synchronous for PAE and PAF.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
description (continued)
If the asynchronous PAE/PAF configuration is selected, PAE is asserted low on the low-to-high transition of
RCLK. PAE is reset to high on the low-to-high transition of WCLK. Similarly, PAF is asserted low on the
low-to-high transition of WCLK, and PAF is reset to high on the low-to-high transition of RCLK.
If the synchronous PAE/PAF configuration is selected , the PAE is asserted and updated on the rising edge of
RCLK only, and not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK only, and not
RCLK. The mode desired is configured during master reset by the state of the programmable flag mode (PFM).
The retransmit function allows data to be reread from the FIFO more than once. A low on the retransmit (RT)
input during a rising RCLK edge initiates a retransmit operation by setting the read pointer to the first location
of the memory array. Zero-latency retransmit timing mode can be selected using the retransmit timing mode
(RM). During master reset, a low on RM selects zero-latency retransmit. A high on RM during master reset
selects normal latency.
If zero-latency retransmit operation is selected, the first data word to be retransmitted is placed on the output
register, with respect to the same RCLK edge that initiated the retransmit, if RT is low.
See Figures 11 and 12 for normal latency retransmit timing. See Figures 13 and 14 for zero-latency retransmit
timing.
The devices can be configured with different input and output bus widths (see Table 1).
†
Table 1. Bus-Matching Configuration Modes
WRITE-PORT
WIDTH
READ-PORT
WIDTH
BM
IW
OW
L
L
L
L
L
×36
×36
×36
×18
×9
×36
×18
×9
H
H
H
H
L
H
L
H
H
×36
×36
H
†
Logic levels during master reset
A big-endian/little-endian data word format is provided. This function is useful when data is written into the FIFO
in long-word (×36/×18) format and read out of the FIFO in small-word (×18/×9) format. If big-endian mode is
selected, the most-significant byte (MSB) (word) of the long word written into the FIFO is read out of the FIFO
first, followed by the least-significant byte (LSB). If little-endian format is selected, the LSB of the long word
written into the FIFO is read out first, followed by the MSB. The mode desired is configured during master reset
by the state of the big-endian/little-endian (BE) pin (see Figure 4 for the bus-matching byte arrangement).
Theinterspersed/noninterspersedparity(IP)bitfunctionallowstheusertoselecttheparitybitinthewordloaded
into the parallel port (D0–Dn) when programming the flag offsets. If interspersed-parity mode is selected, the
FIFO assumes that the parity bit is located in bit positions D8, D17, D26, and D35 during the parallel
programming of the flag offsets. If noninterspersed-parity mode is selected, D8, D17, and D26 are assumed
to be valid bits, and D32, D33, D34, and D35 are ignored. Interspersed parity mode is selected during master
reset by the state of the IP input. Interspersed parity control has an effect only during parallel programming of
the offset registers. It does not affect data written to and read from the FIFO.
The SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, and SN74V3690 are fabricated using
high-speed submicron CMOS technology, and are characterized for operation from 0°C to 70°C.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
Big endian/little endian. During master reset, a low on BE selects big-endian operation. A high on BE during master
reset selects little-endian format.
†
BE
I
I
Bus matching. BM works with IW and OW to select the bus sizes for both write and read ports (see Table 1 for bus-size
configuration).
†
BM
Data inputs. Data inputs for a 36-, 18-, or 9-bit bus. When in 18- or 9-bit mode, the unused input pins are in a
don’t-care state.
D0–D36
EF/OR
FF/IR
I
Empty flag/output ready. In standard mode, the EF function is selected. EF indicates whether the FIFO memory is
empty. In FWFT mode, the OR function is selected. OR indicates whether there is valid data available at the outputs.
O
O
I
Full flag/input ready. In standard mode, the FF function is selected. FF indicates whether the FIFO memory is full. In
FWFT mode, the IR function is selected. IR indicates whether there is space available for writing to the FIFO memory.
Flag-select bit 0. During master reset, FSEL0, along with FSEL1 and LD, selects the default offset values for PAE and
PAF. Up to eight possible settings are available.
†
FSEL0
FSEL1
Flag-select bit 1. During master reset, FSEL1, along with FSEL0 and LD, selects the default offset values for PAE and
PAF. Up to eight possible settings are available.
†
I
First-word fall-through/serial in. During master reset, FWFT/SI selects FWFT or standard mode. After master reset,
FWFT/SI functions as a serial input for loading offset registers.
FWFT/SI
HF
I
O
Half-full flag. HF indicates whether the FIFO memory is more or less than half full.
Interspersed parity. During master reset, a low on IP selects noninterspersed-parity mode. A high selects
interspersed-parity mode. Interspersed-parity control has an effect only during parallel programming of the offset
registers. It does not effect data written to and read from the FIFO.
†
IP
I
I
†
IW
Input width. IW, along with OW and BM, selects the bus width of the write port (see Table 1 for bus-size configuration).
Load. This is a dual-purpose pin. During master reset, the state of LD, along with FSEL0 and FSEL1, determines one
of eight default offset values for PAE and PAF, along with the method by which these offset registers can be
programmed, parallel or serial (see Table 2). After master reset, LD enables writing to and reading from the offset
registers.
LD
I
Master reset. MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During
master reset, the FIFO is configured for either FWFT or standard mode, bus-matching configurations, one of eight
programmable-flag default settings, serial or parallel programming of the offset settings, big-endian/little-endian
format, zero-latency timing mode, interspersed parity, and synchronous versus asynchronous programmable-flag
timing modes.
MRS
OE
I
I
I
Output enable. OE controls the output impedance of Qn.
†
OW
Outputwidth. OW, alongwithIWandBM, selectsthebuswidthofthereadport(seeTable1forbus-sizeconfiguration).
Programmablealmost-emptyflag.PAEgoeslowifthenumberofwordsintheFIFOmemoryislessthanoffsetn, which
is stored in the empty offset register. PAE goes high if the number of words in the FIFO memory is greater than, or
equal to, offset n.
PAE
O
Programmable almost-full flag. PAF goes high if the number of free locations in the FIFO memory is more than
offset m, which is stored in the full offset register. PAF goes low if the number of free locations in the FIFO memory
is less than, or equal to, m.
PAF
PFM
PRS
O
I
Programmable-flagmode. During master reset, a lowonPFMselectsasynchronousprogrammable-flagtimingmode.
A high on PFM selects synchronous programmable-flag timing mode.
†
Partial reset. PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During partial
reset, the existing mode (standard or FWFT), programming method (serial or parallel), and programmable-flag
settings are all retained.
I
Data outputs. Data outputs for a 36-, 18-, or 9-bit bus. When in 18- or 9-bit mode, the unused output pins are in a
don’t-care state. Outputs are not 5-V tolerant, regardless of the state of OE.
Q0–Q35
O
I
Read clock. When enabled by REN, the rising edge of RCLK reads data from the FIFO memory and offsets from the
programmable registers.
RCLK
†
Inputs should not change state after master reset.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
Terminal Functions (Continued)
TERMINAL
NAME
I/O
DESCRIPTION
REN
I
I
Read enable. REN enables RCLK for reading data from the FIFO memory and offset registers.
Retransmit latency mode. During master reset, a low on RM selects zero-latency retransmit timing mode. A high on
RM selects normal-latency mode.
†
RM
Retransmit. RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to low (OR
to high in FWFT mode) and does not disturb the write pointer, programming method, existing timing mode, or
programmable-flag settings. RT is useful to reread data from the first physical location of the FIFO.
RT
I
I
I
I
SEN
Serial enable. SEN enables serial loading of programmable flag offsets.
Write clock. When enabled by WEN, the rising edge of WCLK writes data into the FIFO and offsets into the
programmable registers for parallel programming and, when enabled by SEN, the rising edge of WCLK writes one bit
of data into the programmable register for serial programming.
WCLK
WEN
Write enable. WEN enables WCLK for writing data into the FIFO memory and offset registers.
†
Inputs should not change state after master reset.
detailed description
inputs
data in (D0–Dn)
D0–D35 are data inputs for 36-bit-wide data. D0–D17 are data inputs for 18-bit-wide data. D0–D8 are data
inputs for 9-bit-wide data.
controls
master reset (MRS)
A master reset is accomplished when MRS is taken low. This operation sets the internal read and write pointers
to the first location of the RAM array. PAE goes low, PAF goes high, and HF goes high.
If FWFT/SI is low during master reset, the standard mode, EF, and FF are selected. EF goes low and FF goes
high. If FWFT/SI is high, the FWFT mode, IR, and OR are selected. OR goes high and IR goes low.
All control settings, such as OW, IW, BM, BE, RM, PFM, and IP are defined during the master reset cycle.
During a master reset, the output register is initialized to all zeroes. A master reset is required after power up,
before a write operation can take place. MRS is asynchronous.
See Figure 5 for timing information.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
partial reset (PRS)
A partial reset is accomplished when the PRS input is taken to a low state. As in the case of the master reset,
the internal read and write pointers are set to the first location of the RAM array, PAE goes low, PAF goes high,
and HF goes high.
Whichever mode is active at the time of partial reset remains selected (standard or FWFT mode). If standard
mode is active, FF goes high and EF goes low. If the FWFT mode is active, OR goes high and IR goes low.
Following partial reset, all values held in the offset registers remain unchanged. The programming method
(parallel or serial) active at the time of partial reset also is retained. The output register is initialized to all zeroes.
PRS is asynchronous.
A partial reset is useful for resetting the device during operation when reprogramming programmable-flag
offsets might not be convenient.
See Figure 6 for timing information.
retransmit (RT)
The retransmit operation allows previously read data to be accessed again. There are two modes of retransmit
operation: normal latency and zero latency. There are two stages to retransmit. The first stage is a setup
procedure that resets the read pointer to the first location of memory. The second stage is the actual retransmit,
which consists of reading out the memory contents, starting at the beginning of the memory.
Retransmit setup is initiated by holding RT low during a rising RCLK edge. REN and WEN must be high before
bringing RT low. When zero latency is utilized, REN need not be high before bringing RT low.
If standard mode is selected, the FIFO marks the beginning of the retransmit setup by setting EF low. The
change in level is noticeable only if EF was high before setup. During this period, the internal read pointer is
initialized to the first location of the RAM array.
When EF goes high, retransmit setup is complete and read operations can begin, starting with the first location
in memory. Because standard mode is selected, every word read, including the first word following retransmit
setup, requires a low on REN to enable the rising edge of RCLK.
See Figure 11 for timing information.
If FWFT mode is selected, the FIFO marks the beginning of the retransmit setup by setting OR high. During this
period, the internal read pointer is set to the first location of the RAM array.
When OR goes low, retransmit setup is complete. At the same time, the contents of the first location appear on
the outputs. Because FWFT mode is selected, the first word appears on the outputs and no low on REN is
necessary. Reading all subsequent words requires a low on REN to enable the rising edge of RCLK.
See Figure 12 for timing information.
In retransmit operation, zero-latency mode can be selected using the retransmit latency mode (RM) pin during
a master reset. This can be applied to the standard mode and the FWFT mode.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
first-word fall-through/serial in (FWFT/SI)
FWFT/SI is a dual-purpose pin. During master reset, the state of the FWFT/SI input determines whether the
device operates in standard or FWFT mode.
If, atthetimeofmasterreset, FWFT/SIislow, standardmodeisselected. ThismodeusesEFtoindicatewhether
any words are present in the FIFO memory. It also uses FF to indicate whether the FIFO memory has free space
for writing. In standard mode, every word read from the FIFO, including the first, must be requested using REN
and RCLK.
If, at the time of master reset, FWFT/SI is high, FWFT mode is selected. This mode uses OR to indicate whether
there is valid data at the data outputs (Qn). It also uses IR to indicate whether the FIFO memory has free space
for writing. In the FWFT mode, the first word written to an empty FIFO goes directly to Qn after three RCLK rising
edges, therefore, REN = low is not necessary. Subsequent words must be accessed using REN and RCLK.
After master reset, FWFT/SI acts as a serial input for loading PAE and PAF offsets into the programmable
registers. The serial input function can be used only when the serial loading method is selected during master
reset. Serial programming using the FWFT/SI pin functions the same way in both standard and FWFT modes.
write clock (WCLK)
A write cycle is initiated on the rising edge of the WCLK input. Data setup and hold times must be met, with
respect to the low-to-high transition of the WCLK. It is permissible to stop WCLK. Note that while WCLK is idle,
the FF/IR, PAF, and HF flags are not updated. WCLK is capable only of updating HF flag to low. The write and
read clocks can be independent or coincident.
write enable (WEN)
When WEN is low, data may be loaded into the FIFO RAM array on the rising edge of every WCLK cycle if the
device is not full. Data is stored in the RAM array sequentially and independently of any ongoing read operation.
When WEN is high, no new data is written in the RAM array on each WCLK cycle.
To prevent data overflow in the standard mode, FF goes low, inhibiting further write operations. After completion
of a valid read cycle, FF goes high, allowing a write to occur. FF is updated by two WCLK cycles + t after the
sk
RCLK cycle.
To prevent data overflow in the FWFT mode, IR goes high, inhibiting further write operations. After completion
of a valid read cycle, IR goes low, allowing a write to occur. The IR flag is updated by two WCLK cycles + t
after the valid RCLK cycle.
sk
WEN is ignored when the FIFO is full in either FWFT or standard mode.
read clock (RCLK)
A read cycle is initiated on the rising edge of the RCLK input. Data can be read on the outputs, on the rising edge
of the RCLK input. It is permissible to stop RCLK. While RCLK is idle, the EF/OR, PAE, and HF flags are not
updated. RCLK is capable only of updating the HF flag to high. The write and read clocks can be independent
or coincident.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
read enable (REN)
When REN is low, data is loaded from the RAM array into the output register on the rising edge of every RCLK
cycle, if the device is not empty.
When REN is high, the output register holds the previous data and no new data is loaded into the output register.
The data outputs Q0–Qn maintain the previous data value.
In standard mode, every word accessed at Qn, including the first word written to an empty FIFO, must be
requested using REN. When the last word has been read from the FIFO, the empty flag (EF) goes low, inhibiting
further read operations. REN is ignored when the FIFO is empty. Once a write is performed, EF goes high,
allowing a read to occur. The EF flag is updated by two RCLK cycles + t after the valid WCLK cycle.
sk
In FWFT mode, the first word written to an empty FIFO automatically goes to the outputs Qn, on the third valid
low-to-high transition of RCLK + t after the first write. REN need not be asserted low. In order to access all
sk
other words, a read must be executed using REN. The RCLK low-to-high transition after the last word has been
read from the FIFO and OR goes high with a true read (RCLK with REN = low), inhibiting further read operations.
REN is ignored when the FIFO is empty.
serial enable (SEN)
The SEN input is an enable used only for serial programming of the offset registers. The serial programming
method must be selected during master reset. SEN always is used with LD. When these lines are both low, data
at the SI input can be loaded into the program register, with one bit for each low-to-high transition of WCLK.
When SEN is high, the programmable registers retain the previous settings and no offsets are loaded. SEN
functions the same way in standard and FWFT modes.
output enable (OE)
When output enable is asserted (low), the parallel output buffers receive data from the output register. When
OE is high, the output data bus (Qn) goes into the high-impedance state.
load (LD)
LD is a dual-purpose pin. During master reset, the state of the LD input, along with FSEL0 and FSEL1,
determines one of eight default offset values for the PAE and PAF flags, along with the method by which these
offset registers can be programmed, parallel or serial (see Table 2). After master reset, LD enables write
operations to, and read operations from, the offset registers. Only the offset loading method currently selected
can be used to write to the registers. Offset registers can be read only in parallel.
After master reset, LD activates the programming process of the flag offset values PAE and PAF. Pulling LD low
begins a serial loading, or a parallel load, or a read of these offset values.
bus matching (BM, IW, OW)
BM, IW, and OW define the input and output bus widths. During master reset, the state of these pins is used
to configure the device bus sizes (see Table 1 for control settings). All flags operate on the word/byte-size
boundary, as defined by the selection of bus width (see Figure 4 for the bus-matching byte arrangement).
big endian/little endian (BE)
During master reset, a low on BE selects big-endian operation. A high on BE during master reset selects
little-endian format. This function is useful when the following input-to-output bus widths are implemented: ×36
to ×18, ×36 to ×9, ×18 to ×36, and ×9 to ×36. If big-endian mode is selected, the MSB (word) of the long word
written into the FIFO is read out of the FIFO first, followed by the LSB. If little-endian format is selected, the LSB
of the long word written into the FIFO is read out first, followed by the MSB. The desired mode is configured
during master reset by the state of BE (see Figure 4 for bus-matching byte arrangement).
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
programmable-flag mode (PFM)
During master reset, a low on PFM selects asynchronous programmable-flag timing mode. A high on PFM
selects synchronous programmable-flag timing mode. If asynchronous PAF/PAE configuration is selected
(PFM low during MRS), PAE is asserted low on the low-to-high transition of RCLK. PAE is reset to high on the
low-to-high transition of WCLK. Similarly, PAF is asserted low on the low-to-high transition of WCLK, and PAF
is reset to high on the low-to-high transition of RCLK.
If synchronous PAE/PAF configuration is selected (PFM high during MRS), PAE is asserted and updated on the
rising edge of RCLK only, and not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK
only and not RCLK. The mode desired is configured during master reset by the state of the PFM.
interspersed parity (IP)
During master reset, a low on IP selects noninterspersed-parity mode. A high selects interspersed-parity mode.
The IP bit function allows the user to select the parity bit in the word loaded into the parallel port (D0–Dn) when
programming the flag offsets. If interspersed-parity mode is selected, the FIFO assumes that the parity bits are
located in bit positions D8, D17, D26, and D35 during the parallel programming of the flag offsets. If
noninterspersed-parity mode is selected, D8, D17, and D28 are assumed to be valid bits and D32, D33, D34,
and D35 are ignored. IP mode is selected during master reset by the state of the IP input pin. Interspersed-parity
control has an effect only during parallel programming of the offset registers. It does not affect the data written
to, and read from, the FIFO.
outputs
full flag/input ready (FF/IR)
FF/IR is a dual-purpose pin. In standard mode, the FF function is selected. When the FIFO is full, FF goes low,
inhibiting further write operations. When FF is high, the FIFO is not full. If no reads are performed after a reset
(either MRS or PRS), FF goes low after D writes to the FIFO (D = 1024 for the SN74V3640, D = 2048 for the
SN74V3650, D = 4096 for the SN74V3660, D = 8192 for the SN74V3670, D = 16384 for the SN74V3680, and
D = 32768 for the SN74V3690).
See Figure 7 for timing information.
In FWFT mode, the IR function is selected. IR goes low when memory space is available for writing in data.
When there is no longer any free space left, IR goes high, inhibiting further write operations. If no reads are
performed after a reset (either MRS or PRS), IR goes high after D writes to the FIFO (D = 1025 for the
SN74V3640, D = 2049 for the SN74V3650, D = 4097 for the SN74V3660, D = 8193 for the
SN74V3670, D = 16385 for the SN74V3680, and D = 32769 for the SN74V3690).
See Figure 9 for timing information.
The IR status not only measures the contents of the FIFO memory, but also counts the presence of a word in
the output register. Thus, in FWFT mode, the total number of writes necessary to deassert IR is one greater than
needed to assert FF in standard mode.
FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR are double register-buffered outputs.
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
empty flag/output ready (EF/OR)
EF/OR is a dual-purpose pin. In the standard mode, the EF function is selected. When the FIFO is empty, EF
goes low, inhibiting further read operations. When EF is high, the FIFO is not empty.
See Figure 8 for timing information.
In FWFT mode, the OR function is selected. OR goes low at the same time the first word written to an empty
FIFO appears valid on the outputs. OR stays low after the RCLK low-to-high transition that shifts the last word
from the FIFO memory to the outputs. OR goes high only with a true read (RCLK with REN = low). The previous
data stays at the outputs, indicating the last word was read. Further data reads are inhibited until OR goes low
again.
See Figure 10 for timing information.
EF/OR is synchronous and updated on the rising edge of RCLK.
In standard mode, EF is a double register-buffered output. In FWFT mode, OR is a triple register-buffered
output.
programmable almost-full flag (PAF)
PAF goes low when the FIFO reaches the almost-full condition. In standard mode, if no reads are performed
after reset (MRS), PAF goes low after (D – m) words are written to the FIFO. The PAF goes low after (1024 – m)
writes for the SN74V3640, (2048 – m) writes for the SN74V3650, (4096 – m) writes for the SN74V3660,
(8192 – m) writes for the SN74V3670, (16384 – m) writes for the SN74V3680, and (32768 – m) writes for the
SN74V3690. The offset m is the full offset value. The default setting for this value is shown in Table 2.
In FWFT mode, PAF goes low after (1025 – m) writes for the SN74V3640, (2049 – m) writes for the SN74V3650,
(4097 – m) writes for the SN74V3660, (8193 – m) writes for the SN74V3670, (16385 – m) writes for the
SN74V3680, and (32769 – m) writes for the SN74V3690. The offset m is the full offset value. The default setting
for this value is shown in Table 2.
See Figure 18 for timing information.
If the asynchronous PAF configuration is selected, PAF is asserted low on the low-to-high transition of WCLK.
PAF is reset to high on the low-to-high transition of RCLK. If the synchronous PAF configuration is selected, PAF
is updated on the rising edge of WCLK.
See Figure 20 for timing information.
programmable almost-empty flag (PAE)
PAE goes low when the FIFO reaches the almost-empty condition. In standard mode, PAE goes low when there
are n words, or fewer, in the FIFO. The offset n is the empty offset value. The default setting for this value is
shown in Table 2.
In FWFT mode, PAE goes low when there are n + 1 words, or fewer, in the FIFO. The default setting for this
value is shown in Table 2.
See Figure 19 for timing information.
If the asynchronous PAE configuration is selected, PAE is asserted low on the low-to-high transition of RCLK.
PAE is reset to high on the low-to-high transition of WCLK. If the synchronous PAE configuration is selected,
PAE is updated on the rising edge of RCLK.
See Figure 21 for timing information.
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
half-full flag (HF)
HF indicates a half-full FIFO. The rising WCLK edge that fills the FIFO beyond half-full sets HF low. The flag
remains low until the difference between the write and read pointers becomes less than, or equal to, one-half
of the total depth of the device. The rising RCLK edge that accomplishes this condition sets HF high.
In standard mode, if no reads are performed after reset (MRS or PRS), HF goes low after (D/2 + 1) writes to
the FIFO, where D = 1024 for the SN74V3640, D = 2048 for the SN74V3650, D = 4096 for the SN74V3660,
D = 8192 for the SN74V3670, D = 16384 for the SN74V3680, and D = 32768 for the SN74V3690.
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF goes low after [(D – 1)/2] + 2 writes
to the FIFO, where D = 1025 for the SN74V3640, D = 2049 for the SN74V3650, D = 4097 for the SN74V3660,
D = 8193 for the SN74V3670, D = 16385 for the SN74V3680, and D = 32769 for the SN74V3690.
See Figure 22 for timing information. Because HF is updated by both RCLK WCLK, it is considered
asynchronous.
data outputs (Q0-Qn)
Q0–Q35 are data outputs for 36-bit-wide data. Q0–Q17 are data outputs for 18-bit-wide data. Q0–Q8 are data
outputs for 9-bit-wide data.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.5 V
CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Storage temperature range, T
O
O
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN
3.15
0
TYP
3.3
0
MAX
3.45
0
UNIT
V
V
Supply voltage (see Note 1)
CC
GND Supply voltage
V
V
V
High-level input voltage (see Note 2)
Low-level input voltage (see Note 3)
Operating free-air temperature
2
5.5
0.8
70
V
IH
V
IL
T
A
0
°C
NOTES: 1. V
CC
= 3.3 V ± 0.15 V, JEDEC JESD8-A compliant
2. Outputs are not 5-V tolerant.
3. 1.5-V undershoots are allowed for 10 ns once per cycle.
electrical characteristics over recommended operating conditions, t
15 ns (unless otherwise noted)
= 6 ns, 7.5 ns, 10 ns, and
CLK
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
I
I
= –2 mA
2.4
OH
OL
OH
V
0.4
±1
V
= 8 mA
OL
I
I
I
I
V = V
to 0.4 V
µA
µA
mA
mA
pF
pF
I
I
CC
OE ≥ V
,
V
= V to 0.4 V
CC
±10
40
OZ
IH
O
See Notes 4, 5, and 6
See Notes 4 and 7
CC1
CC2
15
C
C
V = 0,
T
A
= 25°C,
= 25°C,
f = 1 MHz
f = 1 MHz,
10
IN
I
V
= 0,
T
A
Output deselected (OE ≥ V )
IH
10
OUT
O
NOTES: 4. Tested with outputs open (I
OUT
= 0)
5. RCLK and WCLK switch at 20 MHz and data inputs switch at 10 MHz.
6. Typical I = 4.2 + 1.4 × f + 0.02 × C × f (in mA), with V = 3.3 V, T = 25°C, f = WCLK frequency = RCLK frequency (in MHz,
CC1 CC
S
L
S
A
S
using TTL levels), data switching at f /2, C = capacitive load (in pF)
S
L
7. All inputs = (V
– 0.2 V) or (GND + 0.2 V), except RCLK and WCLK, T = 25°C, which switch at 20 MHz.
CC
A
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
timing requirements over recommended ranges of supply voltage and operating free-air
†
temperature (see Figure 2 through Figure 22)
SN74V3640-6
SN74V3650-6
SN74V3660-6
SN74V3670-6
SN74V3680-6
SN74V3690-6
SN74V3640-7
SN74V3650-7
SN74V3660-7
SN74V3670-7
SN74V3680-7
SN74V3690-7
SN74V3640-10 SN74V3640-15
SN74V3650-10 SN74V3650-15
SN74V3660-10 SN74V3660-15
SN74V3670-10 SN74V3670-15
SN74V3680-10 SN74V3680-15
SN74V3690-10 SN74V3690-15
UNIT
MIN
MAX
166
4.5
MIN
MAX
133.3
5
MIN
MAX
100
6.5
MIN
MAX
66.7
10
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Clock cycle frequency
Data access time
Clock cycle time
Clock high time
Clock low time
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
clock
2
6
2
7.5
3.5
3.5
2.5
0.5
2.5
0.5
3.5
0.5
10
2
10
2
15
6
A
CLK
CLKH
CLKL
DS
2.5
2.5
1.5
0.5
1.5
0.5
2
4.5
4.5
3.5
0.5
3.5
0.5
3.5
0.5
10
6
Data setup time
Data hold time
4
1
DH
Enable setup time
Enable hold time
Load setup time
Load hold time
4
ENS
ENH
LDS
LDH
RS
1
4
0
1
‡
Reset pulse duration
10
15
10
15
15
15
Reset setup time
15
15
RSS
RSR
RSF
RTS
OLZ
OE
Reset recovery time
10
10
Reset to flag and output time
Retransmit setup time
15
15
15
15
2
0
2
2
3.5
0
3.5
0
4
0
2
2
Output enable to output in low impedance
Output enable to output valid
Output enable to output in high impedance
Write clock to FF or IR
4.5
4.5
4.5
4.5
8.5
4.5
8.5
4.5
9
2
6
6
2
6
6
8
8
2
2
OHZ
WFF
REF
PAFA
PAFS
PAEA
PAES
HF
5
6.5
6.5
16
6.5
16
6.5
16
10
10
20
10
20
10
20
Read clock to EF or OR
5
Clock to asynchronous PAF
Write clock to synchronous PAF
Clock to asynchronous PAE
Read clock to synchronous PAE
Clock to HF
12.5
5
12.5
5
12.5
Skew time between read clock and
write clock for EF/OR and FF/IR
t
4.5
4.5
5
7
7
9
ns
ns
sk1
sk2
Skew time between read clock and
write clock for PAE and PAF
t
10
14
†
‡
All ac timings apply to standard mode and FWFT mode.
Pulse durations less than minimum values are not allowed.
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
PARAMETER MEASUREMENT INFORMATION
1.5 V
AC TEST CONDITIONS
50 Ω
GND to 3.0 V
3 ns (see Note A)
1.5 V
Input Pulse Levels
Input Rise/Fall Times
Z
O
= 50 Ω
I/O
Input Timing Reference Levels
Output Reference Levels
1.5 V
See B
Output Load for t
Output Load for t
= 10 ns, 15 ns
= 6 ns, 7.5 ns
CLK
CLK
See A and C
A. AC TEST LOAD
FOR 6-ns AND 7.5-ns SPEED GRADES
3.3 V
6
5
4
3
2
1
0
330 Ω
From Output
Under Test
30 pF
(see Note B)
510 Ω
0
20 40 60 80 100 120 140 160 180 200
Capacitance – pF
B. OUTPUT LOAD CIRCUIT
C. LUMPED CAPACITIVE LOAD, TYPICAL DERATING
FOR 10-ns AND 15-ns SPEED GRADES
NOTES: A. For 133-MHz operation, input rise/fall times are 1.5 ns.
B. Includes probe and jig capacitance
Figure 2. Load Circuits
functional description
timing modes: FWFT mode vs standard mode
The SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, and SN74V3690 support two different
timing modes of operation: standard mode or FWFT mode. The mode is selected during master reset by the
state of the FWFT/SI input.
If, atthetimeofmasterreset, FWFT/SIislow, standardmodeisselected. ThismodeusesEFtoindicatewhether
any words are present in the FIFO. It also uses FF to indicate whether the FIFO has any free space for writing.
In standard mode, every word read from the FIFO, including the first word, must be requested using REN and
RCLK.
If, at the time of master reset, FWFT/SI is high, FWFT mode is selected. This mode uses OR to indicate whether
valid data is at the data outputs (Qn). It also uses IR to indicate whether the FIFO has any free space for writing.
In the FWFT mode, the first word written to an empty FIFO goes directly to Qn after three RCLK rising edges;
REN = low is not necessary. Subsequent words must be accessed using REN and RCLK.
Various signals (both input and output) operate differently, depending on which timing mode is in effect.
16
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SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
FWFT mode
In FWFT mode, status flags IR, PAF, HF, PAE, and OR operate as outlined in Table 4. To write data into the FIFO,
WEN must be low. Data presented to the DATA IN lines is clocked into the FIFO on subsequent transitions of
WCLK. After the first write is performed, the OR flag goes low. Subsequent writes continue to fill the FIFO. PAE
goes high after n + 2 words have been loaded into the FIFO, where n is the empty offset value. The default
settings for these values are shown in Table 2, and are user programmable.
If one continues to write data into the FIFO and assumes no read operations are taking place, HF switches to
low once the 514th word for the SN74V3640, 1026th word for the SN74V3650, 2050th word for the SN74V3660,
4098th word for the SN74V3670, 8194th word for the SN74V3680, and 16386th word for the SN74V3690, are
written into the FIFO. Continuing to write data into the FIFO causes PAF to go low. If no reads are performed,
PAF goes low after (1025 – m) writes for the SN74V3640, (2049 – m) writes for the SN74V3650, (4097 – m)
writes for the SN74V3660, (8193 – m) writes for the SN74V3670, (16385 – m) writes for the SN74V3680, and
(32769 – m) writes for the SN74V3690, where m is the full offset value. The default setting for these values is
shown in Table 2.
When the FIFO is full, the IR flag goes high, inhibiting further write operations. If no reads are performed after
a reset, IR goes high after D writes to the FIFO. D = 1025 writes for the SN74V3640, D = 2049 writes for the
SN74V3650, D = 4097 writes for the SN74V3660, D = 8193 writes for the SN74V3670, D = 16385 writes for
the SN74V3680, and D = 32769 writes for the SN74V3690. Note that the additional word in FWFT mode is due
to the capacity of the memory plus output register.
If the FIFO is full, the first read operation causes the IR flag to go low. Subsequent read operations cause PAF
andHFtogohighattheconditionsdescribedinTable4. Iffurtherreadoperationsoccurwithoutwriteoperations,
PAE goes low when there are n + 1 words in the FIFO, where n is the empty offset value. Continuing read
operations causes the FIFO to become empty. When the last word has been read from the FIFO, OR goes high,
inhibiting further read operations. REN is ignored when the FIFO is empty.
When configured in FWFT mode, the OR flag output is triple register buffered, and the IR flag output is double
register buffered.
See Figures 9, 10, 12, and 14 for timing information.
standard mode
In standard mode, status flags FF, PAF, HF, PAE, and EF operate as outlined in Table 3. To write data into the
FIFO, WEN must be low. Data presented to the DATA IN lines is clocked into the FIFO on subsequent transitions
of WCLK. After the first write is performed, EF goes high. Subsequent writes continue to fill the FIFO. PAE goes
high after n + 1 words have been loaded into the FIFO, where n is the empty offset value. The default setting
for these values is shown in Table 2. This parameter is also user programmable.
If one continues to write data into the FIFO and assumes no read operations are taking place, HF switches to
low after the 513rd word for SN74V3640, 1025th word for SN74V3650, 2049th word for SN74V3660,
4097th word for SN74V3670, 8193th word for the SN74V3680, and 16385th word for the SN74V3690 are
written into the FIFO. Continuing to write data into the FIFO causes PAF to go low. If no reads are performed,
PAF goes low after (1024 – m) writes for the SN74V3640, (2048 – m) writes for the SN74V3650, (4096 – m)
writes for the SN74V3660, (8192 – m) writes for the SN74V3670, (16384 – m) writes for the SN74V3680, and
(32768 – m) writes for the SN74V3690. Offset m is the full offset value. The default setting for these values is
in the footnote of Table 2. This parameter is also user programmable.
When the FIFO is full, FF goes low, inhibiting further write operations. If no reads are performed after a reset,
FF goes low after D writes to the FIFO. D = 1024 writes for the SN74V3640, D = 2048 writes for the SN74V3650,
D = 4096 writes for the SN74V3660, D = 8192 writes for the SN74V3670, D = 16384 writes for the SN74V3680,
and D = 32768 writes for the SN74V3690.
17
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SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
standard mode (continued)
If the FIFO is full, the first read operation causes FF to go high. Subsequent read operations cause PAF and
HF to go high at the conditions described in Table 3. If further read operations occur without write operations,
PAE goes low when there are n words in the FIFO, where n is the empty offset value. Continuing read operations
causes the FIFO to become empty. When the last word has been read from the FIFO, EF goes low, inhibiting
further read operations. REN is ignored when the FIFO is empty.
When configured in standard mode, the EF and FF outputs are register-buffered outputs.
See Figures 7, 8, 11, and 13 for timing information.
Table 2. Default Programmable Flag Offsets
SN74V3640, SN74V3650
FSEL1 FSEL0 OFFSETS (n, m)
SN74V3660, SN74V3670, SN74V3680, SN74V3690
†
†
LD
L
LD
H
L
FSEL1 FSEL0
OFFSETS (n, m)
H
L
L
H
L
511
255
127
63
31
15
7
L
H
L
L
L
1,023
511
255
127
63
L
L
L
L
H
L
L
H
L
H
L
L
L
H
H
H
H
L
H
H
L
H
L
H
L
L
H
H
H
31
H
H
H
H
15
H
3
H
7
PROGRAM MODE
PROGRAM MODE
‡
‡
Serial
H
L
X
X
X
X
Serial
H
L
X
X
X
X
§
§
Parallel
Parallel
†
‡
n = empty offset for PAE, m = full offset for PAF
As well as selecting serial programming mode, one of the default values also is loaded, depending on the state
of FSEL0 and FSEL1.
§
As well as selecting parallel programming mode, one of the default values also is loaded, depending on the state
of FSEL0 and FSEL1.
programming flag offsets
Full and empty flag offset values are user programmable. The SN74V3640, SN74V3650, SN74V3660,
SN74V3670, SN74V3680, and SN74V3690 have internal registers for these offsets. Eight default offset values
are selectable during master reset. These offset values are shown in Table 2. Offset values can also be
programmed into the FIFO by serial or parallel loading. The loading method is selected using LD. During master
reset, the state of the LD input determines whether serial or parallel flag offset programming is enabled. A high
on LD during master reset selects serial loading of offset values. A low on LD during master reset selects parallel
loading of offset values.
InadditiontoloadingoffsetvaluesintotheFIFO, itisalsopossibletoreadthecurrentoffsetvalues. Offsetvalues
canbereadviatheparalleloutputportQ0–Qn, regardlessoftheprogrammingmodeselected(serialorparallel).
It is not possible to read the offset values in serial fashion.
Figure 3 summarizes the control pins and sequence for both serial and parallel programming modes. A more
detailed description is given in the following paragraphs.
The offset registers may be programmed (and reprogrammed) any time after master reset, regardless of
whether serial or parallel programming has been selected. Valid programming ranges are from 0 to D – 1.
18
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SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
synchronous vs asynchronous programmable flag timing selection
The SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, and SN74V3690 can be configured
during the master reset cycle, with either synchronous or asynchronous timing for PAF and PAE, by use of the
PFM pin.
If synchronous PAF/PAE configuration is selected (PFM high during MRS), PAF is asserted and updated on the
rising edge of WCLK only and not RCLK. Similarly, PAE is asserted and updated on the rising edge of RCLK
only, and not WCLK (see Figure 17 for synchronous PAF timing and Figure 18 for synchronous PAE timing).
If asynchronous PAF/PAE configuration is selected (PFM low during MRS), PAF is asserted low on the
low-to-high transition of WCLK, and PAF is reset to high on the low-to-high transition of RCLK. Similarly, PAE
is asserted low on the low-to-high transition of RCLK. PAE is reset to high on the low-to-high transition of WCLK.
See Figure 19 for asynchronous PAF timing and Figure 20 for asynchronous PAE timing.
Table 3. Status Flags for Standard Mode
SN74V3640
0
SN74V3650
0
SN74V3660
0
SN74V3670
0
FF PAF HF PAE EF
H
H
H
H
H
H
H
H
H
L
L
L
H
H
1 to n
1 to n
1 to n
1 to n
Number of
Words in
FIFO (see
Note 8)
(n + 1) to 512
(n + 1) to 1024
(n + 1) to 2048
(n + 1) to 4096
H
513 to
[1024 – (m + 1)]
1025 to
[2048 – (m + 1)]
2049 to
[4096 – (m + 1)]
4097 to
[8192 – (m + 1)]
H
H
L
H
H
(1024 – m) to 1023
(2048 – m) to 2047
(4096 – m) to 4095
(8192 – m) to 8191
H
L
L
L
L
L
H
H
H
H
1024
2048
4096
8192
SN74V3680
0
SN74V3690
FF PAF HF PAE EF
0
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
Number of
Words in
FIFO (see
Note 8)
1 to n
1 to n
H
H
H
H
H
(n + 1) to 8192
(n + 1) to 16384
H
H
H
H
8193 to [16384 – (m + 1)] 16385 to [32768 – (m + 1)]
(16384 – m) to 16383
(32768 – m) to 32767
L
16384
32768
L
L
NOTE 8: See Table 2 for values for n, m.
19
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1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
Table 4. Status Flags for FWFT Mode
SN74V3640
0
SN74V3650
0
SN74V3660
0
SN74V3670
0
IR
L
PAF HF PAE OR
H
H
H
H
H
H
L
L
H
L
L
1 to (n + 1)
(n + 2) to 513
1 to (n + 1)
(n + 2) to 1025
1 to (n + 1)
(n + 2) to 2049
1 to (n + 1)
(n + 2) to 4097
L
Number of
Words in
FIFO (see
Note 8)
L
H
514 to
[1025 – (m + 1)]
1026 to
[2049 – (m + 1)]
2050 to
[4097 – (m + 1)]
4098 to
[8193 – (m + 1)]
L
H
L
H
L
(1025 – m) to 1024
(2049 – m) to 2048
(4097 – m) to 4096
(8193 – m) to 8192
L
L
L
L
L
H
H
L
L
1025
2049
4097
8193
H
SN74V3680
0
SN74V3690
0
IR
L
PAF HF PAE OR
H
H
H
H
H
H
L
L
H
L
L
1 to (n + 1)
(n + 2) to 8193
1 to (n + 1)
(n + 2) to 16385
L
Number of
Words in
FIFO (see
Note 8)
L
H
16386 to
[32769 – (m + 1)]
8194 to [16385 – (m + 1)]
L
H
L
H
L
(16385 – m) to 16384
(32769 – m) to 32768
L
L
L
L
L
H
H
L
L
16385
32769
H
NOTE 8: See Table 2 for values for n, m.
SN74V3640, SN74V3650, SN74V3660,
SN74V3670, SN74V3680, SN74V3690
LD
WEN
REN
SEN WCLK RCLK
Parallel write to registers:
Empty offset (LSB)
Empty offset (MSB)
Full offset (LSB)
0
0
1
1
1
↑
X
Full offset (MSB)
Parallel read from registers:
Empty offset (LSB)
Empty offset (MSB)
Full offset (LSB)
0
0
1
1
0
1
X
↑
Full offset (MSB)
Serial shift into registers:
20 bits for the SN74V3640
22 bits for the SN74V3650
24 bits for the SN74V3660
26 bits for the SN74V3670
28 bits for the SN74V3680
30 bits for the SN74V3690
1 bit for each rising WCLK edge,
starting with empty offset (LSB)
ending with full offset (MSB)
0
↑
X
X
1
1
1
1
0
X
1
1
X
0
1
1
X
X
X
X
↑
X
X
↑
No operation
Write memory
Read memory
No operation
X
X
X
NOTES: A. The programming method can be selected only at master reset.
B. Parallel reading of the offset registers is always permitted, regardless of which programming method has been selected.
C. The programming sequence applies to FWFT and standard modes.
Figure 3. Programmable Flag Offset Programming Sequence
Figure 1Figure 2
20
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1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
1st Parallel Offset Write/Read Cycle
Data Inputs/Outputs
D/Q8
EMPTY OFFSET REGISTER (PAE) BIT LOCATIONS
D/Q35
D/Q15
D/Q0
X
X
X
X
X
X
X
X
X
15 14 13 12 11 10
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
Noninterspersed Parity
Interspersed Parity
X
X
15 14 13 12 11 10
9
X
2nd Parallel Offset Write/Read Cycle
Data Inputs/Outputs
D/Q35
D/Q17
D/Q8
FULL OFFSET REGISTER (PAF) BIT LOCATIONS
D/Q0
X
X
X
X
X
X
X
16 15 14 13 12 11 10
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
Noninterspersed Parity
Interspersed Parity
X
X
16 15 14 13 12 11 10
9
X
×36 Bus Width
1st Parallel Offset Write/Read Cycle
D/Q17
D/Q15
Data Inputs/Outputs
EMPTY OFFSET (LSB) REGISTER (PAE) BIT LOCATIONS
D/Q0
X
X
X
15 14 13 12 11 10
9
X
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
Noninterspersed Parity
Interspersed Parity
X
15 14 13 12 11 10
9
D/Q8
2nd Parallel Offset Write/Read Cycle
D/Q17
D/Q15
Data Inputs/Outputs
FULL OFFSET (LSB) REGISTER (PAF) BIT LOCATIONS
D/Q0
X
X
X
15 14 13 12 11 10
9
X
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
Noninterspersed Parity
Interspersed Parity
X
15 14 13 12 11 10
9
D/Q8
×18 Bus Width
Number of bits used:
10 bits for the SN74V3640
11 bits for the SN74V3650
12 bits for the SN74V3660
13 bits for the SN74V3670
14 bits for the SN74V3680
15 bits for the SN74V3690
Note: All unused bits of the
LSB and MSB are don’t care.
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
Figure 1Figure 2
21
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SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
1st Parallel Offset Write/Read Cycle
D/Q8
D/Q0
EMPTY OFFSET REGISTER (PAE) BIT LOCATIONS
X
8
7
6
5
4
3
2
1
2nd Parallel Offset Write/Read Cycle
D/Q8
D/Q0
EMPTY OFFSET REGISTER (PAE) BIT LOCATIONS
X
16
15
14
13
12
11
10
9
3rd Parallel Offset Write/Read Cycle
D/Q8
D/Q0
FULL OFFSET REGISTER (PAF) BIT LOCATIONS
X
8
7
6
5
4
3
2
1
4th Parallel Offset Write/Read Cycle
D/Q8
D/Q0
FULL OFFSET REGISTER (PAF) BIT LOCATIONS
16 15 14 13 12 11 10
X
9
×9 Bus Width
Number of bits used:
10 bits for the SN74V3640
11 bits for the SN74V3650
12 bits for the SN74V3660
13 bits for the SN74V3670
14 bits for the SN74V3680
15 bits for the SN74V3690
Note: All unused bits of the
LSB and MSB are don’t care.
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
serial programming mode
If the serial programming mode has been selected as described previously, programming of PAE and PAF
values can be achieved by using a combination of the LD, SEN, WCLK, and SI inputs. Programming PAE and
PAF proceeds as follows. When LD and SEN are set low, data on the SI input are written, one bit for each WCLK
rising edge, starting with the empty offset LSB and ending with the full offset MSB. This makes a total of 20 bits
for the SN74V3640, 22 bits for the SN74V3650, 24 bits for the SN74V3660, 26 bits for the SN74V3670, 28 bits
for the SN74V3680, and 30 bits for the SN74V3690.
See Figure 15 for the timing information.
Using the serial method, individual registers cannot be programmed selectively. PAE and PAF can show a valid
status only after the complete set of bits (for all offset registers) has been entered. The registers can be
reprogrammed, as long as the complete set of new offset bits is entered. When LD is low and SEN is high, no
serial write to the registers can occur.
22
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serial programming mode (continued)
Write operations to the FIFO are allowed before and during the serial programming sequence. In this case, the
programming of all offset bits need not occur at once. A select number of bits can be written to the SI input and
then, by bringing LD and SEN high, data can be written to FIFO memory via Dn by switching WEN. When WEN
is brought high with LD and SEN restored to a low, the next offset bit in sequence is written to the registers via
SI. If an interruption of serial programming is desired, it is sufficient either to set LD low and deactivate SEN,
or to set SEN low and deactivate LD. When LD and SEN are restored to a low level, serial offset programming
continues.
From the time serial programming begins, neither programmable flag is valid until the full set of bits required
to fill all the offset registers is written. Measuring from the rising WCLK edge that achieves the previous criteria,
PAF is valid after two more rising WCLK edges + t
. PAE is valid after the next two rising RCLK edges
PAF
+ t
+ t
.
PAE
sk2
Flag offset values can be read only via parallel output port Qn.
parallel programming mode
If the parallel programming mode has been selected as described previously, programming of PAE and PAF
values can be achieved by using a combination of the LD, WCLK , WEN and Dn inputs. Programming PAE and
PAF proceeds as follows. LD and WEN must be set low. For ×36-bit input bus width, data on the inputs Dn are
written into the Empty Offset register on the first low-to-high transition of WCLK. On the second low-to-high
transition of WCLK, data are written into the Full Offset register. The third transition of WCLK writes, once again,
to the Empty Offset register. For ×18-bit input bus width, data on the inputs Dn are written into the Empty Offset
register (LSB) on the first low-to-high transition of WCLK. On the second low-to-high transition of WCLK, data
are written into the Empty Offset (MSB) register. The third transition of WCLK writes to the Full Offset register
(LSB). The fourth transition of WCLK writes to the Full Offset register (MSB). The fifth transition of WCLK writes,
once again, to the Empty Offset register (LSB). A total of four writes to the offset registers is required to load
values using a ×18 input bus width. For an input bus width of ×9 bits, a total of six write cycles to the offset
registers is required to load values.
See Figures 3 and 16 for timing information.
Writing offsets in parallel employs a dedicated Write Offset register pointer. Reading offsets employs a
dedicated Read Offset register pointer. The two pointers operate independently; however, a read and a write
should not be performed simultaneously to the offset registers. A master reset initializes both pointers to the
Empty Offset register (LSB). A partial reset has no effect on the position of these pointers.
Write operations to the FIFO are allowed before and during the parallel programming sequence. In this case,
the programming of all offset registers need not occur at one time. One, two, or more offset registers can be
written to and then, by bringing LD high, write operations can be redirected to the FIFO memory. When LD is
set low again and WEN is low, the next offset register in sequence is written to. As an alternative to holding WEN
low and switching LD, parallel programming can also be interrupted by setting LD low and switching WEN.
Note that the status of a programmable-flag (PAE or PAF) output is invalid during the programming process.
From the time parallel programming has begun, a programmable-flag output is not valid until the appropriate
offset word has been written to the register(s) pertaining to that flag. Measuring from the rising WCLK edge that
achieves the previous criteria, PAF is valid after two more rising WCLK edges + t
. PAE is valid after the next
PAF
two rising RCLK edges + t
+ t
.
PAE
sk2
Reading the offset registers employs a dedicated read offset register pointer. The contents of the offset registers
can be read on the Q0–Qn pins when LD is set low and REN is set low. For ×36 output bus width, data are read
via Qn from the Empty Offset register on the first low-to-high transition of RCLK. On the second low-to-high
transition of RCLK, data are read from the Full Offset register. The third transition of RCLK reads, once again,
from the Empty Offset register. For ×18 output bus width, a total of four read cycles is required to obtain the
values of the offset registers, starting with the Empty Offset register (LSB) and finishing with the Full Offset
register (MSB). For ×9 output bus width, a total of six read cycles must be performed on the offset registers.
23
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SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
parallel programming mode (continued)
See Figures 3 and 17 for timing information.
It is permissible to interrupt the offset register read sequence with reads or writes to the FIFO. The interruption
is accomplished by deasserting REN, LD, or both together. When REN and LD are restored to a low level,
reading of the offset registers continues where it left off. It should be noted (and care should be taken from the
fact) that when a parallel read of the flag offsets is performed, the data word that was present on output lines
Qn is overwritten.
Parallel reading of the offset registers always is permitted, regardless of which timing mode (Standard or FWFT
modes) has been selected.
retransmit operation
The retransmit operation allows data that has been read to be accessed again. There are two modes of
retransmit operation: normal latency and zero latency. There are two stages to retransmit. The first stage is a
setup procedure that resets the read pointer to the first location of memory. The second stage is the actual
retransmit, which consists of reading out the memory contents, starting at the beginning of memory.
Retransmit setup is initiated by holding RT low during a rising RCLK edge. REN and WEN must be high before
bringing RT low. When zero latency is utilized, REN need not be high before bringing RT low. At least two words,
but no more than D – 2 words should have been written into the FIFO, and read from the FIFO, between reset
(master or partial) and the time of retransmit setup, D = 1024 for the SN74V3640, D = 2048 for the SN74V3650,
D = 4096 for the SN74V3660, D = 8192 for the SN74V3670, D = 16384 for the SN74V3680, and D = 32768 for
the SN74V3690. In FWFT mode, D = 1025 for the SN74V3640, D = 2049 for the SN74V3650, D = 4097 for the
SN74V3660, D = 8193 for the SN74V3670, D = 16385 for the SN74V3680, and D = 32769 for the SN74V3690.
If standard mode is selected, the FIFO marks the beginning of the retransmit setup by setting EF low. The
change in level is noticeable only if EF was high before setup. During this period, the internal read pointer is
initialized to the first location of the RAM array.
When EF goes high, retransmit setup is complete and read operations can begin, starting with the first location
in memory. Because standard mode is selected, every word read, including the first word following retransmit
setup, requires a low on REN to enable the rising edge of RCLK.
See Figure 11 for timing information.
If FWFT mode is selected, the FIFO marks the beginning of the retransmit setup by setting OR high. During this
period, the internal read pointer is set to the first location of the RAM array.
When OR goes low, retransmit setup is complete. At the same time, the contents of the first location appear on
the outputs. Because FWFT mode is selected, the first word appears on the outputs and no low on REN is
necessary. Reading all subsequent words requires a low on REN to enable the rising edge of RCLK.
See Figure 12 for timing information.
For either standard mode or FWFT mode, updating of PAE, HF, and PAF begins with the rising edge of RCLK
that RT is set up on. PAE is synchronized to RCLK, thus, on the second rising edge of RCLK after RT is set up,
PAE is updated. HF is asynchronous, thus, the rising edge of RCLK that RT is set up on updates HF. PAF is
synchronized to WCLK, thus, the second rising edge of WCLK that occurs t after the rising edge of RCLK that
sk
RT is set up on updates PAF. RT is synchronized to RCLK.
The retransmit function has the option of two modes of operation, either normal latency or zero latency.
Figures 11 and 12 show normal latency. Figures 13 and 14 show the zero-latency retransmit operation. Zero
latency means, basically, that the first data word to be retransmitted is placed in the output register, with respect
to the RCLK pulse that initiated the retransmit.
24
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SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
D35-D27
D26-D18
D17-D9
D8-D0
BYTE ORDER ON INPUT PORT:
BYTE ORDER ON OUTPUT PORT:
A
B
C
D
Write to FIFO
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BE
BM
IW
OW
A
B
C
D
Read from FIFO
X
L
L
L
(a) ×36 INPUT TO ×36 OUTPUT
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BE
BM
IW
OW
X
Q35-Q27
X
X
Q26-Q18
X
A
Q17-Q9
C
B
Q8-Q0
D
1st: Read from FIFO
2nd: Read from FIFO
L
H
L
L
(b) ×36 INPUT TO ×18 OUTPUT – BIG ENDIAN
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BE
BM
IW
OW
X
Q35-Q27
X
X
Q26-Q18
X
C
Q17-Q9
A
D
Q8-Q0
B
1st: Read from FIFO
2nd: Read from FIFO
H
H
L
L
(c) ×36 INPUT TO ×18 OUTPUT – LITTLE ENDIAN
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BE
BM
IW
OW
X
X
X
A
1st: Read from FIFO
2nd: Read from FIFO
3rd: Read from FIFO
4th: Read from FIFO
L
H
L
H
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
X
X
X
B
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
X
Q35-Q27
X
X
Q26-Q18
X
X
Q17-Q9
X
C
Q8-Q0
D
(d) ×36 INPUT TO ×9 OUTPUT – BIG ENDIAN
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BE
BM
IW
OW
X
X
X
D
1st: Read from FIFO
2nd: Read from FIFO
3rd: Read from FIFO
4th: Read from FIFO
H
H
L
H
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
X
X
X
C
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
X
Q35-Q27
X
X
Q26-Q18
X
X
Q17-Q9
X
B
Q8-Q0
A
(e) ×36 INPUT TO ×9 OUTPUT – LITTLE ENDIAN
Figure 4. Bus-Matching Byte Arrangement
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
D35-D27
D26-D18
D17-D9
D8-D0
BYTE ORDER ON INPUT PORT:
X
Q35-Q27
X
X
Q26-Q18
X
A
Q17-Q9
C
B
Q8-Q0
D
1st: Write to FIFO
2nd: Write to FIFO
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BYTE ORDER ON OUTPUT PORT:
BE
BM
IW
OW
A
B
C
D
Read from FIFO
Read from FIFO
L
H
H
L
(a) ×18 INPUT TO ×36 OUTPUT – BIG ENDIAN
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BE
BM
IW
OW
C
D
A
B
H
H
H
L
(b) ×18 INPUT TO ×36 OUTPUT – LITTLE ENDIAN
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BYTE ORDER ON INPUT PORT:
X
X
X
A
1st: Write to FIFO
2nd: Write to FIFO
3rd: Write to FIFO
4th: Write to FIFO
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
X
X
X
B
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
X
Q35-Q27
X
X
Q26-Q18
X
X
Q17-Q9
X
C
Q8-Q0
D
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BYTE ORDER ON OUTPUT PORT:
BE
BM
IW
OW
A
B
C
D
Read from FIFO
Read from FIFO
L
H
H
H
(a) ×9 INPUT TO ×36 OUTPUT – BIG ENDIAN
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BE
BM
IW
OW
D
C
B
A
H
H
H
H
(b) ×9 INPUT TO ×36 OUTPUT – LITTLE ENDIAN
Figure 1. Bus-Matching Byte Arrangement (Continued)
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
t
RS
MRS
REN
t
t
t
t
RSS
RSS
RSS
RSR
t
RSR
RSR
WEN
t
FWFT/SI
t
t
RSS
RSS
RSS
RSR
LD
t
FSEL0,
FSEL1
t
BM,
OW,
IW
t
RSS
BE
t
t
t
RSS
RSS
RSS
RM
PFM
IP
t
RSS
RT
t
RSS
SEN
EF/OR
FF/IR
PAE
t
t
t
t
t
RSF
RSF
RSF
RSF
RSF
If FWFT = High, OR = High
If FWFT = Low, EF = Low
If FWFT = Low, FF = High
If FWFT = High, IR = Low
PAF,
HF
OE = High
OE = Low
Q0–Qn
Figure 2. Master Reset Timing
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
t
RS
PRS
REN
t
t
t
RSR
RSS
RSR
t
t
RSS
RSS
WEN
RT
t
RSS
SEN
t
t
t
t
t
If FWFT = High, OR = High
If FWFT = Low, EF = Low
RSF
RSF
RSF
RSF
RSF
EF/OR
FF/IR
If FWFT = Low, FF = High
If FWFT = High, IR = Low
PAE
PAF,
HF
OE = High
OE = Low
Q0–Qn
Figure 3. Partial Reset Timing
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
t
No Write
1
No Write
CLK
t
CLKH
t
CLKH
WCLK
2
1
t
2
t
sk1
t
DS
sk1
(see Note A)
t
DS
t
DH
(see Note A)
t
DH
D0–Dn
Dx
Dx + 1
t
t
t
t
WFF
WFF
WFF
WFF
FF
WEN
RCLK
t
t
t
ENS
t
ENS
ENH
ENH
REN
t
A
t
A
Q0–Qn Data in Output Register
Data Read
Next Data Read
NOTES: A.
t
is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that FF goes high (after one
sk1
WCLK cycle + t
). If the time between the rising edge of the RCLK and the rising edge of the WCLK is less than t
, FF
WFF sk1
deassertion can be delayed one additional WCLK cycle.
B. LD = high, OE = low, EF = high
Figure 4. Write Cycle and Full Flag Timing (Standard Mode)
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
t
CLK
t
CLKH
t
CLKL
RCLK
1
2
t
ENS
t
t
ENS
ENS
t
t
t
ENH
ENH
ENH
No Operation
No Operation
REN
EF
t
ref
t
ref
t
ref
t
A
t
A
t
A
Last Word
Last Word
D0
D1
Q0–Qn
OE
t
t
t
OLZ
OLZ
OHZ
t
OE
t
sk1
(see Note A)
WCLK
WEN
t
ENS
t
ENS
t
t
ENH
ENH
t
t
DS
DS
t
t
DH
DH
D0
D1
D0–Dn
NOTES: A.
t
is the minimum time between a rising WCLK edge and a rising RCLK edge to ensure that EF goes high (after one
sk1
RCLK cycle + t ). If the time between the rising edge of WCLK and the rising edge of RCLK is less than t
be delayed one additional RCLK cycle.
, EF deassertion can
sk1
ref
B. LD = high
C. First-data-word latency: t
+ 1T
+ t
RCLK REF
sk1
Figure 5. Read Cycle, Empty Flag, and First-Data-Word Latency Timing (Standard Mode)
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
WCLK
1
1
2
t
ENS
t
WEN
t
DH
t
t
t
DS
DS
DS
t
ENH
DS
D–1
D–1
D–1
1
2
3
W(D)
W(D-m-2)
W(D-m-1)
W(D-m)
W(D-m+1)
W(D-m+2)
W(D-1)
W(n+2)
W(n+3)
W(n+4)
W
W
W
W1
D0–D17
W2
t
W3
W4
2
2
2
(see Note A)
t
(see Note B)
2
sk1
sk2
RCLK
REN
1
2
3
1
t
A
W1
Q0–Q17
Data in Output Register
t
×
×
×
×
REF
OR
t
PAES
PAE
t
HF
HF
t
PAFS
PAF
IR
t
WFF
NOTES: A.
B.
t
is the minimum time between a rising WCLK edge and a rising RCLK edge to ensure that OR goes low after two RCLK cycles + t
sk1
edge of WLCK and the rising edge of RCLK is less than t
is the minimum time between a rising WCLK edge and a rising RCLK edge to ensure that PAE goes high after one RCLK cycle + t . If the time between the
sk2
rising edge of WCLK and the rising edge of RCLK is less than t
. If the time between the rising
REF
, OR assertion can be delayed one additional RCLK cycle.
sk1
t
PAES
, PAE deassertion can be delayed one additional RCLK cycle.
sk2
C. LD = high, OE = low
D. n = PAE offset, m = PAF offset, D = maximum FIFO depth
E. D = 1025 for the SN74V3640, D = 2049 for the SN74V3650, D = 4097 for the SN74V3660, D = 8193 for the SN74V3670, D = 16385 for the SN74V3680, and D = 32769
for the SN74V3690
×
×
F. First-data-word latency: t
+ 2t
+ t
sk1
RCLK REF
Figure 6. Write Timing (FWFT Mode)
PRODUCT PREVIEW
WCLK
1
2
t
ENH
t
t
sk2
(see Note B)
sk1
(see Note A)
t
ENS
×
×
×
×
WEN
t
DH
t
DS
WD
D0–D17
RCLK
1
2
t
t
ENS
ENS
REN
OE
t
OE
t
t
t
t
t
A
A
A
A
A
t
t
A
OHZ
D–1
D–1
1
2
W(D-n-1)
W(D-n)
W(D-n+1)
W(D-n+2)
W(D-1)
Wm+2
W(m+3)
W(m+4)
W
W
Q0–Q17
W1
W3
WD
W1
W2
2
2
t
REF
OR
t
×
×
PAES
PAE
HF
t
HF
t
PAFS
PAF
IR
t
t
WFF
WFF
NOTES: A.
B.
t
is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that IR goes low after one WCLK cycle + t
, IR assertion may be delayed an additional WCLK cycle.
sk1
is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that PAF to goes high after one WCLK cycle + t
. If the time between the rising
. If the time between the
sk1
WFF
edge of RLCK and the rising edge of WCLK is less than t
t
sk2
rising edge of RCLK and the rising edge of WCLK is less than t
PAFS
, PAF deassertion may be delayed an additional WCLK cycle.
sk2
C. LD = high
D. n = PAE offset, m = PAF offset, D = maximum FIFO depth
E. D = 1025 for the SN74V3640, D = 2049 for the SN74V3650, D = 8193 for the SN74V3670, D = 16385 for the SN74V3680, and D = 32769 for the SN74V3690
Figure 7. Read Timing (FWFT Mode)
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
RCLK
1
2
t
t
RTS
ENS
t
t
ENH
t
ENH
ENS
REN
t
A
t
A
t
A
Q0–Qn
Wx
Wx + 1
sk2
W1 (see Note C)
W2
(see
Note C)
t
1
2
WCLK
WEN
RT
t
RTS
t
ENS
t
ENH
t
REF
t
REF
EF
PAE
HF
t
PAES
t
HF
t
PAFS
PAF
NOTES: A. Retransmit setup is complete after EF returns high; only then can a read operation begin.
B. OE = low
C. W1 = first word written to the FIFO after master reset, W2 = second word written to the FIFO after master reset
D. No more than (D – 2) words may be written to the FIFO between reset (master or partial) and retransmit setup. Therefore, FF is
high throughout the retransmit setup procedure.
D = 1024 for the SN74V3640, D = 2048 for the SN74V3650, D = 4096 for the SN74V3660, D = 8192 for the SN74V3670, D = 16384
for the SN74V3680, and D = 32768 for the SN74V3690.
E. There must be at least two words written to and two words read from the FIFO before a retransmit operation can be invoked.
F. RM is set high during MRS.
Figure 8. Retransmit Timing (Standard Mode)
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
3
1
2
4
RCLK
t
ENS
t
RTS
t
ENH
t
ENS
t
ENH
REN
t
A
t
A
t
A
t
A
Wx
Wx + 1
W1 (see Note D)
W2 (see Note D)
W3 (see Note D)
W4
Q0–Qn
t
sk2
1
2
WCLK
WEN
t
RTS
t
ENS
t
ENH
RT
OR
t
REF
t
REF
t
PAES
PAE
HF
t
HF
t
PAFS
PAF
NOTES: A. Retransmit setup is complete after OR returns low.
B. No more than (D – 2) words can be written to the FIFO between reset (master or partial) and retransmit setup. Therefore, IR is
low throughout the retransmit setup procedure.
D = 1025 for the SN74V3640, D = 2049 for the SN74V3650, D = 4097 for the SN74V3660, D = 8193 for the SN74V3670, D = 16385
for the SN74V3680, and D = 32769 for the SN74V3690.
C. OE = low
D. W1, W2, W3 = first, second, and third words written to the FIFO after master reset
E. There must be at least two words written to the FIFO before a retransmit operation can be invoked.
F. RM is set high during MRS.
Figure 9. Retransmit Timing (FWFT Mode)
34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
1
2
3
RCLK
t
ENS
t
ENH
REN
t
A
t
A
t
A
t
A
t
A
Wx
Wx + 1
W0
W1 (see Note C)
W2 (see Note C)
W3
Q0–Qn
t
sk2
1
2
WCLK
WEN
t
RTS
t
ENH
t
ENS
RT
EF
(see Note A)
t
PAES
PAE
t
HF
HF
t
PAFS
PAF
NOTES: A. If the FIFO is empty at the point of retransmit, EF is updated, based on RCLK (retransmit clock cycle). Valid data appears on the
output.
B. OE = low, enables data to be read on outputs Q0–Qn
C. W1 = first word written to the FIFO after master reset, W2 = second word written to the FIFO after master reset
D. No more than (D – 2) words may be written to the FIFO between reset (master or partial) and retransmit setup. Therefore, FF is
high throughout the retransmit setup procedure.
D = 1024 for the SN74V3640, D = 2048 for the SN74V3650, D = 4096 for the SN74V3660, D = 8192 for the SN74V3670,
D = 16384 for the SN74V3680, D = 32768 for the SN74V3690.
E. At least two words must be written to and read from the FIFO before a retransmit operation can be invoked.
F. RM is set low during MRS.
Figure 10. Zero-Latency Retransmit Timing (Standard Mode)
35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
4
1
2
5
3
RCLK
t
ENH
t
ENS
REN
t
A
t
A
t
A
t
A
t
A
Wx
Wx + 1
W1
W2 (see Note D)
W3 (see Note D)
W4 (see Note D)
W5
Q0–Qn
t
sk2
1
2
WCLK
WEN
t
RTS
t
ENS
t
ENH
RT
OR
t
PAES
PAE
HF
t
HF
t
PAFS
PAF
NOTES: A. If the FIFO is empty at the point of retransmit, OR is updated, based on RCLK (retransmit clock cycle). Valid data also appears
on the output.
B. No more than (D – 2) words may be written to the FIFO between reset (master or partial) and retransmit setup. Therefore, IR is
low throughout the retransmit setup procedure.
D = 1025 for the SN74V3640, D = 2049 for the SN74V3650, D = 4097 for the SN74V3660, and D = 8193 for the SN74V3670,
D = 16385 for the SN74V3680, and D = 32769 for the SN74V3690.
C. OE = low
D. W1, W2, W3 = first, second, and third words written to the FIFO after master reset.
E. There must be at least two words written to the FIFO before a retransmit operation can be invoked.
F. RM is set low during MRS.
Figure 11. Zero-Latency Retransmit Timing (FWFT Mode)
36
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
WCLK
SEN
t
ENS
t
t
ENH
LDH
ENH
t
LDS
t
t
LDH
LD
SI
t
t
DH
DS
Bit 0
Bit x
(see Note A)
Bit 0
Bit x
(see Note A)
Empty Offset
Full Offset
NOTE A: x = 9 for the SN74V3640, x = 10 for the SN74V3650, x = 11 for the SN74V3660, x = 12 for the SN74V3670, x = 13 for the SN74V3680,
x = 14 for the SN74V3690.
Figure 12. Serial Loading of Programmable Flag Registers (FWFT Mode)
t
CLK
t
CLKH
t
CLKL
WCLK
LD
t
LDS
t
t
LDH
t
LDH
t
ENS
ENH
t
t
ENH
WEN
t
DS
t
DH
DH
PAF
Offset
PAE
Offset
D0–D16
NOTE A: This diagram shows programming with an input bus width of 36 bits.
Figure 13. Parallel Loading of Programmable Flag Registers (Standard and FWFT Modes)
37
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
t
CLK
t
CLKH
t
CLKL
RCLK
t
LDS
t
LDH
t
LDH
LD
t
ENS
t
t
ENH
ENH
REN
t
A
t
A
PAE Offset
PAF Offset
Data in Output Register
Q0–Qn
NOTES: A. OE = low
B. This diagram shows reading of offset registers with an output bus width of 36 bits.
Figure 14. Parallel Read of Programmable Flag Registers (Standard and FWFT Modes)
38
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
t
CLKH
t
CLKL
WCLK
1
2
2
1
t
ENS
t
ENH
WEN
PAF
t
t
PAES
PAFS
D – m Words in FIFO
(see Note B)
D – (m + 1) Words in FIFO
(see Note B)
D – (m + 1)
Words in
FIFO (see
Note B)
t
sk2
(see Note C)
RCLK
REN
t
ENS
t
ENH
NOTES: A. m = PAF offset
B. D = maximum FIFO depth
In FWFT mode: D = 1025 for the SN74V3640, D = 2049 for the SN74V3650, D = 4097 for the SN74V3660, and D = 8193 for the
SN74V3670, D = 16385 for the SN74V3680, and D = 32769 for the SN74V3690.
In standard mode: D = 1024 for the SN74V3640, D = 2048 for the SN74V3650, D = 4096 for the SN74V3660, D = 8192 for the
SN74V3670, D = 16384 for the SN74V3680, D = 32768 for the SN74V3690.
C.
t
is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that PAF goes high (after one
sk2
WCLK cycle + t
PAFS
time may be delayed one additional WCLK cycle.
). If the time between the rising edge of RCLK and the rising edge of WCLK is less than t , PAFdeassertion
sk2
D. PAF is asserted and updated on the rising edge of WCLK only.
E. Select this mode by setting PFM high during master reset.
Figure 15. Synchronous Programmable Almost-Full Flag Timing (Standard and FWFT Modes)
39
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
t
CLKH
t
CLKL
WCLK
t
ENS
t
ENH
WEN
PAE
n Words in FIFO (see Note B)
n + 1 Words in FIFO (see Note C)
n Words in FIFO (see Note B)
n + 1 Words in FIFO (see Note C)
n Words in FIFO (see Note B)
n + 1 Words in FIFO (see Note C)
t
sk2
(see Note D)
t
t
PAES
PAES
1
2
1
2
RCLK
REN
t
ENS
t
ENH
NOTES: A. n = PAE offset
B. For standard mode
C. For FWFT mode
D.
t
is the minimum time between a rising WCLK edge and a rising RCLK edge to ensure that PAE goes high (after one
sk2
RCLK cycle + t
PAES
can be delayed one additional RCLK cycle.
). If the time between the rising edge of WCLK and the rising edge of RCLK is less than t , PAEdeassertion
sk2
E. PAE is asserted and updated on the rising edge of WCLK only.
F. Select this mode by setting PFM high during master reset.
Figure 16. Synchronous Programmable Almost-Empty Flag Timing (Standard and FWFT Modes)
40
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
t
CLKH
t
CLKL
WCLK
t
ENS
t
ENH
WEN
PAF
t
PAFA
D – (m + 1) Words in FIFO
D – m Words in FIFO
D – (m + 1) Words in FIFO
t
PAFA
RCLK
t
ENS
REN
NOTES: A. m = PAF offset
B. D = maximum FIFO depth
In FWFT mode: D = 1025 for the SN74V3640, D = 2049 for the SN74V3650, D = 4097 for the SN74V3660, D = 8193 for the
SN74V3670, D = 16385 for the SN74V3680, and D = 32769 for the SN74V3690.
In standard mode: D = 1024 for the SN74V3640, D = 2048 for the SN74V3650, D = 4096 for the SN74V3660, D = 8192 for the
SN74V3670, D = 16384 for the SN74V3680, and D = 32768 for the SN74V3690.
C. PAF is asserted to low on WCLK transition and reset to high on RCLK transition.
D. Select this mode by setting PFM low during master reset.
Figure 17. Asynchronous Programmable Almost-Full Flag Timing (Standard and FWFT Modes)
41
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
t
CLKH
t
CLKL
WCLK
t
ENS
t
ENH
WEN
PAE
n Words in FIFO
(see Note B)
n + 1 Words in FIFO
(see Note C)
t
PAEA
n Words in FIFO (see Note B)
n + 1 Words in FIFO (see Note C)
n + 1 Words in FIFO
(see Note B)
n + 2 Words in FIFO
(see Note C)
t
PAEA
RCLK
REN
t
ENS
NOTES: A. n = PAE offset
B. For standard mode
C. For FWFT mode
D. PAE is asserted low on RCLK transition and reset to high on WCLK transition.
E. Select this mode by setting PFM low during master reset.
Figure 18. Asynchronous Programmable Almost-Empty Flag Timing (Standard and FWFT Modes)
42
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
t
CLKH
t
CLKL
WCLK
t
ENS
t
t
ENH
D
2
WEN
HF
Words in FIFO (see Note A)
HF
D
1
+ 1 Words in FIFO (see Note B)
2
D
2
D
2
Words in FIFO
(see Note A)
Words in FIFO (see Note A)
D
1
+ 1 Words in FIFO (see Note B)
t
HF
D
1
2
+ 1 Words in FIFO
(see Note B)
2
RCLK
t
ENS
REN
NOTES: A. In standard mode: D = maximum FIFO depth. D = 1024 for the SN74V3640, D = 2048 for the SN74V3650, D = 4096 for the
SN74V3660, D = 8192 for the SN74V3670, D = 16384 for the SN74V3680, and D = 32768 for the SN74V3690.
B. In FWFT mode: D = maximum FIFO depth. D = 1025 for the SN74V3640, D = 2049 for the SN74V3650, D = 4097 for the
SN74V3660, D = 8193 for the SN74V3670, D = 16385 for the SN74V3680, and D = 32769 for the SN74V3690.
Figure 19. Half-Full Flag Timing (Standard and FWFT Modes)
43
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
operating configurations
width-expansion configuration
Word width can be increased by connecting the control signals of multiple devices together. Status flags can
be detected from any one device. The exceptions are the EF and FF functions in standard mode and the IR and
OR functions in FWFT mode. Because of variations in skew between RCLK and WCLK, it is possible for EF/FF
deassertion and IR/OR assertion to vary by one cycle between FIFOs. In standard mode, such problems can
be avoided by creating composite flags, that is, ANDing EF of every FIFO and separately ANDing FF of every
FIFO. In FWFT mode, composite flags can be created by ORing OR of every FIFO and separately ORing IR
of every FIFO.
Figure 23 demonstrates a width expansion using two SN74V3640, SN74V3650, SN74V3660, SN74V3670,
SN74V3680, and SN74V3690 devices. D0–D35 from each device form a 72-bit-wide input bus and Q0–Q35
from each device form a 72-bit-wide output bus. Any word width can be attained by adding additional
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, and SN74V3690 devices.
Partial Reset (PRS)
Master Reset (MRS)
First-Word Fall-Through/Serial Input
(FWFT/SI)
Retransmit (RT)
(Dm + 1) – Dn
D0–Dm
m
n
m + n
Data In
Read Clock (RCLK)
Read Enable (REN)
Output Enable (OE)
FIFO 1
FIFO 2
Write Clock (WCLK)
Write Enable (WEN)
Load (LD)
SN74V3640
SN74V3650
SN74V3660
SN74V3670
SN74V3680
SN74V3690
SN74V3640
SN74V3650
SN74V3660
SN74V3670
SN74V3680
SN74V3690
Programmable
Almost-Empty Flag (PAE)
Full Flag/Input Ready 1
(FF/IR)
Empty Flag/Output Ready 1
(EF/OR)
Full Flag/Input Ready 2
(FF/IR)
Gate
Empty Flag/Output Ready 2
(EF/OR)
Gate
Programmable
(see Note A)
Almost-Full Flag (PAF)
(see Note A)
Data Out
n
(Qm + 1) – Qn m + n
Half-Full Flag (HF)
m
Q0–Qm
NOTES: A. Use an OR gate in FWFT mode and an AND gate in standard mode.
B. Do not connect any output control signals together directly.
C. FIFO 1 and FIFO 2 must be the same depth, but can be different word widths.
Figure 20. 1024 × 72, 2048 × 72, 4096 × 72, 8192 × 72, 16384 × 72, 32768 × 72
Width-Expansion Block Diagram
44
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
depth-expansion configuration (FWFT mode only)
The SN74V3640 easily can be adapted to applications requiring depths greater than 1024 for the SN74V3640,
2048 for the SN74V3650, 4096 for the SN74V3660, 8192 for the SN74V3670, 16384 for the SN74V3680, and
32768 for the SN74V3690, with an 18-bit bus width. In FWFT mode, the FIFOs can be connected in series (the
data outputs of one FIFO connected to the data inputs of the next), with no external logic necessary. The
resulting configuration provides a total depth equivalent to the sum of the depths associated with each single
FIFO. Figure 24 shows a depth expansion using two SN74V3640, SN74V3650, SN74V3660, SN74V3670,
SN74V3680, and SN74V3690 devices.
Care should be taken to select FWFT mode during master reset for all FIFOs in the depth-expansion
configuration. The first word written to an empty configuration passes from one FIFO to the next (ripple down)
until it finally appears at the outputs of the last FIFO in the chain. No read operation is necessary, but the RCLK
of each FIFO must be free running. Each time the data word appears at the outputs of one FIFO, that device’s
OR line goes low, enabling a write to the next FIFO in line.
FWFT/SI
Transfer Clock
FWFT/SI
FWFT/SI
Write Clock
Write Enable
Input Ready
Read Clock
WCLK
RCLK
WCLK
RCLK
Read Enable
SN74V3640
SN74V3650
SN74V3660
SN74V3670
SN74V3680
SN74V3690
SN74V3640
SN74V3650
SN74V3660
SN74V3670
SN74V3680
SN74V3690
WEN
IR
OR
WEN
IR
REN
Output Ready
Output Enable
n
Data Out
REN
OE
OR
OE
GND
n
n
Data In
Dn
Qn
Dn
Qn
Figure 21. 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36, 65536 × 36
Depth-Expansion Block Diagram
For an empty-expansion configuration, the amount of time it takes for OR of the last FIFO in the chain to go low
(i.e., valid data to appear on the last FIFO’s outputs) after a word has been written to the first FIFO is the sum
of the delays for each FIFO:
(n–1) (4 transfer clock)
Where:
3tRCLK
(1)
n
= number of FIFOs in the expansion
= RCLK period
t
RCLK
Note that extra cycles should be added for the possibility that the t
and the transfer clock, or RCLK and the transfer clock, for the OR flag.
specification is not met between WCLK
sk1
The ripple-down delay is noticeable only for the first word written to an empty-depth-expansion configuration.
There will be no delay evident for subsequent words written to the configuration.
The first free location created by reading from a full-depth-expansion configuration will bubble up from the last
FIFO to the previous one until, finally, it moves into the first FIFO of the chain. Each time a free location is created
in one FIFO of the chain, that FIFO’s IR line goes low, enabling the preceding FIFO to write a word to fill it.
45
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690
1024 × 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003
depth-expansion configuration (FWFT mode only) (continued)
For a full expansion configuration, the amount of time it takes for IR of the first FIFO in the chain to go low after
a word has been read from the last FIFO is the sum of the delays for each individual FIFO:
(n–1) (3 transfer clock)
2tWCLK
(2)
Where:
n
= number of FIFOs in the expansion
= WCLK period
t
WCLK
Note that extra cycles should be added for the possibility that the t
and the transfer clock, or WCLK and the transfer clock, for the IR flag.
specification is not met between RCLK
sk1
The transfer-clock line should be tied to either WCLK or RCLK, whichever is faster. Both these actions result
in data moving as quickly as possible to the end of the chain and moving free locations to the beginning of the
chain.
46
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
Drawing
PEU
PEU
PEU
PEU
PEU
PEU
PEU
PEU
PEU
PEU
PEU
PEU
PEU
PEU
PEU
PEU
PEU
PEU
PEU
PEU
PEU
PEU
PEU
PEU
SN74V3640-10PEU
SN74V3640-15PEU
SN74V3640-6PEU
SN74V3640-7PEU
SN74V3650-10PEU
SN74V3650-15PEU
SN74V3650-6PEU
SN74V3650-7PEU
SN74V3660-10PEU
SN74V3660-15PEU
SN74V3660-6PEU
SN74V3660-7PEU
SN74V3670-10PEU
SN74V3670-15PEU
SN74V3670-6PEU
SN74V3670-7PEU
SN74V3680-10PEU
SN74V3680-15PEU
SN74V3680-6PEU
SN74V3680-7PEU
SN74V3690-10PEU
SN74V3690-15PEU
SN74V3690-6PEU
SN74V3690-7PEU
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
128
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
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Level-3-220C-168 HR
Level-3-220C-168 HR
Level-3-220C-168 HR
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Level-3-220C-168 HR
Level-3-220C-168 HR
Level-3-220C-168 HR
Level-3-220C-168 HR
Level-3-220C-168 HR
Level-3-220C-168 HR
Level-3-220C-168 HR
Level-3-220C-168 HR
Level-3-220C-168 HR
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Level-3-220C-168 HR
Level-3-220C-168 HR
Level-3-220C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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30-Mar-2005
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPQF058A – JANUARY 1998 – REVISED JUNE 1999
PEU (R-PQFP-G128)
PLASTIC QUAD FLATPACK
0,27
0,17
M
0,08
65
0,50
102
103
64
16,20
15,80
14,20
13,80
12,50 TYP
128
39
1
38
0,13 NOM
18,50 TYP
20,20
19,80
22,20
21,80
Gage Plane
0,25
0,05 MIN
0°–7°
1,45
1,35
0,75
0,45
Seating Plane
0,08
1,60 MAX
4087743/B 10/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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