SN74SSTUB32866NMJR [TI]
25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST;
| 型号： | SN74SSTUB32866NMJR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST 双倍数据速率 |
| 文件： | 总42页 (文件大小：2152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74SSTUB32866
www.ti.com
SCAS792C–OCTOBER 2006–REVISED NOVEMBER 2007
25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
1
FEATURES
•
•
•
Supports SSTL_18 Data Inputs
2
•
Member of the Texas Instruments Widebus+™
Family
Differential Clock (CLK and CLK) Inputs
Supports LVCMOS Switching Levels on the
Control and RESET Inputs
•
•
Pinout Optimizes DDR2 DIMM PCB Layout
Configurable as 25-Bit 1:1 or 14-Bit 1:2
Registered Buffer
•
•
•
Checks Parity on DIMM-Independent Data
Inputs
•
•
Chip-Select Inputs Gate the Data Outputs from
Changing State and Minimizes System Power
Consumption
Able to Cascade with a Second
SN74SSTUB32866
Supports Industrial Temperature Range
(-40°C to 85°C)
Output Edge-Control Circuitry Minimizes
Switching Noise in an Unterminated Line
DESCRIPTION
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. In the
1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout
configuration, two devices per DIMM are required to drive 18 SDRAM loads.
All inputs are SSTL_18, except the reset (RESET) and control (Cn) inputs, which are LVCMOS. All outputs are
edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications, except the
open-drain error (QERR) output.
The SN74SSTUB32866 operates from a differential clock (CLK and CLK). Data are registered at the crossing of
CLK going high and CLK going low.
The SN74SSTUB32866 accepts a parity bit from the memory controller on the parity bit (PAR_IN) input,
compares it with the data received on the DIMM-independent D-inputs (D2–D3, D5–D6, D8–D25 when C0 = 0
and C1 = 0; D2–D3, D5–D6, D8–D14 when C0 = 0 and C1 = 1; or D1-D6, D8-D13 when C0 = 1 and C1 = 1) and
indicates whether a parity error has occurred on the open-drain QERR pin (active low). The convention is even
parity; i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs,
combined with the parity input bit. To calculate parity, all DIMM-independent data inputs must be tied to a known
logic state.
When used as a single device, the C0 and C1 inputs are tied low. In this configuration, parity is checked on the
PAR_IN input signal, which arrives one cycle after the input data to which it applies. Two clock cycles after the
data are registered, the corresponding partial-parity-out (PPO) and QERR signals are generated.
When used in pairs, the C0 input of the first register is tied low, and the C0 input of the second register is tied
high. The C1 input of both registers are tied high. Parity, which arrives one cycle after the data input to which it
applies, is checked on the PAR_IN input signal of the first device. Two clock cycles after the data are registered,
the corresponding PPO and QERR signals are generated on the second device. The PPO output of the first
register is cascaded to the PAR_IN of the second SN74SSTUB32866. The QERR output of the first
SN74SSTUB32866 is left floating, and the valid error information is latched on the QERR output of the second
SN74SSTUB32866.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
SN74SSTUB32866ZKER
SN74SSTUB32866ZWLR
TOP-SIDE MARKING
SB866
LFBGA–ZKE
LFBGA–ZWL
Tape and reel
Tape and reel
-40°C to 85°C
SB866
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
Widebus+ is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2007, Texas Instruments Incorporated
SN74SSTUB32866
www.ti.com
SCAS792C–OCTOBER 2006–REVISED NOVEMBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
If an error occurs and the QERR output is driven low, it stays latched low for a minimum of two clock cycles or
until RESET is driven low. If two or more consecutive parity errors occur, the QERR output is driven low and
latched low for a clock duration equal to the parity-error duration or until RESET is driven low. The
DIMM-dependent signals (DCKE, DCS, DODT, and CSR) are not included in the parity-check computation.
The C0 input controls the pinout configuration of the 1:2 pinout from register-A configuration (when low) to
register-B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to
14-bit 1:2 (when high). C0 and C1 should not be switched during normal operation. They should be hard-wired to
a valid low or high level to configure the register in the desired mode. In the 25-bit 1:1 pinout configuration, the
A6, D6, and H6 terminals are driven low and are do-not-use (DNU) pins.
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CLK and
CLK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register is
cleared, and the data outputs are driven low quickly, relative to the time required to disable the differential input
receivers. However, when coming out of reset, the register becomes active quickly, relative to the time required
to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the
time from the low-to-high transition of RESET until the input receivers are fully enabled, the design of the
SN74SSTUB32866 ensures that the outputs remain low, thus ensuring there will be no glitches on the output.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the
low state during power up.
The device supports low-power standby operation. When RESET is low, the differential input receivers are
disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when
RESET is low, all registers are reset and all outputs are forced low, except QERR. The LVCMOS RESET and Cn
inputs always must be held at a valid logic high or low level.
The device also supports low-power active operation by monitoring both system chip select (DCS and CSR)
inputs and gates the Qn and PPO outputs from changing states when both DCS and CSR inputs are high. If
either DCS or CSR input is low, the Qn and PPO outputs function normally. Also, if the internal low-power signal
(LPS1) is high (one cycle after DCS and CSR go high), the device gates the QERR output from changing states.
If LPS1 is low, the QERR output functions normally. The RESET input has priority over the DCS and CSR control
and, when driven low, forces the Qn and PPO outputs low and forces the QERR output high. If the DCS control
functionality is not desired, the CSR input can be hard-wired to ground, in which case the setup-time requirement
for DCS is the same as for the other D data inputs. To control the low-power mode with DCS only, the CSR input
should be pulled up to VCC through a pullup resistor.
The two VREF pins (A3 and T3) are connected together internally by approximately 150Ω. However, it is
necessary to connect only one of the two VREF pins to the external VREF power supply. An unused VREF pin
should be terminated with a VREF coupling capacitor.
2
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SCAS792C–OCTOBER 2006–REVISED NOVEMBER 2007
PACKAGE
Terminal Assignments for 1:1 Register-A (C0 = 0, C1 = 0)
1
D1 (DCKE)
D2
2
PPO
D15
3
4
5
Q1 (QCKE)
Q2
6
A
B
C
D
E
F
VREF
GND
VCC
VCC
DNU
Q15
Q16
DNU
Q17
Q18
C0
GND
VCC
D3
D16
Q3
D4 (DODT)
D5
QERR
D17
GND
VCC
GND
VCC
Q4 (QODT)
Q5
D6
D18
GND
VCC
GND
VCC
Q6
G
H
J
PAR_IN
CLK
RESET
D7 (DCS)
CSR
D19
C1
GND
VCC
GND
VCC
Q7 (QCS)
NC
DNU
NC
CLK
K
L
D8
GND
VCC
GND
VCC
Q8
Q19
Q20
Q21
Q22
Q23
Q24
Q25
D9
D20
Q9
M
N
P
R
T
D10
D21
GND
VCC
GND
VCC
Q10
D11
D22
Q11
D12
D23
GND
VCC
GND
VCC
Q12
D13
D24
Q13
D14
D25
VREF
VCC
Q14
Each pin name in parentheses indicates the DDR2 DIMM signal name.
DNU - Do not use
NC - No internal connection
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SCAS792C–OCTOBER 2006–REVISED NOVEMBER 2007
Logic Diagram for 1:1 Register Configuration (Positive Logic); C0 = 0, C1 = 0
4
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SCAS792C–OCTOBER 2006–REVISED NOVEMBER 2007
Parity Logic Diagram for 1:1 Register Configuration (Positive Logic); C0 = 0, C1 = 0
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SCAS792C–OCTOBER 2006–REVISED NOVEMBER 2007
PACKAGE
(TOP VIEW)
1
2
PPO
3
4
5
6
A D1 (DCKE)
VREF
GND
VCC
VCC
Q1A (QCKEA) Q1B (QCKEB)
B
C
D2
D3
DNU
GND
VCC
Q2A
Q3A
Q2B
Q3B
DNU
D D4 (DODT)
QERR
DNU
GND
VCC
GND
VCC
Q4A (QODTA) Q4B(QODTB)
E
F
D5
D6
Q5A
Q6A
Q5B
Q6B
DNU
GND
VCC
GND
VCC
G
H
J
PAR_IN
CLK
CLK
D8
RESET
D7 (DCS)
CSR
C1
C0
GND
VCC
GND
VCC
Q7A (QCSA)
NC
Q7B (QCSB)
NC
K
L
DNU
GND
VCC
GND
VCC
Q8A
Q8B
D9
DNU
Q9A
Q9B
M
N
P
R
T
D10
D11
D12
D13
D14
DNU
GND
VCC
GND
VCC
Q10A
Q11A
Q12A
Q13A
Q14A
Q10B
Q11B
Q12B
Q13B
Q14B
DNU
DNU
GND
VCC
GND
VCC
DNU
DNU
VREF
VCC
Each pin name in parentheses indicates the DDR2 DIMM signal name.
DNU - Do not use
NC - No internal connection
6
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SCAS792C–OCTOBER 2006–REVISED NOVEMBER 2007
Logic Diagram for 1:2 Register-A Configuration (Positive Logic); C0 = 0, C1 = 1
Copyright © 2006–2007, Texas Instruments Incorporated
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SCAS792C–OCTOBER 2006–REVISED NOVEMBER 2007
Parity Logic Diagram for 1:2 Register-A Configuration (Positive Logic); C0 = 0, C1 = 1
8
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SCAS792C–OCTOBER 2006–REVISED NOVEMBER 2007
PACKAGE
(TOP VIEW)
Terminal Assignments for 1:2 Register-B (C0 = 1, C1 = 1)
1
D1
2
PPO
3
4
5
Q1A
6
Q1B
A
B
C
D
E
F
VREF
GND
VCC
VCC
D2
DNU
GND
VCC
Q2A
Q2B
D3
DNU
Q3A
Q3B
D4
QERR
DNU
GND
VCC
GND
VCC
Q4A
Q4B
D5
Q5A
Q5B
D6
DNU
GND
VCC
GND
VCC
Q6A
Q6B
G
H
J
PAR_IN
CLK
RESET
D7 (DCS)
CSR
C1
C0
GND
VCC
GND
VCC
Q7A (QCSA)
NC
Q7B (QCSB)
NC
CLK
K
L
D8
DNU
GND
VCC
GND
VCC
Q8A
Q8B
D9
DNU
Q9A
Q9B
M
N
P
R
T
D10
DNU
GND
VCC
GND
VCC
Q10A
Q10B
D11 (DODT)
D12
DNU
Q11A (QODTA) Q11B (QODTB)
DNU
GND
VCC
GND
VCC
Q12A
Q13A
Q12B
Q13B
D13
DNU
D14 (DCKE)
DNU
VREF
VCC
Q14A (QCKEA) Q14B (QCKEB)
Each pin name in parentheses indicates the DDR2 DIMM signal name.
DNU - Do not use
NC - No internal connection
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SCAS792C–OCTOBER 2006–REVISED NOVEMBER 2007
Logic Diagram for 1:2 Register-B Configuration C0 = 1, C1 = 1
10
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SCAS792C–OCTOBER 2006–REVISED NOVEMBER 2007
Parity Logic Diagram for 1:2 Register-B Configuration (Positive Logic); C0 = 1, C1 = 1
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SCAS792C–OCTOBER 2006–REVISED NOVEMBER 2007
TERMINAL FUNCTIONS
TERMINAL
NAME
ELECTRICAL
CHARACTERISTICS
DESCRIPTION
GND
VCC
Ground
Ground input
Power-supply voltage
Input reference voltage
Positive master clock input
Negative master clock input
1.8 V nominal
0.9 V nominal
Differential input
Differential input
LVCMOS inputs
VREF
CLK
CLK
C0, C1
RESET
Configuration control input. Register A or Register B and 1:1 mode or 1:2 mode select.
Asynchronous reset input. Resets registers and disables VREF, data, and clock differential-input
receivers. When RESET is low, all Q outputs are forced low and the QERR output is forced high.
LVCMOS input
D1-D25
CSR, DCS
DODT
Data input. Clocked in on the crossing of the rising edge of CLK and the falling edge of CLK.
Chip select inputs. Disables D1–D25(1) outputs switching when both inputs are high
The outputs of this register bit will not be suspended by the DCS and CSR control.
The outputs of this register bit will not be suspended by the DCS and CSR control.
SSTL_18 inputs
SSTL_18 inputs
SSTL_18 input
SSTL_18 input
DCKE
PAR_IN
Parity input. Arrives one clock cycle after the corresponding data input. Pulldown resistor of typical
150kΩ to GND.
SSTL_18 input
pulldown
Q1–Q25(2)
PPO
Data outputs that are suspended by the DCS and CSR control.
Partial parity out. Indicates odd parity of inputs D1–D25. (1)
Data output that will not be suspended by the DCS and CSR control
Data output that will not be suspended by the DCS and CSR control
Data output that will not be suspended by the DCS and CSR control
Output error bit. Timing is determined by the device mode.
No internal connection
1.8 V CMOS outputs
1.8 V CMOS output
1.8 V CMOS output
1.8 V CMOS output
1.8 V CMOS output
Open-drain output
QCS
QODT
QCKE
QERR
NC
DNU
Do not use. Inputs are in standby-equivalent mode, and outputs are driven low.
(1) Data inputs = D2, D3, D5, D6, D8-D25 when C0 = 0 and C1 = 0
Data inputs = D2, D3, D5, D6, D8-D14 when C0 = 0 and C1 = 1
Data inputs = D1-D6, D8-D10, D12, D13 when C0 = 1 and C1 = 1.D
(2) Data outputs = Q2, Q3, Q5, Q6, Q8-Q25 when C0 = 0 and C1 = 0
Data outputs = Q2, Q3, Q5, Q6, Q8-Q14 when C0 = 0 and C1 = 1
Data outputs = Q1-Q6, Q8-Q10, Q12, Q13 when C0 = 1 and C1 = 1.
FUNCTION TABLE
INPUTS
OUTPUTS
RESET
DCS
L
CSR
X
CLK
CLK
Dn
L
Qn
L
H
H
H
H
H
H
L
↑
↑
↑
↑
↑
↓
L
X
↓
H
L
H
X
L
↓
L
X
L
↓
↓
H
X
H
H
H
Q0
Q0
L
X
X
L or H
L or H
X
X or Floating X or Floating X or Floating X or Floating X or Floating
FUNCTION TABLE
INPUTS
OUTPUTS
RESET
CLK
CLK
DCKE, DCS, DODT QCKE, QCS, QODT
H
H
H
L
↑
↑
↓
↓
H
H
L
L
X
L orH
L orH
Q0
L
X or Floating
X or Floating
X or Floating
12
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SCAS792C–OCTOBER 2006–REVISED NOVEMBER 2007
PARITY AND STANDBY FUNCTION
INPUTS
OUTPUTS
(3)
RESET
CLK
CLK
DCS
CSR
Σ OF INPUTS = H PAR_IN(2) PPO
QERR
D1–D25(1)
Even
Odd
Even
Odd
Even
Odd
Even
Odd
X
H
H
H
H
H
H
H
H
H
H
L
↑
↓
L
L
X
X
L
L
L
H
L
↑
↓
H
↑
↓
L
X
H
H
L
H
L
↑
↓
L
X
L
H
H
L
↑
↓
H
L
L
H
↑
↓
H
L
L
↑
↑
↓
↓
H
L
H
H
X
X
H
L
H
L
L
H
↑
↓
H
H
X
PPO0
PPO0
L
QERR 0
QERR 0
H
L or H
X or
L or H
X or
X
X
X or
X or
X
X or
Floating Floating
Floating Floating
Floating
(1) Data inputs = D2-D3, D5-D6, D8-D25 when C0 = 0 and C1 = 0
Data inputs = D2-D3, D5-D6, D8-D14 when C0 = 0 and C1 = 1
Data inputs = D1-D6, D8-D10, D12, D13 when C0 = 1 and C1 = 1
(2) PAR_IN arrives one clock cycle (C0 = 0) or two clock cycles (C0 = 1) after the data to which it applies.
(3) This transition assumes that QERR is high at the crossing of CLK going high and CLK going low. If
QERR goes low, it stays latched low for a minimum of two clock cycles or until RESET is driven low. If
two or more consecutive parity errors occur, the QERR output is driven low and latched low for a clock
duration equal to the parity duration or until RESET is driven low.
PARITY ERROR DETECT IN LOW-POWER MODE(1)
1:1 MODE
(C0 = 0, C1 = 0)
1:2 REGISTER-A MODE
(C0 = 0, C1 = 1)
1:2 REGISTER-B MODE
(C0 = 1, C1 = 1)
CASCADED MODE
(Registers A and B)
INPUT-DATA
ERROR
OCCURRENCE(2)
PPO
QERR
PPO
QERR
DURATION(3)
PPO
QERR
DURATION(3)
PPO
QERR
DURATION(3)
DURATION(3)
DURATION(3)
DURATION(3)
DURATION(3)
DURATION(3)
n – 4
n – 3
n – 2
n – 1
1 Cycle
2 Cycles
2 Cycles
2 Cycles
1 Cycle
1 Cycle
1 Cycle
2 Cycles
2 Cycles
2 Cycles
1 Cycle
1 Cycle
1 Cycle
2 Cycles
2 Cycles
2 Cycles
1 Cycle
1 Cycle
1 Cycle
2 Cycles
2 Cycles
2 Cycles
1 Cycle
1 Cycle
LPM + 2
Cycles
LPM + 2
Cycles
LPM + 1
Cycle
LPM + 1
Cycle
LPM + 2
Cycles
LPM + 2
Cycles
LPM + 2
Cycles
LPM + 2
Cycles
n
Not detected
Not detected
Not detected
Not detected
Not detected
Not detected
Not detected
Not detected
(1) If a parity error occurs before the device enters the low-power mode (LPM), the behavior of PPO and QERR is dependent on the mode
of the device and the position of the parity error occurrence. This table illustrates the low-power-mode effect on parity detect. The
low-power mode is activated on the n clock cycle when DCS and CSR go high.
(2) The clock-edge position of a one cycle data-input error relative to the clock-edge (n) which initiates LPM at the DCS and CSR inputs.
(3) If an error occurs, then QERR output may be driven low and the PPO output driven high. These columns show the clock duration for
which the PPO signal will be high.
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SCAS792C–OCTOBER 2006–REVISED NOVEMBER 2007
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
–0.5 to 2.5
-0.5 to VCC + 0.5
–0.5 to VCC + 0.5
±50
UNIT
V
VCC
VI
Supply voltage range
Input voltage range(2) (3)
Output voltage range(2) (3)
V
VO
IIK
V
Input clamp current, (VI < 0 or VI > VCC
)
mA
mA
mA
mA
IOK
IO
Output clamp current, (VO < 0 or VO > VCC
Continuous output current (VO = 0 to VCC
Continuous current through each VCC or GND
No airflow
)
±50
)
±50
ICC
±100
39.8
Airflow 150 ft/min
Airflow 250 ft/min
Airflow 500 ft/min
No airflow
34.1
Thermal impedance,
junction-to-ambient(4)
RθJA
33.6
K/W
32.5
RθJC
Tstg
Thermal resistance, junction-to-case(4)
Storage temperature range
14.5
–65 to 150
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) This value is limited to 2.5 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS(1)
MIN
NOM
MAX
1.9
UNIT
V
VCC
VREF
VTT
VI
Supply voltage
1.7
Reference voltage
0.49 × VCC 0.5 × VCC
0.51 × VCC
V
Termination voltage
VREF–40 mV
0
VREF VREF + 40 mV
VCC
V
Input voltage
V
VIH
VIL
AC high-level input voltage
AC low-level input voltage
DC high-level input voltage
DC low-level input voltage
High-level input voltage
Low-level input voltage
Common-mode input voltage range
Peak-to-peak input voltage
High-level output current
Data inputs, CSR, PAR_IN
Data inputs, CSR, PAR_IN
Data inputs, CSR, PAR_IN
Data inputs, CSR, PAR_IN
RESET, Cn
VREF + 250 mV
V
VREF–250 mV
VREF–125 mV
V
VIH
VIL
VREF + 125 mV
V
V
VIH
VIL
0.65 × VCC
V
RESET, Cn
0.35 × VCC
V
VICR
VI(PP)
IOH
CLK, CLK
0.675
600
1.125
V
CLK, CLK
mV
mA
Q outputs, PPO
–8
8
Q outputs, PPO
IOL
TA
Low-level output current
mA
QERR output
30
Operating free-air temperature
-40
85
°C
(1) The RESET and Cn inputs of the device must be held at valid logic voltage levels (not floating) to ensure proper device operation. The
differential inputs must not be floating unless RESET is low. See the TI application report, Implications of Slow or Floating CMOS Inputs
(SCBA004).
14
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SCAS792C–OCTOBER 2006–REVISED NOVEMBER 2007
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
VCC
1.7V to 1.9V
1.7V
MIN TYP(1)
VCC–0.2
MAX
UNIT
VOH
Q outputs, PPO
V
IOH = –6 mA
IOL = 100 µA
IOL = 6 mA
1.3
1.7V to 1.9V
1.7V
0.2
0.4
0.5
-5
Q outputs, PPO
QERR output
PAR_IN
VOL
V
IOL = 25 mA
VI = GND
1.7V
II
VI = VCC
1.9V
25
µA
All other inputs(2)
QERR output
VI = VCC or GND
VO = VCC or GND
RESET = GND
±5
IOZ
ICC
1.9V
1.9V
±10
200
µA
µA
Static standby
IO = 0
RESET = VCC, VI = VIH(AC) or
VIL(AC)
Static operating
40
mA
RESET = VCC, VI = VIH(AC) or
VIL(AC), CLK and CLK switching
50% duty cycle
Dynamic operating – clock
only
45
43
60
45
2
µA/MHz
Dynamic operating – per
each data input, 1:1
configuration
RESET = VCC, VI = VIH(AC) or
VIL(AC), CLK and CLK switching
50% duty cycle, one data input
switching at one-half clock
frequency, 50% duty cycle
ICCD
IO = 0
1.8V
µA clock
MHz/
D input
Dynamic operating – per
each data input, 1:2
configuration
Chip-select-enabled
low-power active mode –
clock only
RESET = VCC, VI = VIH(AC) or
VIL(AC), CLK and CLK switching
50% duty cycle
µA/MHz
Chip-select-enabled
ICCDLP low-power active mode -
1:1 configuration
RESET = VCC, VI = VIH(AC) or
VIL(AC), CLK and CLK switching
50% duty cycle, one data input
switching at one-half clock
frequency, 50% duty cycle
IO = 0
1.8V
1.8V
µA clock
MHz/
D input
Chip-select-enabled
low-power active mode –
1:2 configuration
3
3
Data inputs, CSR, PAR_IN VI = VREF ± 250 mV
2.5
2
3.5
3
CI
CLK, CLK
RESET
VICR = 0.9 V, VI(PP) = 600 mV
VI = VCC or GND
pF
4
(1) All typical values are at VCC = 1.8 V, TA = 25°C.
(2) Each VREF pin (A3 or T3) should be tested independently, with the other (untested) pin open.
Copyright © 2006–2007, Texas Instruments Incorporated
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SCAS792C–OCTOBER 2006–REVISED NOVEMBER 2007
TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2 and
(1)
VCC = 1.8 V ± 0.1 V
UNIT
MIN
MAX
fclock Clock frequency
410
MHz
ns
tw
Pulse duration, CLK, CLK high or low
Differential inputs active time(2)
1
tact
10
15
ns
tinact Differential inputs inactive time(3)
ns
DCS before CLK↑, CLK↓, CSR high; CSR before CLK↑, CLK↓, DCS high
600
500
500
500
400
400
DCS before CLK↑, CLK↓, CSR low
DODT, DCKE, and Data before CLK↑, CLK↓
PAR_IN before CLK↑, CLK↓
tsu
Setup time
Hold time
ps
ps
DCS, DODT, DCKE, and Data after CLK↑, CLK↓
PAR_IN after CLK↑, CLK↓
th
(1) All inputs slew rate is 1 V/ns ± 20%.
(2) VREF must be held at a valid input level, and data inputs must be held low for a minimum time of tact max, after RESET is taken high.
(3) VREF, data, and clock inputs must be held at valid voltage levels (not floating) for a minimum time of tinact max, after RESET is taken low.
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
VCC = 1.8 V ± 0.1 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
See Figure 2
UNIT
MIN
410
0.4
0.6
1.2
1
MAX
fmax
tpdm
tpd
MHz
ns
Production test, See Figure 1
See Figure 5
CLK and CLK
CLK and CLK
Q
0.8
1.6
2.4
2.0
3
PPO
ns
tPLH
tPHL
tRPHL
tRPHL
tRPLH
See Figure 4
CLK and CLK
QERR
ns
(1)
See Figure 2
See Figure 5
See Figure 5
Q
RESET
RESET
ns
ns
PPO
QERR
3
3
(1) Includes 350-ps test-load transmission-line delay.
OUTPUT SLEW RATES
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
VCC = 1.8 V ± 0.1 V
PARAMETER
FROM
TO
UNIT
MIN
1
MAX
dV/dt_r
dV/dt_f
dV/dt_Δ(1)
20%
80%
80%
20%
4
4
1
V/ns
V/ns
V/ns
1
20% or 80%
80% or 20%
(1) Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate).
16
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SCAS792C–OCTOBER 2006–REVISED NOVEMBER 2007
PARAMETER MEASUREMENT INFORMATION
V
/2
CC
V
/2
V
/2
CC
CC
V
/2
V
/2
CC
CC
Figure 1. Output Load For Production Test
PROPAGATION DELAY (Design Goal as per JEDEC Specification)
VCC = 1.8 V ± 0.1 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
(1)
tpdm
CLK and CLK
CLK and CLK
Q
Q
1.1
1.5
1.6
ns
ns
(1)
tpdmss
(1) Includes 350 psi test-load transmission delay line
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SCAS792C–OCTOBER 2006–REVISED NOVEMBER 2007
Figure 2. Data Output Load Circuit and Voltage Waveforms
18
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SCAS792C–OCTOBER 2006–REVISED NOVEMBER 2007
Figure 3. Data Output Slew-Rate Measurement Information
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SCAS792C–OCTOBER 2006–REVISED NOVEMBER 2007
Figure 4. Error Output Load Circuit and Voltage Waveforms
20
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SCAS792C–OCTOBER 2006–REVISED NOVEMBER 2007
Figure 5. Partial-Parity-Out Load Circuit and Voltage Waveforms
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SCAS792C–OCTOBER 2006–REVISED NOVEMBER 2007
APPLICATION INFORMATION
The typical values below are for standard raw cards. Test equipment used was the JEDEC register validation
board using pattern 0x43, 0x4F, and 0x5A.
(1) (2)
Table 1. Raw Card Values
RAW CARD
tpdmss
OVERSHOOT
MIN
MAX
1.6 ns
2.0 ns
2.0 ns
A/F
B/G
C/H
1.2 ns
1.3 ns
1.3 ns
140 mV
430 mV
430 mV
(1) All values are valid under nominal conditions and minimum/maximum of typical signals on one typical
DIMM.
(2) Measurements include all jitter and ISI effects.
SN74SSTUB32866 Used as a Single Device in the 1:1 Register Configuration; C0 = 0, C1 = 0
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SCAS792C–OCTOBER 2006–REVISED NOVEMBER 2007
Timing Diagram for SN74SSTUB32866 Used as a Single Device; C0 = 0, C1 = 0 (RESET
Switches From L to H)
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SCAS792C–OCTOBER 2006–REVISED NOVEMBER 2007
Timing Diagram for SN74SSTUB32866 Used as a Single Device; C0 = 0, C1 = 0 (RESET = H)
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SCAS792C–OCTOBER 2006–REVISED NOVEMBER 2007
Timing Diagram for SN74SSTUB32866 Used as a Single Device; C0 = 0, C1 = 0 (RESET
Switches From = H to L)
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SCAS792C–OCTOBER 2006–REVISED NOVEMBER 2007
SN74SSTUB32866 Used in Pair in the 1:2 Register Configuration
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SCAS792C–OCTOBER 2006–REVISED NOVEMBER 2007
Timing Diagram for the First SN74SSTUB32866 (1:2 Register-A Configuration) Device Used in
Pair; C0 = 0, C1 = 1 (RESET Switches From L to H)
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SCAS792C–OCTOBER 2006–REVISED NOVEMBER 2007
Timing Diagram for the First SN74SSTUB32866 (1:2 Register-A Configuration) Device Used in
Pair; C0 = 0, C1 = 1 (RESET = H)
28
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SCAS792C–OCTOBER 2006–REVISED NOVEMBER 2007
Timing Diagram for the First SN74SSTUB32866 (1:2 Register-A Configuration) Device Used in
Pair; C0 = 0, C1 = 1 (RESET = Switches From H to L)
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SCAS792C–OCTOBER 2006–REVISED NOVEMBER 2007
Timing Diagram for the Second SN74SSTUB32866 (1:2 Register-B Configuration) Device Used
in Pair; C0 = 1, C1 = 1 (RESET = Switches From L to H)
30
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SCAS792C–OCTOBER 2006–REVISED NOVEMBER 2007
Timing Diagram for the Second SN74SSTUB32866 (1:2 Register-B Configuration) Device Used
in Pair; C0 = 1, C1 = 1 (RESET = H)
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SCAS792C–OCTOBER 2006–REVISED NOVEMBER 2007
Timing Diagram for the Second SN74SSTUB32866 (1:2 Register-B Configuration) Device Used
in Pair; C0 = 1, C1 = 1 (RESET = Switches From H to L)
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN74SSTUB32866NMJR
ACTIVE
NFBGA
NMJ
96
1000 RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
SB866
SN74SSTUB32866ZKER
SN74SSTUB32866ZWLR
LIFEBUY
ACTIVE
LFBGA
BGA
ZKE
ZWL
96
96
1000 RoHS & Green
1000 RoHS & Green
SNAGCU
SNAGCU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
SB866
SB866
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Dec-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74SSTUB32866NMJR NFBGA
SN74SSTUB32866ZKER LFBGA
NMJ
ZKE
ZWL
96
96
96
1000
1000
1000
330.0
330.0
330.0
24.4
24.4
24.4
5.7
5.7
5.7
13.7
13.7
13.7
2.0
2.0
2.0
8.0
8.0
8.0
24.0
24.0
24.0
Q1
Q1
Q1
SN74SSTUB32866ZWLR
BGA
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Dec-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74SSTUB32866NMJR
SN74SSTUB32866ZKER
SN74SSTUB32866ZWLR
NFBGA
LFBGA
BGA
NMJ
ZKE
ZWL
96
96
96
1000
1000
1000
350.0
350.0
350.0
350.0
350.0
350.0
43.0
43.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
NMJ0096A
A
5.6
5.4
B
BALL A1 CORNER
13.6
13.4
1.4 MAX
C
SEATING PLANE
0.45
0.35
0.12
C
(0.75) TYP
4 TYP
T
R
P
N
M
L
(0.75) TYP
K
J
SYMM
12
TYP
H
G
F
E
D
C
0.55
0.45
96X Ø
0.15
0.05
C
C
A B
B
A
0.8 TYP
1
2
3
4
5
6
0.8 TYP
SYMM
4225132/A 08/2019
NanoFree is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
NMJ0096A
SYMM
(0.8) TYP
A
B
(0.8) TYP
C
D
E
F
G
H
J
SYMM
K
L
M
N
P
R
T
96X (Ø 0.4)
1
2
3
4
5
6
LAND PATTERN EXAMPLE
SCALE: 8X
0.05 MIN
0.05 MAX
ALL AROUND
ALL AROUND
EXPOSED
METAL
METAL UNDER
SOLDER MASK
(Ø 0.40)
SOLDER MASK
OPENING
(Ø 0.40)
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225132/A 08/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. Refer to Texas Instruments
Literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
NMJ0096A
SYMM
(0.8) TYP
A
B
(0.8) TYP
C
D
E
F
G
H
J
SYMM
K
L
M
N
P
R
T
96X (Ø 0.4)
1
2
3
4
5
6
SOLDER PASTE EXAMPLE
BASED ON 0.150 mm THICK STENCIL
SCALE: 8X
4225132/A 08/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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