SN74LVTH241PWG4 [TI]
3.3-V ABT Octal Buffers/Drivers With 3-State Outputs 20-TSSOP -40 to 85;
| 型号： | SN74LVTH241PWG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V ABT Octal Buffers/Drivers With 3-State Outputs 20-TSSOP -40 to 85 驱动 信息通信管理 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总15页 (文件大小：621K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCAS352K − MARCH 1994 − REVISED OCTOBER 2003
SN54LVTH241 . . . J OR W PACKAGE
SN74LVTH241 . . . DB, DW, NS, OR PW PACKAGE
(TOP VIEW)
D
D
D
D
D
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V
)
CC
Support Unregulated Battery Operation
Down to 2.7 V
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
2OE
1Y1
2A4
1Y2
2A3
1Y3
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
= 3.3 V, T = 25°C
A
I
and Power-Up 3-State Support Hot
off
Insertion
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
13 2A2
12 1Y4
D
D
Latch-Up Performance Exceeds 500 mA Per
JESD 17
11
2A1
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
SN54LVTH241 . . . FK PACKAGE
(TOP VIEW)
description/ordering information
3
2 1 20 19
18
These octal buffers/drivers are designed
1A2
2Y3
1A3
2Y2
1A4
1Y1
2A4
1Y2
2A3
1Y3
4
5
6
7
8
specifically for low-voltage (3.3-V) V
operation,
17
16
15
14
CC
with the capability to provide a TTL interface to a
5-V system environment.
The ’LVTH241 devices are organized as two 4-bit
line drivers with separate output-enable (1OE,
2OE) inputs. When 1OE is low or 2OE is high, the
devices pass noninverted data from the A inputs
to the Y outputs. When 1OE is high or 2OE is low,
the outputs are in the high-impedance state.
9 10 11 12 13
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
ORDERING INFORMATION
ORDERABLE
†
T
PACKAGE
TOP-SIDE MARKING
A
PART NUMBER
SN74LVTH241DW
SN74LVTH241DWR
SN74LVTH241NSR
SN74LVTH241DBR
SN74LVTH241PW
SN74LVTH241PWR
SNJ54LVTH241J
Tube
SOIC − DW
LVTH241
Tape and reel
Tape and reel
Tape and reel
Tube
SOP − NS
LVTH241
LXH241
−40°C to 85°C
SSOP − DB
TSSOP − PW
LXH241
Tape and reel
Tube
CDIP − J
CFP − W
LCCC − FK
SNJ54LVTH241J
SNJ54LVTH241W
SNJ54LVTH241FK
Tube
SNJ54LVTH241W
SNJ54LVTH241FK
−55°C to 125°C
Tube
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCAS352K − MARCH 1994 − REVISED OCTOBER 2003
description/ordering information (continued)
When V
is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
through a pullup resistor
CC
and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by
the current-sinking/current-sourcing capability of the driver.
These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
FUNCTION TABLES
INPUTS
OUTPUT
1Y
1OE
1A
H
L
L
H
L
L
H
X
Z
INPUTS
OUTPUT
2Y
2OE
H
2A
H
H
L
H
L
L
X
Z
logic diagram (positive logic)
1
19
1OE
2OE
2A1
2
18
11
13
15
17
9
7
5
3
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
1A1
4
16
14
12
1A2
2A2
2A3
2A4
6
1A3
8
1A4
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCAS352K − MARCH 1994 − REVISED OCTOBER 2003
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
Voltage range applied to any output in the high state, V (see Note 1) . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Current into any output in the low state, I : SN54LVTH241 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74LVTH241 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, I (see Note 2): SN54LVTH241 . . . . . . . . . . . . . . . . . . . . . . . 48 mA
O
SN74LVTH241 . . . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
O
Package thermal impedance, θ (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V > V
.
CC
O
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
SN54LVTH241 SN74LVTH241
UNIT
MIN
2.7
2
MAX
MIN
2.7
2
MAX
V
V
V
V
Supply voltage
3.6
3.6
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
5.5
−24
48
0.8
5.5
−32
64
V
IL
V
I
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
mA
mA
ns/V
µs/V
°C
OH
OL
∆t/∆v
∆t/∆V
Outputs enabled
10
10
200
−55
200
−40
CC
T
A
Operating free-air temperature
125
85
NOTE 4: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
CC
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3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCAS352K − MARCH 1994 − REVISED OCTOBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVTH241
SN74LVTH241
PARAMETER
TEST CONDITIONS
I = −18 mA
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
V
= 2.7 V,
−1.2
−1.2
V
IK
CC
CC
CC
I
= 2.7 V to 3.6 V,
= 2.7 V,
I
I
I
I
I
I
I
I
I
I
= −100 µA
= −8 mA
= −24 mA
= −32 mA
= 100 µA
= 24 mA
= 16 mA
= 32 mA
= 48 mA
= 64 mA
V
−0.2
CC
2.4
V
−0.2
CC
2.4
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
V
V
OH
2
V
= 3 V
CC
CC
2
0.2
0.5
0.2
0.5
0.4
0.5
V
= 2.7 V
0.4
V
OL
0.5
V
CC
= 3 V
0.55
0.55
10
1
V
V
= 0 or 3.6 V,
= 3.6 V,
V = 5.5 V
10
1
CC
I
Control inputs
V = V
or GND
CC
I
CC
I
I
I
µA
µA
µA
I
V = V
1
1
I
CC
Data inputs
V
V
= 3.6 V
= 0,
CC
V = 0
I
−5
−5
100
V or V = 0 to 4.5 V
I
off
CC
O
V = 0.8 V
I
75
75
V
CC
V
CC
= 3 V
V = 2 V
I
−75
−75
Data inputs
I(hold)
500
−750
‡
= 3.6 V ,
V = 0 to 3.6 V
I
I
I
V
V
V
= 3.6 V,
= 3.6 V,
V
V
= 3 V
5
5
µA
µA
OZH
CC
CC
CC
O
= 0.5 V
−5
−5
OZL
O
= 0 to 1.5 V, V = 0.5 V to 3 V,
O
∗
100
100
100
100
µA
µA
I
OZPU
OZPD
OE/OE = don’t care
V
= 1.5 V to 0, V = 0.5 V to 3 V,
CC
OE/OE = don’t care
O
∗
I
Outputs high
Outputs low
0.19
5
0.19
5
V
I
= 3.6 V,
CC
= 0,
I
mA
mA
O
CC
V = V
I
or GND
CC
Outputs disabled
0.19
0.19
V
= 3 V to 3.6 V, One input at V − 0.6 V,
CC
CC
Other inputs at V
§
0.2
0.2
∆I
CC
or GND
CC
C
C
V = 3 V or 0
3
7
3
7
pF
pF
i
I
V
O
= 3 V or 0
o
∗
†
‡
§
On products compliant to MIL-PRF-38535, this parameter is not production tested.
All typical values are at V = 3.3 V, T = 25°C.
CC
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V or GND.
A
CC
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ꢞ
ꢨ
ꢞ
ꢢ
ꢧ
ꢜ
ꢞ
ꢡ
ꢦ
ꢟ
ꢧ
ꢩ
ꢥ
ꢠ
ꢥ
ꢟ
ꢞ
ꢰ
ꢦ
ꢰ
ꢡ
ꢧ
ꢬ
ꢟ
ꢍ
ꢆ
ꢥ
ꢭ
ꢧ
ꢟ
ꢙ
ꢦ
ꢟ
ꢜ
ꢩ
ꢣ
ꢤ
ꢥ
ꢦ
ꢢ ꢝ ꢧ ꢦ ꢰꢥ ꢡꢩ ꢠꢞ ꢟ ꢢ ꢡꢦ ꢜꢞ ꢦꢣ ꢥ ꢜ ꢝꢥ ꢟ ꢥ ꢪꢩ ꢡ ꢠꢣꢢ ꢜꢟ ꢮ ꢞꢜꢝ ꢡꢣꢜ ꢦꢡꢜ ꢞꢢꢥ ꢍ
ꢜ
ꢟ
ꢩ
ꢥ
ꢟ
ꢥ
ꢩ
ꢱ
ꢥ
ꢟ
ꢜ
ꢝ
ꢥ
ꢩ
ꢞ
ꢰ
ꢝ
ꢜ
ꢜ
ꢡ
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢃ
ꢉ
ꢊ
ꢀ
ꢁ
ꢋ
ꢃ
ꢌ ꢍꢌ ꢎꢅ ꢏꢐꢆ ꢑ ꢒꢆꢏꢄ ꢐꢓꢔ ꢔ ꢕꢖꢀꢗ ꢘ ꢖꢙ ꢅ ꢕꢖ
ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢃ
ꢉ
ꢀ
ꢀ
ꢚ
ꢙ
ꢆ
ꢇ
ꢌ
ꢎ
ꢀ
ꢆ
ꢏ
ꢆ
ꢕ
ꢑ
ꢓ
ꢆ
ꢛ
ꢓ
ꢆ
SCAS352K − MARCH 1994 − REVISED OCTOBER 2003
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature range, C = 50 pF (unless otherwise noted) (see Figure 1)
L
SN54LVTH241
SN74LVTH241
= 3.3 V
V
= 3.3 V
V
FROM
(INPUT)
TO
(OUTPUT)
CC
0.3 V
CC
0.3 V
V
CC
= 2.7 V
V
= 2.7 V
PARAMETER
UNIT
CC
†
MIN
MAX
3.7
3.5
4.6
4.6
4.7
5
MIN
MAX
4
MIN TYP
MAX
3.5
3.4
4.5
4.4
4.5
4.7
MIN
MAX
3.9
3.6
5.4
5
t
t
t
t
t
t
1
1.2
1
1.1
1.3
1.1
1.4
1.6
1.8
2.3
2.2
2.7
2.9
2.8
3
PLH
PHL
PZH
PZL
PHZ
PLZ
A
Y
Y
Y
ns
ns
ns
3.7
5.5
5.1
5.5
5.5
OE or OE
OE or OE
1.3
1.5
1.7
5.3
5.2
†
All typical values are at V
CC
= 3.3 V, T = 25°C.
A
ꢛ
ꢖ
ꢑ
ꢘ
ꢓ
ꢒ
ꢆ
ꢛ
ꢖ
ꢕ
ꢅ
ꢙ
ꢕ
ꢚ
ꢞ
ꢦ
ꢨ
ꢡ
ꢩ
ꢤ
ꢧ
ꢜ
ꢞ
ꢡ
ꢦ
ꢢ
ꢡ
ꢦ
ꢢ
ꢥ
ꢩ
ꢦ
ꢟ
ꢪ
ꢩ
ꢡ
ꢠ
ꢣ
ꢠꢥ ꢟ ꢞ ꢰꢦ ꢪꢝ ꢧ ꢟ ꢥ ꢡꢨ ꢠꢥ ꢱ ꢥ ꢬꢡ ꢪꢤꢥ ꢦꢜꢍ ꢒ ꢝꢧ ꢩꢧ ꢢꢜ ꢥꢩ ꢞꢟ ꢜꢞ ꢢ ꢠꢧ ꢜꢧ ꢧꢦ ꢠ ꢡꢜ ꢝꢥꢩ
ꢢ
ꢜ
ꢟ
ꢞ
ꢦ
ꢜ
ꢝ
ꢥ
ꢨ
ꢡ
ꢩ
ꢤ
ꢧ
ꢜ
ꢞ
ꢱ
ꢥ
ꢡ
ꢩ
ꢟ
ꢪ
ꢥ
ꢢ
ꢞ
ꢨ
ꢞ
ꢢ
ꢧ
ꢜ
ꢞ
ꢡ
ꢦ
ꢟ
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ꢩ
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ꢠ
ꢥ
ꢟ
ꢞ
ꢰ
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ꢰ
ꢡ
ꢧ
ꢬ
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ꢍ
ꢆ
ꢥ
ꢭ
ꢧ
ꢟ
ꢙ
ꢦ
ꢟ
ꢜ
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ꢣ
ꢤ
ꢥ
ꢦ
ꢢ ꢝꢧ ꢦ ꢰꢥ ꢡꢩ ꢠꢞ ꢟ ꢢ ꢡꢦ ꢜꢞ ꢦꢣꢥ ꢜ ꢝꢥ ꢟ ꢥ ꢪꢩ ꢡꢠ ꢣꢢꢜ ꢟ ꢮ ꢞꢜꢝ ꢡꢣꢜ ꢦꢡꢜ ꢞꢢꢥ ꢍ
ꢜ
ꢟ
ꢩ
ꢥ
ꢟ
ꢥ
ꢩ
ꢱ
ꢥ
ꢟ
ꢜ
ꢝ
ꢥ
ꢩ
ꢞ
ꢰ
ꢝ
ꢜ
ꢜ
ꢡ
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢃꢄꢅ
ꢆ
ꢇ
ꢈ
ꢃ
ꢉ
ꢊ
ꢀ
ꢁ
ꢋ
ꢃ
ꢄꢅ
ꢆ
ꢇ
ꢈꢃ
ꢉ
ꢌ
ꢍ
ꢌ
ꢎ
ꢅ
ꢏ
ꢐꢆ
ꢑ
ꢒ
ꢆꢏ
ꢄ
ꢐ
ꢓ
ꢔ
ꢔ
ꢕꢖ
ꢀꢗ
ꢘ
ꢖ
ꢙ
ꢅ
ꢕꢖ
ꢀ
ꢚ
ꢙ
ꢆ
ꢇ
ꢌ
ꢎ
ꢀ
ꢆ
ꢏ
ꢆ
ꢕ
ꢑ
ꢓ
ꢆ
ꢛ
ꢓ
ꢆ
ꢀ
SCAS352K − MARCH 1994 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
6 V
TEST
/t
S1
S1
Open
GND
500 Ω
From Output
Under Test
t
Open
6 V
PLH PHL
t
/t
PLZ PZL
C
= 50 pF
L
t
/t
GND
500 Ω
PHZ PZH
(see Note A)
2.7 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
2.7 V
0 V
2.7 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
t
PLZ
PZL
t
t
t
PHL
PLH
Output
Waveform 1
S1 at 6 V
3 V
V
V
OH
1.5 V
1.5 V
1.5 V
1.5 V
t
Output
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
t
PZH
PHZ
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
− 0.3 V
OH
1.5 V
1.5 V
Output
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
SN74LVTH241DBR
SN74LVTH241DW
SN74LVTH241DWR
SN74LVTH241DWRG4
SN74LVTH241PW
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SSOP
SOIC
DB
20
20
20
20
20
20
20
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
LXH241
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DW
DW
DW
PW
PW
PW
PW
25
2000
2000
70
Green (RoHS
& no Sb/Br)
LVTH241
LVTH241
LVTH241
LXH241
LXH241
LXH241
LXH241
SOIC
Green (RoHS
& no Sb/Br)
SOIC
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
Green (RoHS
& no Sb/Br)
SN74LVTH241PWE4
SN74LVTH241PWG4
SN74LVTH241PWR
70
Green (RoHS
& no Sb/Br)
70
Green (RoHS
& no Sb/Br)
2000
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVTH241 :
Enhanced Product: SN74LVTH241-EP
•
NOTE: Qualified Version Definitions:
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVTH241DBR
SN74LVTH241DWR
SN74LVTH241PWR
SSOP
SOIC
DB
DW
PW
20
20
20
2000
2000
2000
330.0
330.0
330.0
16.4
24.4
16.4
8.2
7.5
13.0
7.1
2.5
2.7
1.6
12.0
12.0
8.0
16.0
24.0
16.0
Q1
Q1
Q1
10.8
6.95
TSSOP
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LVTH241DBR
SN74LVTH241DWR
SN74LVTH241PWR
SSOP
SOIC
DB
DW
PW
20
20
20
2000
2000
2000
367.0
367.0
367.0
367.0
367.0
367.0
38.0
45.0
38.0
TSSOP
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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