SN74LVTH125IPWREP [TI]

3.3-V ABT QUADRUPLE BUS BUFFER WITH 3-STATE OUTPUTS;
SN74LVTH125IPWREP
型号: SN74LVTH125IPWREP
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

3.3-V ABT QUADRUPLE BUS BUFFER WITH 3-STATE OUTPUTS

驱动 光电二极管 输出元件 逻辑集成电路
文件: 总9页 (文件大小:431K)
中文:  中文翻译
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ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢊꢋ ꢌꢍ  
ꢎ ꢏꢎ ꢋꢅ ꢐꢑꢆ ꢒ ꢓꢐꢔꢕ ꢓꢍꢄ ꢌ ꢑꢓꢀ ꢑ ꢓꢖ ꢖꢌ ꢕ  
ꢗ ꢘꢆ ꢇ ꢎ ꢋꢀꢆꢐꢆ ꢌ ꢙ ꢓꢆ ꢍ ꢓꢆꢀ  
SCBS765 − NOVEMBER 2003  
D
D
Controlled Baseline  
− One Assembly/Test Site, One Fabrication  
Site  
D
D
I
and Power-Up 3-State Support Hot  
off  
Insertion  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
D
D
D
Enhanced Product-Change Notification  
D
D
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
Qualification Pedigree  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
Supports Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
3.3-V V  
)
CC  
D
D
Supports Unregulated Battery Operation  
Down to 2.7 V  
PW PACKAGE  
(TOP VIEW)  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
= 3.3 V, T = 25°C  
1OE  
1A  
1Y  
2OE  
2A  
2Y  
V
CC  
4OE  
CC  
A
Component qualification in accordance with JEDEC and industry  
standards to ensure reliable operation over an extended  
temperature range. This includes, but is not limited to, Highly  
Accelerated Stress Test (HAST) or biased 85/85, temperature  
cycle, autoclave or unbiased HAST, electromigration, bond  
intermetallic life, and mold compound life. Such qualification  
testing should not be viewed as justifying use of this component  
beyond specified performance and environmental limits.  
4A  
4Y  
3OE  
3A  
3Y  
8
GND  
description/ordering information  
This bus buffer is designed specifically for low-voltage (3.3-V) V  
a TTL interface to a 5-V system environment.  
operation, but with the capability to provide  
CC  
The SN74LVTH125 features independent line drivers with 3-state outputs. Each output is in the high-impedance  
state when the associated output-enable (OE) input is high.  
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors  
with the bus-hold circuitry is not recommended.  
When V  
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.  
CC  
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup resistor;  
CC  
This device is fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry  
off  
off  
disables the outputs, preventing damaging current backflow through the device when it is powered down. The  
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,  
which prevents driver conflict.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
T
A
PACKAGE  
−40°C to 85°C  
TSSOP − PW Tape and reel  
SN74LVTH125IPWREP  
LH125EP  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢆꢦ  
Copyright 2003, Texas Instruments Incorporated  
ꢢ ꢦ ꢣ ꢢꢛ ꢜꢯ ꢞꢝ ꢡ ꢩꢩ ꢧꢡ ꢟ ꢡ ꢠ ꢦ ꢢ ꢦ ꢟ ꢣ ꢏ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
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ꢎꢏ ꢎꢋꢅ ꢐ ꢑꢆ ꢒꢓ ꢐ ꢔꢕ ꢓꢍ ꢄꢌ ꢑꢓ ꢀ ꢑꢓ ꢖꢖ ꢌꢕ  
ꢗꢘ ꢆ ꢇ ꢎ ꢋꢀꢆꢐꢆ ꢌ ꢙꢓꢆ ꢍ ꢓꢆꢀ  
SCBS765 − NOVEMBER 2003  
FUNCTION TABLE  
(each buffer)  
INPUTS  
OUTPUT  
Y
OE  
A
H
L
L
L
H
L
H
X
Z
logic diagram (positive logic)  
1
10  
1OE  
3OE  
3A  
2
3
9
8
1A  
1Y  
2Y  
3Y  
4Y  
4
13  
12  
2OE  
4OE  
4A  
5
6
11  
2A  
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
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SCBS765 − NOVEMBER 2003  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage range, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V  
CC  
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V  
I
Voltage range applied to any output in the high-impedance  
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V  
O
Voltage range applied to any output in the high state, V (see Note 1) . . . . . . . . . . . . . −0.5 V to V  
+ 0.5 V  
O
CC  
Current into any output in the low state, I  
Current into any output in the high state, I (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA  
O
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA  
IK  
OK  
I
Output clamp current, I  
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA  
O
Package thermal impedance, θ (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W  
JA  
stg  
Storage temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.  
2. This current flows only when the output is in the high state and V > V  
.
CC  
O
3. The package thermal impedance is calculated in accordance with JESD 51-7.  
recommended operating conditions (see Note 4)  
MIN  
2.7  
2
MAX  
UNIT  
V
V
V
V
V
Supply voltage  
3.6  
CC  
High-level input voltage  
Low-level input voltage  
Input voltage  
V
IH  
0.8  
5.5  
−32  
64  
V
IL  
V
I
I
I
High-level output current  
Low-level output current  
Input transition rise or fall rate  
Power-up ramp rate  
mA  
mA  
ns/V  
µs/V  
°C  
OH  
OL  
t/v  
t/V  
Outputs enabled  
10  
200  
−40  
CC  
T
A
Operating free-air temperature  
85  
NOTE 4: All unused control inputs of the device must be held at V  
or GND to ensure proper device operation. Refer to the TI application report,  
CC  
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.  
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢊꢋꢌꢍ  
ꢎꢏ ꢎꢋꢅ ꢐ ꢑꢆ ꢒꢓ ꢐ ꢔꢕ ꢓꢍ ꢄꢌ ꢑꢓ ꢀ ꢑꢓ ꢖꢖ ꢌꢕ  
ꢗꢘ ꢆ ꢇ ꢎ ꢋꢀꢆꢐꢆ ꢌ ꢙꢓꢆ ꢍ ꢓꢆꢀ  
SCBS765 − NOVEMBER 2003  
electrical characteristics over recommended operating free-air temperature range (unless  
otherwise noted)  
TYP  
PARAMETER  
TEST CONDITIONS  
MIN  
MAX  
UNIT  
V
V
V
V
V
= 2.7 V,  
I = −18 mA  
−1.2  
V
IK  
CC  
CC  
CC  
CC  
I
= 2.7 V to 3.6 V,  
= 2.7 V,  
I
I
I
I
I
I
I
I
= −100 µA  
= −8 mA  
= −32 mA  
= 100 µA  
= 24 mA  
= 16 mA  
= 32 mA  
= 64 mA  
V
−0.2  
OH  
OH  
OH  
OL  
OL  
OL  
OL  
OL  
CC  
2.4  
2
V
OH  
V
V
= 3 V,  
0.2  
0.5  
0.4  
0.5  
0.55  
10  
V
= 2.7 V  
CC  
CC  
V
OL  
V
= 3 V  
V
V
= 0 or 3.6 V,  
= 3.6 V,  
V = 5.5 V  
I
CC  
Control  
inputs  
V = V  
or GND  
1
CC  
I
CC  
I
I
µA  
V = V  
1
−5  
I
CC  
Data inputs  
V
V
= 3.6 V  
= 0,  
CC  
V = 0  
I
I
I
V or V = 0 to 4.5 V  
I
100  
µA  
µA  
off  
CC  
O
V = 0.8 V  
I
75  
V
CC  
= 3 V  
V = 2 V  
I
−75  
Data inputs  
I(hold)  
V
CC  
V
CC  
V
CC  
V
CC  
= 3.6 V ,  
V = 0 to 3.6 V  
500  
5
I
I
I
I
= 3.6 V,  
= 3.6 V,  
V
= 3 V  
µA  
µA  
µA  
OZH  
O
O
V
= 0.5 V  
−5  
50  
OZL  
= 0 to 1.5 V, V = 0.5 V to 3 V, OE = don’t care  
O
OZPU  
V
= 1.5 V to 0, V = 0.5 V to 3 V, OE = don’t care  
O
50  
0.19  
7
µA  
I
CC  
OZPD  
Outputs high  
Outputs low  
0.12  
4.5  
I
V
= 3.6 V, I = 0, V = V  
CC  
or GND  
mA  
CC  
§
CC  
CC  
O
I
Outputs disabled  
0.12  
0.19  
0.2  
V
= 3 V to 3.6 V, One input at V  
CC  
− 0.6 V, Other inputs at V  
or GND  
mA  
pF  
pF  
I  
CC  
CC  
C
C
V = 3 V or 0  
I
4
i
V
O
= 3 V or 0  
6.5  
o
§
All typical values are at V  
= 3.3 V, T = 25°C.  
A
CC  
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.  
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V  
or GND.  
CC  
switching characteristics over recommended operating free-air temperature range, C = 50 pF  
L
(unless otherwise noted) (see Figure 1)  
V
= 3.3 V  
CC  
0.3 V  
V
= 2.7 V  
CC  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
UNIT  
MIN TYP  
MAX  
3.5  
3.9  
4
MIN  
MAX  
4.5  
4.9  
5.5  
5.4  
5.7  
4
t
t
t
t
t
t
1
2
PLH  
PHL  
PZH  
PZL  
PHZ  
PLZ  
A
Y
Y
Y
ns  
ns  
ns  
1
1
2.1  
2
OE  
OE  
1.1  
1.5  
1.3  
2.1  
2.3  
2.8  
4
4.5  
4.5  
4
All typical values are at V  
CC  
= 3.3 V, T = 25°C.  
A
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
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ꢗ ꢘꢆ ꢇ ꢎ ꢋꢀꢆꢐꢆ ꢌ ꢙ ꢓꢆ ꢍ ꢓꢆꢀ  
SCBS765 − NOVEMBER 2003  
PARAMETER MEASUREMENT INFORMATION  
6 V  
TEST  
S1  
Open  
GND  
S1  
500 Ω  
From Output  
Under Test  
t
/t  
Open  
6 V  
PLH PHL  
/t  
t
PLZ PZL  
/t  
C
= 50 pF  
L
t
GND  
PHZ PZH  
500 Ω  
(see Note A)  
2.7 V  
0 V  
LOAD CIRCUIT  
Timing Input  
Data Input  
1.5 V  
t
w
t
t
h
su  
2.7 V  
2.7 V  
0 V  
1.5 V  
1.5 V  
Input  
1.5 V  
1.5 V  
0 V  
VOLTAGE WAVEFORMS  
PULSE DURATION  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
2.7 V  
0 V  
2.7 V  
Output  
Control  
1.5 V  
1.5 V  
1.5 V  
1.5 V  
Input  
0 V  
V
t
t
PLZ  
PZL  
t
t
t
PHL  
PLH  
Output  
Waveform 1  
S1 at 6 V  
3 V  
OH  
1.5 V  
1.5 V  
1.5 V  
t
1.5 V  
Output  
V
V
+ 0.3 V  
OL  
V
OL  
(see Note B)  
V
OL  
t
t
PZH  
PHZ  
PHL  
PLH  
Output  
Waveform 2  
S1 at GND  
V
OH  
V
V
OH  
− 0.3 V  
OH  
1.5 V  
1.5 V  
Output  
0 V  
(see Note B)  
OL  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
INVERTING AND NONINVERTING OUTPUTS  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
LOW- AND HIGH-LEVEL ENABLING  
NOTES: A. includes probe and jig capacitance.  
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 , t 2.5 ns, t 2.5 ns.  
O
r
f
D. The outputs are measured one at a time with one transition per measurement.  
E. All parameters and waveforms are not applicable to all devices.  
Figure 1. Load Circuit and Voltage Waveforms  
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
PACKAGE OPTION ADDENDUM  
www.ti.com  
18-Sep-2008  
PACKAGING INFORMATION  
Orderable Device  
SN74LVTH125IPWREP  
V62/04671-01XE  
Status (1)  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
TSSOP  
PW  
14  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TSSOP  
PW  
14  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
OTHER QUALIFIED VERSIONS OF SN74LVTH125-EP :  
Catalog: SN74LVTH125  
NOTE: Qualified Version Definitions:  
Catalog - TI's standard catalog product  
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
14-Jul-2012  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
SN74LVTH125IPWREP TSSOP  
PW  
14  
2000  
330.0  
12.4  
6.9  
5.6  
1.6  
8.0  
12.0  
Q1  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
14-Jul-2012  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
TSSOP PW 14  
SPQ  
Length (mm) Width (mm) Height (mm)  
367.0 367.0 35.0  
SN74LVTH125IPWREP  
2000  
Pack Materials-Page 2  
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