SN74LVT16646DLR_技术文档

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SCBS149D − JULY 1994 − REVISED MARCH 2004

SN54LVT16646 . . . WD PACKAGE

SN74LVT16646 . . . DGG OR DL PACKAGE

(TOP VIEW)

D

Members of the Texas Instruments

Widebus Family

State-of-the-Art Advanced BiCMOS

Technology (ABT) Design for 3.3-V

Operation and Low-Static Power

Dissipation

1

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

1DIR

1CLKAB

1SAB

GND

1OE

2

1CLKBA

1SBA

GND

1B1

3

D

Support Mixed-Mode Signal Operation (5-V

Input and Output Voltages With 3.3-V V

4

)

5

1A1

1A2

CC

6

1B2

Support Unregulated Battery Operation

Down to 2.7 V

7

V

CC

8

1A3

1A4

1A5

GND

1A6

1A7

1A8

2A1

2A2

2A3

GND

2A4

2A5

2A6

1B3

1B4

1B5

GND

1B6

1B7

1B8

2B1

2B2

2B3

GND

2B4

2B5

2B6

Typical V

<0.8 V at V

(Output Ground Bounce)

OLP

CC

9

= 3.3 V, T = 25°C

A

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

Bus-Hold Data Inputs Eliminate the Need

for External Pullup Resistors

I

and Power-Up 3-State Support Hot

off

Insertion

Distributed V

Minimizes High-Speed Switching Noise

and GND Pin Configuration

CC

Flowthrough Architecture Optimizes

PCB Layout

Latch-Up Performance Exceeds 500 mA

Per JEDEC Standard JESD-17

ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

V

CC

2A7

2A8

GND

2B7

2B8

GND

2SBA

2CLKBA

2OE

description/ordering information

2SAB

2CLKAB

2DIR

The ’LVT16646 devices are 16-bit bus

transceivers and registers designed for

low-voltage (3.3-V) V

operation, but with the

CC

capability to provide a TTL interface to a 5-V

system environment.

These devices can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is clocked

into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1

illustrates the four fundamental bus-management functions that can be performed with the ′LVT16646 devices.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

T

A

Tube

SN74LVT16646DL

SSOP − DL

LVT16646

Tape and reel

SN74LVT16646DLR

SN74LVT16646DGGR

SNJ54LVT16646WD

−40°C to 85°C

−55°C to 125°C

TSSOP − DGG Tape and reel

CFP − WD Tube

LVT16646

SNJ54LVT16646WD

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available

at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments.

Copyright  2004, Texas Instruments Incorporated

ꢑ ꢁ ꢄꢔꢀꢀ ꢙ ꢆꢘ ꢔꢒꢗ ꢐꢀ ꢔ ꢁ ꢙꢆꢔꢕ ꢛꢜ ꢝꢞ ꢟꢠꢡ ꢢꢣꢤ ꢥꢛ ꢡꢠ ꢥꢛꢦ ꢝꢥꢞ ꢚꢒ ꢙ ꢕ ꢑ ꢓꢆ ꢐꢙ ꢁ

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1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢈꢃ ꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢈ ꢃꢈ

ꢋꢌ ꢋꢍꢅ ꢎ ꢏꢆ ꢇ ꢈꢍ ꢏꢐ ꢆ ꢏꢑ ꢀ ꢆꢒ ꢎꢁ ꢀꢓ ꢔꢐ ꢅ ꢔ ꢒꢀ ꢎꢁꢕ ꢒꢔ ꢖꢐ ꢀꢆ ꢔꢒꢀ

ꢗꢐ ꢆ ꢘ ꢋ ꢍꢀꢆꢎꢆ ꢔ ꢙꢑꢆ ꢚꢑ ꢆꢀ

SCBS149D − JULY 1994 − REVISED MARCH 2004

description/ordering information (continued)

Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the

transceiver mode, data present at the high-impedance port may be stored in either register or in both. The

select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry

used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition

between stored and real-time data. The direction control (DIR) determines which bus receives data when OE

is low. In the isolation mode (OE high), A data may be stored in one register and/or B data may be stored in the

other register.

When an output function is disabled, the input function is still enabled and may be used to store and transmit

data. Only one of the two buses, A or B, may be driven at a time.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors

with the bus-hold circuitry is not recommended.

These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry

off

disables the outputs, preventing damaging current backflow through the devices when they are powered down.

The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,

which prevents driver conflict.

To ensure the high-impedance state during power up or power down, OE should be tied to V

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

through a pullup

CC

FUNCTION TABLE

INPUTS

DATA I/Os

OPERATION OR FUNCTION

OE

X

H

L

DIR

X

CLKAB

CLKBA

SAB

X

SBA

X

A1 THRU A8

B1 THRU B8

†

↑

X

Input

Unspecified

Input

Store A, B unspecified

†

X

↑

X

Unspecified

Store B, A unspecified

X

↑

H or L

X

↑

H or L

X

Input

Input disabled

Output

Input

Store A and B data

Isolation, hold storage

Real-time B data to A bus

Stored B data to A bus

Real-time A data to B bus

Stored A data to B bus

X

Input disabled

Input

L

X

L

X

H or L

X

H

Output

Input

L

H

X

L

X

Input

Output

L

H or L

X

H

X

Input

Output

†

The data output functions may be enabled or disabled by various signals at OE and DIR. Data input functions always are enabled; i.e., data at

the bus pins are stored on every low-to-high transition of the clock inputs.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢗ ꢐꢆ ꢘ ꢋ ꢍꢀꢆꢎꢆ ꢔ ꢙ ꢑꢆ ꢚꢑ ꢆ

SCBS149D − JULY 1994 − REVISED MARCH 2004

DIR CLKAB CLKBA SAB

SBA

L

DIR

H

CLKAB CLKBA SAB

SBA

X

OE

L

OE

L

X

L

REAL-TIME TRANSFER

BUS B TO BUS A

REAL-TIME TRANSFER

BUS A TO BUS B

DIR CLKAB CLKBA SAB

SBA

X

DIR

L

CLKAB CLKBA SAB

SBA

H

OE

X

OE

L

X

H or L

X

H

X

↑

X

↑

X

L

H

H or L

X

H

X

↑

STORAGE FROM

A, B, OR A AND B

TRANSFER STORED DATA

TO A AND/OR B

Figure 1. Bus-Management Functions

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢈꢃ ꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢈ ꢃꢈ

ꢋꢌ ꢋꢍꢅ ꢎ ꢏꢆ ꢇ ꢈꢍ ꢏꢐ ꢆ ꢏꢑ ꢀ ꢆꢒ ꢎꢁ ꢀꢓ ꢔꢐ ꢅ ꢔ ꢒꢀ ꢎꢁꢕ ꢒꢔ ꢖꢐ ꢀꢆ ꢔꢒꢀ

ꢗꢐ ꢆ ꢘ ꢋ ꢍꢀꢆꢎꢆ ꢔ ꢙꢑꢆ ꢚꢑ ꢆꢀ

SCBS149D − JULY 1994 − REVISED MARCH 2004

logic diagram (positive logic)

56

1OE

1

1DIR

55

1CLKBA

54

1SBA

2

1CLKAB

3

1SAB

One of Eight Channels

1D

C1

5

1A1

52

1B1

1D

C1

To Seven Other Channels

29

28

2OE

2DIR

30

31

27

2CLKBA

2SBA

2CLKAB

26

2SAB

One of Eight Channels

1D

C1

15

2A1

42

2B1

1D

C1

To Seven Other Channels

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢗ ꢐꢆ ꢘ ꢋ ꢍꢀꢆꢎꢆ ꢔ ꢙ ꢑꢆ ꢚꢑ ꢆ

SCBS149D − JULY 1994 − REVISED MARCH 2004

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V

CC

Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

I

Voltage range applied to any output in the high state or power-off state, V (see Note 1) . . . . −0.5 V to 7 V

O

Current into any output in the low state, I : SN54LVT16646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA

O

SN74LVT16646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA

Current into any output in the high state, I (see Note 2): SN54LVT16646 . . . . . . . . . . . . . . . . . . . . . . . 48 mA

O

SN74LVT16646 . . . . . . . . . . . . . . . . . . . . . . . 64 mA

Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

IK

OK

I

Output clamp current, I

(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

O

Package thermal impedance, θ (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W

JA

DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

Storage temperature range, T

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. This current flows only when the output is in the high state and V > V

.

CC

O

3. The package thermal impedance is calculated in accordance with JESD 51−7.

recommended operating conditions (see Note 4)

SN54LVT16646 SN74LVT16646

MIN MAX MIN MAX

UNIT

V

Supply voltage

2.7

2

3.6

2.7

2

3.6

V

CC

High-level input voltage

Low-level input voltage

Input voltage

IH

0.8

5.5

−24

48

0.8

5.5

−32

64

V

IL

V

I

High-level output current

Low-level output current

Input transition rise or fall rate

Operating free-air temperature

mA

ns/V

°C

OH

OL

∆t/∆v

Outputs enabled

10

T

A

−55

125

−40

85

NOTE 4: All unused control inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

CC

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5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢈꢃ ꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢈ ꢃꢈ

ꢋꢌ ꢋꢍꢅ ꢎ ꢏꢆ ꢇ ꢈꢍ ꢏꢐ ꢆ ꢏꢑ ꢀ ꢆꢒ ꢎꢁ ꢀꢓ ꢔꢐ ꢅ ꢔ ꢒꢀ ꢎꢁꢕ ꢒꢔ ꢖꢐ ꢀꢆ ꢔꢒꢀ

ꢗꢐ ꢆ ꢘ ꢋ ꢍꢀꢆꢎꢆ ꢔ ꢙꢑꢆ ꢚꢑ ꢆꢀ

SCBS149D − JULY 1994 − REVISED MARCH 2004

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

SN54LVT16646

SN74LVT16646

PARAMETER

TEST CONDITIONS

UNIT

†

MIN TYP

MAX

MIN TYP

MAX

V

= 2.7 V,

I = −18 mA

−1.2

V

IK

CC

I

‡

= MIN to MAX ,

I

= −100 µA

= − 8 mA

= − 24 mA

= −32 mA

= 100 µA

= 24 mA

= 16 mA

= 32 mA

= 48 mA

= 64 mA

V

−0.2

V

−0.2

OH

OL

CC

2.4

CC

2.4

= 2.7 V,

V

OH

V

2

V

= 3 V

CC

2

0.2

0.5

0.2

0.5

0.4

0.5

V

= 2.7 V

0.4

V

OL

0.5

V

CC

= 3 V

0.55

1

V

= 3.6 V,

V = V

I CC

or GND

1

10

CC

Control inputs

‡

= 0 or MAX ,

V = 5.5 V

I

10

CC

V = 5.5 V

I

20

I

µA

§

V = V

5

V

CC

= 3.6 V

A or B ports

I

CC

V = 0

−10

100

I

V

= 0,

V or V = 0 to 4.5 V

I

µA

off

CC

O

V = 0.8 V

75

I

= 3 V

A or B ports

I(hold)

CC

V = 2 V

I

−75

I

V

= 3.6 V,

V

= 3 V

1

−1

1

−1

µA

OZH

CC

O

V

= 0.5 V

OZL

CC

Outputs high

Outputs low

Outputs disabled

− 0.6 V,

0.12

5

0.12

5

V

= 3.6 V,

I

= 0,

CC

O

I

mA

CC

V = V

I

or GND

CC

0.12

V

= 3 V to 3.6 V,

One input at V

CC

or GND

CC

Other inputs at V

¶

∆I

CC

0.2

mA

CC

C

V = 3 V or 0

3.5

12

3.5

12

pF

i

I

V

O

= 3 V or 0

io

†

‡

§

¶

All typical values are at V

CC

= 3.3 V, T = 25°C.

A

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

Unused pins at V or GND

CC

This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V

or GND.

CC

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ꢨ

ꢠ

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ꢰ

ꢤ

ꢠ

ꢨ

ꢞ

ꢩ

ꢤ

ꢡ

ꢝ

ꢧ

ꢝ

ꢡ

ꢦ

ꢛ

ꢝ

ꢠ

ꢥ

ꢞ

ꢦ

ꢨ

ꢤ

ꢟ

ꢤ

ꢞ

ꢝ

ꢯ

ꢥ

ꢯ

ꢠ

ꢦ

ꢫ

ꢞ

ꢌ

ꢆ

ꢤ

ꢬ

ꢦ

ꢞ

ꢐ

ꢥ

ꢞ

ꢛ

ꢨ

ꢢ

ꢣ

ꢤ

ꢥ

ꢡ ꢜ ꢦ ꢥ ꢯꢤ ꢠꢨ ꢟꢝ ꢞ ꢡ ꢠꢥ ꢛꢝ ꢥꢢ ꢤ ꢛ ꢜꢤ ꢞ ꢤ ꢩꢨ ꢠ ꢟꢢꢡ ꢛꢞ ꢭ ꢝꢛꢜ ꢠꢢꢛ ꢥꢠꢛ ꢝꢡꢤ ꢌ

ꢛ

ꢞ

ꢨ

ꢤ

ꢞ

ꢤ

ꢨ

ꢰ

ꢤ

ꢞ

ꢛ

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ꢤ

ꢨ

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ꢯ

ꢜ

ꢛ

ꢠ

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢆ

ꢇ

ꢈ

ꢃ

ꢈ

ꢉ

ꢀ

ꢋ ꢌꢋ ꢍꢅ ꢎꢏꢆ ꢇ ꢈ ꢍꢏꢐ ꢆ ꢏꢑꢀ ꢆ ꢒꢎꢁꢀ ꢓꢔꢐ ꢅꢔꢒꢀ ꢎꢁꢕ ꢒꢔꢖ ꢐ ꢀ ꢆꢔ ꢒ

ꢁ

ꢊ

ꢃ

ꢄ

ꢅ

ꢆ

ꢇ

ꢈ

ꢃ

ꢈ

ꢀ

ꢗ ꢐꢆ ꢘ ꢋ ꢍꢀꢆꢎꢆ ꢔ ꢙ ꢑꢆ ꢚꢑ ꢆ

SCBS149D − JULY 1994 − REVISED MARCH 2004

timing requirements over recommended operating free-air temperature range (unless otherwise

noted) (see Figure 2)

SN54LVT16646

= 3.3 V

SN74LVT16646

= 3.3 V

V

CC

V

CC

V

= 2.7 V

V

= 2.7 V

UNIT

CC

0.3 V

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

f

t

Clock frequency

150

MHz

ns

clock

Pulse duration, CLK high or low

3.3

1.3

2.4

0.5

0.6

3.3

1.4

3

3.3

1.3

2.4

0.5

3.3

1.4

3

w

Data high

Data low

Data high

Data low

Setup time,

A or B before CLKAB↑ or CLKBA↑

t

ns

su

h

0

Hold time,

A or B after CLKAB↑ or CLKBA↑

t

0.5

switching characteristics over recommended operating free-air temperature range, C = 50 pF

L

(unless otherwise noted) (see Figure 2)

SN54LVT16646

= 3.3 V

SN74LVT16646

V

= 3.3 V

V

FROM

(INPUT)

TO

(OUTPUT)

CC

V

CC

= 2.7 V

MAX

PARAMETER

UNIT

CC

0.3 V

†

MIN

150

1.8

2.1

1.3

1

MAX

MIN

MAX

MIN TYP

MAX

MIN

f

t

150

MHz

ns

max

PLH

PHL

PLH

PHL

PLH

PHL

PZH

PZL

PHZ

PLZ

PZH

PZL

PHZ

PLZ

6

5.9

4.9

4.8

6.4

5.7

6.5

6.7

6

6.9

6.6

5.6

5.8

7.4

7.5

7.1

6.5

7.7

7.3

8.5

7.4

1.8

2.1

1.3

1

3.8

3.9

3

5.7

4.7

6.2

5.4

5.6

6.5

5.8

5.7

5.8

7.2

6.6

6.7

6.5

5.4

5.6

7.2

6.4

6.5

6.9

5.9

6.7

8.3

7.2

CLKBA or

CLKAB

A or B

B or A

A or B

SBA or SAB

OE

ns

3.1

4

1.4

1

1.4

1

‡

4.3

3

1

3.1

4.6

4.5

3.3

3.5

4.7

4.9

2.3

2.2

1

2.3

2.2

1

OE

5.9

7.3

7.8

DIR

1.2

1.7

1.5

1.2

1.7

1.5

DIR

†

‡

All typical values are at V

CC

= 3.3 V, T = 25°C.

A

These parameters are measured with the internal output state of the storage register opposite to that of the bus input.

ꢚ

ꢒ

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ꢠ

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ꢡ

ꢠ

ꢥ

ꢡ

ꢤ

ꢨ

ꢥ

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ꢩ

ꢨ

ꢠ

ꢟ

ꢢ

ꢟꢤ ꢞ ꢝ ꢯꢥ ꢩꢜ ꢦ ꢞ ꢤ ꢠꢧ ꢟꢤ ꢰ ꢤ ꢫꢠ ꢩꢣꢤ ꢥꢛꢌ ꢓ ꢜꢦ ꢨꢦ ꢡꢛ ꢤꢨ ꢝꢞ ꢛꢝ ꢡ ꢟꢦ ꢛꢦ ꢦꢥ ꢟ ꢠꢛ ꢜꢤꢨ

ꢡ

ꢛ

ꢞ

ꢝ

ꢥ

ꢛ

ꢜ

ꢤ

ꢧ

ꢠ

ꢨ

ꢣ

ꢦ

ꢛ

ꢝ

ꢰ

ꢤ

ꢠ

ꢨ

ꢞ

ꢩ

ꢤ

ꢡ

ꢝ

ꢧ

ꢝ

ꢡ

ꢦ

ꢛ

ꢝ

ꢠ

ꢥ

ꢞ

ꢦ

ꢨ

ꢤ

ꢟ

ꢤ

ꢞ

ꢝ

ꢯ

ꢥ

ꢯ

ꢠ

ꢦ

ꢫ

ꢞ

ꢌ

ꢆ

ꢤ

ꢬ

ꢦ

ꢞ

ꢐ

ꢥ

ꢞ

ꢛ

ꢨ

ꢢ

ꢣ

ꢤ

ꢥ

ꢡ ꢜꢦ ꢥ ꢯꢤ ꢠꢨ ꢟꢝ ꢞ ꢡ ꢠꢥ ꢛꢝ ꢥꢢꢤ ꢛ ꢜꢤ ꢞ ꢤ ꢩꢨ ꢠꢟ ꢢꢡꢛ ꢞ ꢭ ꢝꢛꢜ ꢠꢢꢛ ꢥꢠꢛ ꢝꢡꢤ ꢌ

ꢛ

ꢞ

ꢨ

ꢤ

ꢞ

ꢤ

ꢨ

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ꢤ

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ꢛ

ꢜ

ꢤ

ꢨ

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ꢜ

ꢛ

ꢠ

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢈꢃ ꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢈ ꢃꢈ

ꢋꢌ ꢋꢍꢅ ꢎ ꢏꢆ ꢇ ꢈꢍ ꢏꢐ ꢆ ꢏꢑ ꢀ ꢆꢒ ꢎꢁ ꢀꢓ ꢔꢐ ꢅ ꢔ ꢒꢀ ꢎꢁꢕ ꢒꢔ ꢖꢐ ꢀꢆ ꢔꢒꢀ

ꢗꢐ ꢆ ꢘ ꢋ ꢍꢀꢆꢎꢆ ꢔ ꢙꢑꢆ ꢚꢑ ꢆꢀ

SCBS149D − JULY 1994 − REVISED MARCH 2004

PARAMETER MEASUREMENT INFORMATION

6 V

TEST

S1

500 Ω

Open

GND

t

/t

PLH PHL

Open

6 V

From Output

Under Test

t

/t

PLZ PZL

t

/t

PHZ PZH

GND

C

= 50 pF

L

500 Ω

(see Note A)

2.7 V

0 V

LOAD CIRCUIT FOR OUTPUTS

1.5 V

Timing Input

Data Input

t

w

t

h

su

2.7 V

0 V

2.7 V

0 V

Input

1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

2.7 V

0 V

2.7 V

0 V

Output

Control

1.5 V

t

Input

1.5 V

t

PZL

t

PHL

PLH

PLZ

1.5 V

Output

Waveform 1

S1 at 6 V

V

3 V

OH

1.5 V

Output

V

+ 0.3 V

− 0.3 V

OL

V

OL

(see Note B)

t

PHZ

t

PLH

t

PZH

PHL

Output

Waveform 2

S1 at GND

V

OH

V

OH

1.5 V

Output

(see Note B)

9 0 V

OL

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

NOTES: A.

C includes probe and jig capacitance.

L

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.

O

r

f

D. The outputs are measured one at a time, with one transition per measurement.

E. All parameters and waveforms are not applicable to all devices.

Figure 2. Load Circuit and Voltage Waveforms

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

30-Mar-2005

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SN74LVT16646DGGR

ACTIVE

TSSOP

DGG

56

2000

Pb-Free

(RoHS)

CU NIPDAU Level-1-250C-UNLIM

SN74LVT16646DL

SN74LVT16646DLR

ACTIVE

NRND

SSOP

DL

56

20

TBD

CU NIPDAU Level-1-235C-UNLIM

1000

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan

-

The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS

&

no Sb/Br)

-

please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DATA

MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001

DL (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN

0.025 (0,635)

48

0.0135 (0,343)

0.008 (0,203)

0.005 (0,13)

M

25

0.010 (0,25)

0.005 (0,13)

0.299 (7,59)

0.291 (7,39)

0.420 (10,67)

0.395 (10,03)

Gage Plane

0.010 (0,25)

0°–ā8°

1

24

0.040 (1,02)

0.020 (0,51)

A

Seating Plane

0.004 (0,10)

0.008 (0,20) MIN

PINS **

0.110 (2,79) MAX

28

48

0.630

56

DIM

0.380

(9,65)

0.730

A MAX

A MIN

(16,00) (18,54)

0.370

(9,40)

0.620

0.720

(15,75) (18,29)

4040048/E 12/01

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).

D. Falls within JEDEC MO-118

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MTSS003D – JANUARY 1995 – REVISED JANUARY 1998

DGG (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN

0,27

0,17

M

0,08

0,50

48

25

6,20

6,00

8,30

7,90

0,15 NOM

Gage Plane

0,25

1

24

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

48

56

64

DIM

A MAX

12,60

12,40

14,10

13,90

17,10

16,90

A MIN

4040078/F 12/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

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TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

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Applications

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Amplifiers

amplifier.ti.com

www.ti.com/audio

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dsp.ti.com

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Digital Control

Military

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

Logic

interface.ti.com

logic.ti.com

Power Mgmt

Microcontrollers

power.ti.com

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Security

www.ti.com/opticalnetwork

www.ti.com/security

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www.ti.com/video

microcontroller.ti.com

Telephony

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265


型号：	SN74LVT16646DLR
厂家：	TEXAS INSTRUMENTS
描述：	3.3V ABT 16 BIT BUS TRANSCEIVERS AND REGISTERS WITH 3 STATE OUTPUTS 3.3V ABT 16位总线收发器和寄存器具有三态输出总线驱动器总线收发器触发器逻辑集成电路光电二极管输出元件输入元件信息通信管理
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