SN74LVT16543DLRG4 [TI]
3.3-V ABT 16-Bit Registered Transceivers With 3-State Outputs 56-SSOP -40 to 85;
| 型号： | SN74LVT16543DLRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V ABT 16-Bit Registered Transceivers With 3-State Outputs 56-SSOP -40 to 85 信息通信管理 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总8页 (文件大小：143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LVT16543, SN74LVT16543
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS148C – MAY 1992 – REVISED JULY 1995
SN54LVT16543 . . . WD PACKAGE
SN74LVT16543 . . . DGG OR DL PACKAGE
(TOP VIEW)
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low-Static Power
Dissipation
1OEAB
1LEAB
1CEAB
GND
1OEBA
1LEBA
1CEBA
GND
1B1
1B2
1
2
3
4
5
6
7
8
9
56
55
54
53
52
51
50
49
48
Members of the Texas Instruments
Widebus Family
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V
)
1A1
1A2
CC
Support Unregulated Battery Operation
Down to 2.7 V
V
V
CC
CC
1A3
1A4
1B3
1B4
Typical V
< 0.8 V at V
(Output Ground Bounce)
OLP
= 3.3 V, T = 25°C
CC
A
1A5 10
47 1B5
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
GND
1A6
GND
1B6
11
12
46
45
1A7 13
1A8 14
2A1 15
2A2 16
2A3 17
GND 18
2A4 19
2A5 20
2A6 21
44 1B7
43 1B8
42 2B1
41 2B2
40 2B3
39 GND
38 2B4
37 2B5
36 2B6
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
Bus-Hold Data Inputs Eliminate the Need
for External Pullup Resistors
Support Live Insertion
Distributed V
Minimizes High-Speed Switching Noise
and GND Pin Configuration
CC
V
22
35
V
CC
CC
Flow-Through Architecture Optimizes
PCB Layout
2A7 23
34 2B7
2A8 24
33 2B8
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
GND 25
32 GND
31 2CEBA
30 2LEBA
29 2OEBA
2CEAB 26
2LEAB 27
2OEAB 28
description
The ’LVT16543 are 16-bit registered transceivers designed for low-voltage (3.3-V) V
operation, but with the
CC
capability to provide a TTL interface to a 5-V system environment. These devices can be used as two 8-bit
transceivers or one 16-bit transceiver. Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or
OEBA) inputs are provided for each register to permit independent control in either direction of data flow.
The A-to-B enable (CEAB) input must be low in order to enter data from A or to output data from B. If CEAB
is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts
the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect
the data present at the output of the A latches. Data flow from B to A is similar but requires using the CEBA,
LEBA, and OEBA inputs.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
Copyright 1995, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVT16543, SN74LVT16543
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS148C – MAY 1992 – REVISED JULY 1995
description (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74LVT16543 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG) packages,
which provide twice the I/O pin count and functionality of standard small-outline packages in the same
printed-circuit-board area.
The SN54LVT16543 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVT16543 is characterized for operation from –40°C to 85°C.
†
logic symbol
56
54
55
1
1EN3
G1
1OEBA
1CEBA
1LEBA
1OEAB
1C5
2EN4
G2
3
1CEAB
1LEAB
2OEBA
2CEBA
2LEBA
2OEAB
2CEAB
2LEAB
2
2C6
29
31
30
28
26
27
7EN9
G7
7C11
8EN10
G8
8C12
5
52
1A1
5D
4
1B1
3
6D
6
51
49
48
47
45
44
1A2
1A3
1A4
1A5
1B2
1B3
1B4
1B5
1B6
1B7
8
9
10
12
1A6
1A7
1A8
2A1
13
14
15
43
42
1B8
2B1
11D
10
9
12D
16
17
19
20
21
23
24
41
40
38
37
36
34
33
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2B2
2B3
2B4
2B5
2B6
2B7
2B8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVT16543, SN74LVT16543
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS148C – MAY 1992 – REVISED JULY 1995
logic diagram (positive logic)
56
1OEBA
54
1CEBA
55
1LEBA
1
1OEAB
3
1CEAB
2
1LEAB
C1
1D
5
1A1
52
1B1
C1
1D
To Seven Other Channels
29
2OEBA
31
2CEBA
30
2LEBA
28
2OEAB
26
2CEAB
27
2LEAB
C1
1D
15
2A1
42
2B1
C1
1D
To Seven Other Channels
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVT16543, SN74LVT16543
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS148C – MAY 1992 – REVISED JULY 1995
†
FUNCTION TABLE
(each 8-bit section)
INPUTS
OUTPUT
B
CEAB
LEAB
OEAB
A
X
X
X
L
H
X
L
L
L
X
X
H
L
X
H
L
Z
Z
‡
B
0
L
L
L
L
H
H
†
‡
A-to-B data flow is shown; B-to-A flow control is the
same except that it uses CEBA, LEBA, and OEBA.
Output level before the indicated steady-state input
conditions were established
§
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high state or power-off state, V (see Note 1) . . . . –0.5 V to 7 V
O
Current into any output in the low state, I : SN54LVT16543 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74LVT16543 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, I (see Note 2): SN54LVT16543 . . . . . . . . . . . . . . . . . . . . . . . 48 mA
O
SN74LVT16543 . . . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Maximum power dissipation at T = 55°C (in still air) (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . 1 W
A
DL package . . . . . . . . . . . . . . . . . . . . 1.4 W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
§
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V > V
.
CC
O
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
Formoreinformation,refertothePackageThermalConsiderationsapplicationnoteinthe1994ABTAdvancedBiCMOSTechnology
Data Book, literature number SCBD002B.
recommended operating conditions (see Note 4)
SN54LVT16543 SN74LVT16543
UNIT
MIN MAX
MIN MAX
V
V
V
V
Supply voltage
2.7
2
3.6
2.7
2
3.6
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
5.5
–24
48
0.8
5.5
–32
64
V
IL
V
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
mA
mA
ns/V
°C
OH
OL
I
∆t/∆v
Outputs enabled
10
10
T
A
–55
125
–40
85
NOTE 4: Unused control inputs must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVT16543, SN74LVT16543
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS148C – MAY 1992 – REVISED JULY 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVT16543
SN74LVT16543
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
= 2.7 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
CC
CC
I
‡
= MIN to MAX ,
= 2.7 V,
I
I
I
I
I
I
I
I
I
I
= –100 µA
= – 8 mA
= – 24 mA
= –32 mA
= 100 µA
= 24 mA
= 16 mA
= 32 mA
= 48 mA
= 64 mA
V
–0.2
V
–0.2
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
CC
2.4
CC
2.4
V
OH
V
V
2
V
= 3 V
CC
CC
2
0.2
0.5
0.2
0.5
0.4
0.5
V
= 2.7 V
0.4
V
OL
0.5
V
CC
= 3 V
0.55
0.55
±1
V
V
= 3.6 V,
V = V
I
or GND
±1
10
CC
CC
Control inputs
‡
= 0 or MAX ,
V = 5.5 V
I
10
CC
I
I
V = 5.5 V
I
20
20
µA
§
V
CC
= 3.6 V
V = V
I CC
A or B ports
5
5
V = 0
–10
–10
±100
I
I
I
V
V
= 0,
V or V = 0 to 4.5 V
I
µA
µA
off
CC
O
V = 0.8 V
75
75
I
= 3 V
A or B ports
I(hold)
CC
V = 2 V
I
–75
–75
I
I
V
V
= 3.6 V,
= 3.6 V,
V
= 3 V
1
–1
1
–1
µA
µA
OZH
CC
O
O
V
= 0.5 V
OZL
CC
Outputs high
Outputs low
Outputs disabled
– 0.6 V,
0.12
5
0.12
5
V
= 3.6 V,
or GND
CC
I
= 0,
CC
O
I
mA
CC
V = V
I
0.12
0.12
V
= 3 V to 3.6 V,
One input at V
CC
or GND
CC
Other inputs at V
¶
∆I
0.2
0.2
mA
CC
CC
C
C
V = 3 V or 0
4
4
pF
pF
i
I
V
O
= 3 V or 0
13
13
io
†
‡
§
¶
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
Unused pins at V or GND
CC
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVT16543, SN74LVT16543
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS148C – MAY 1992 – REVISED JULY 1995
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
SN54LVT16543
= 3.3 V
SN74LVT16543
= 3.3 V
V
CC
V
CC
UNIT
V
= 2.7 V
V
= 2.7 V
CC
CC
± 0.3 V
± 0.3 V
MIN
3.3
0.8
1.5
0.7
1.6
0.8
1.2
0.8
1.3
MAX
MIN
3.3
0.5
1.9
0.4
1.9
0
MAX
MIN
3.3
0.8
1.5
0.7
1.6
0.8
1.2
0.8
1.3
MAX
MIN
3.3
0.5
1.9
0.4
1.9
0
MAX
t
t
Pulse duration, LEAB or LEBA low
ns
ns
w
Data high
Data low
Data high
Data low
Data high
Data low
Data high
Data low
A or B before LEAB↑ or
LEBA↑
Setup time
su
A or B before CEAB↑ or
CEBA↑
ns
ns
ns
A or B after LEAB↑ or
LEBA↑
Hold time
1.3
0
1.3
0
t
h
A or B after CEAB↑ or
CEBA↑
1.4
1.4
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
SN54LVT16543
= 3.3 V
SN74LVT16543
FROM
(INPUT)
TO
(OUTPUT)
V
CC
V
CC
= 3.3 V
V
V
= 2.7 V
= 2.7 V
PARAMETER
UNIT
CC
CC
± 0.3 V
± 0.3 V
†
MIN
1.4
1.3
1.3
1.5
1.4
1.6
2
MAX
5
MIN
MAX
5.8
5.9
8.5
8.3
7.7
8.4
7.3
6.2
7.7
8.5
7.2
5.9
MIN TYP
MAX
4.6
4.6
6.3
6
MIN
MAX
5.5
5.8
8.1
7.8
7.6
8.2
7.1
5.9
7.6
8.3
7.1
5.6
t
t
t
t
t
t
t
t
t
t
t
t
1.4
1.3
1.7
1.9
1.5
1.6
2
2.7
2.9
3.7
3.7
3.3
3.3
4.1
3.9
3.3
3.3
4.1
4
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
PZH
PZL
PHZ
PLZ
A or B
B or A
A or B
A or B
A or B
A or B
A or B
ns
ns
ns
ns
ns
ns
4.7
6.8
6.5
6
LE
OE
OE
CE
CE
5.8
6.2
6.5
5.8
6
6.3
6.7
6
2.7
1.4
1.6
2
2.7
1.5
1.7
2
6.2
6.6
6.6
5.6
6.4
6.4
5.4
2.6
2.6
†
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVT16543, SN74LVT16543
3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS148C – MAY 1992 – REVISED JULY 1995
PARAMETER MEASUREMENT INFORMATION
6 V
Open
TEST
S1
S1
500 Ω
t
t
/t
Open
6 V
From Output
Under Test
PLH PHL
/t
t
PLZ PZL
/t
GND
GND
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
2.7 V
0 V
LOAD CIRCUIT FOR OUTPUTS
1.5 V
Timing Input
Data Input
t
w
t
t
h
su
2.7 V
0 V
2.7 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
0 V
Output
Control
1.5 V
1.5 V
t
1.5 V
1.5 V
Input
t
PZL
t
t
PHL
PLH
PLZ
1.5 V
Output
Waveform 1
S1 at 6 V
V
V
3 V
OH
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
– 0.3 V
OL
V
OL
OL
(see Note B)
t
PHZ
t
PLH
t
t
PZH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
OH
1.5 V
1.5 V
Output
(see Note B)
0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明