SN74LVC2G17DCKR [TI]
DUAL SCHMITT TRIGGER BUFFER; 双施密特触发器缓冲器型号: | SN74LVC2G17DCKR |
厂家: | TEXAS INSTRUMENTS |
描述: | DUAL SCHMITT TRIGGER BUFFER |
文件: | 总13页 (文件大小:325K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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ꢊꢋꢌ ꢄ ꢀꢆꢍ ꢎꢏ ꢐꢐꢑꢐ ꢒꢏꢈ ꢈ ꢓꢒ ꢔ ꢋꢕ ꢕꢓ ꢒ
SCES381E − JANUARY 2002 − REVISED SEPTEMBER 2003
DBV OR DCK PACKAGE
(TOP VIEW)
D
Available in the Texas Instruments
NanoStar and NanoFree Packages
D
D
D
D
D
D
D
D
D
D
Supports 5-V V
Operation
CC
1
2
3
6
5
4
1A
GND
2A
1Y
Inputs Accept Voltages to 5.5 V
V
CC
Max t of 5.4 ns at 3.3 V
pd
Low Power Consumption, 10-µA Max I
2Y
CC
YEA, YEP, YZA, OR YZP PACKAGE
(BOTTOM VIEW)
24-mA Output Drive at 3.3 V
Typical V
<0.8 V at V
(Output Ground Bounce)
= 3.3 V, T = 25°C
OLP
CC
A
3 4
2 5
1 6
2A
GND
1A
2Y
V
Typical V
(Output V
= 3.3 V, T = 25°C
Undershoot)
OHV
OH
CC
>2 V at V
1Y
CC
A
I
Supports Partial-Power-Down Mode
off
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
This dual Schmitt-trigger buffer is designed for 1.65-V to 5.5-V V
operation.
CC
The SN74LVC2G17 contains two buffers and performs the Boolean function Y = A. The device functions as two
independent buffers, but because of Schmitt action, it may have different input threshold levels for positive-going
(V ) and negative-going (V ) signals.
T+
T−
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
‡
NanoStar − WCSP (DSBGA)
0.17-mm Small Bump − YEA
SN74LVC2G17YEAR
SN74LVC2G17YZAR
SN74LVC2G17YEPR
SN74LVC2G17YZPR
NanoFree − WCSP (DSBGA)
0.17-mm Small Bump − YZA (Pb-free)
Reel of 3000
_ _ _C7_
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
−40°C to 85°C
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
Reel of 3000
Reel of 250
Reel of 3000
SN74LVC2G17DBVR
SN74LVC2G17DBVT
SN74LVC2G17DCKR
SOT (SOT-23) − DBV
SOT (SC-70) − DCK
C17_
C7_
Reel of 250
SN74LVC2G17DCKT
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code,
and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
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Copyright 2003, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCES381E − JANUARY 2002 − REVISED SEPTEMBER 2003
description/ordering information (continued)
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
FUNCTION TABLE
(each inverter)
INPUT
A
OUTPUT
Y
H
L
H
L
logic diagram (positive logic)
1
3
6
4
1A
2A
1Y
2Y
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
I
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
IK
I
Output clamp current, I
OK
O
O
Continuous current through V
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CC
Package thermal impedance, θ (see Note 3): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165°C/W
JA
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259°C/W
YEA/YZA package . . . . . . . . . . . . . . . . . . . . . . . . . . . 143°C/W
YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 123°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of V is provided in the recommended operating conditions table.
CC
3. The package thermal impedance is calculated in accordance with JESD 51-7.
2
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SCES381E − JANUARY 2002 − REVISED SEPTEMBER 2003
recommended operating conditions (see Note 4)
MIN
1.65
0
MAX
5.5
UNIT
V
V
V
Supply voltage
Input voltage
Output voltage
Operating
V
V
V
CC
5.5
I
0
V
CC
−4
O
V
V
= 1.65 V
= 2.3 V
CC
−8
CC
−16
−24
−32
4
I
High-level output current
mA
OH
OL
V
= 3 V
CC
V
CC
V
CC
V
CC
= 4.5 V
= 1.65 V
= 2.3 V
8
16
24
32
85
I
Low-level output current
mA
V
= 3 V
CC
CC
V
= 4.5 V
T
Operating free-air temperature
−40
°C
A
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCES381E − JANUARY 2002 − REVISED SEPTEMBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
TYP
PARAMETER
TEST CONDITIONS
MIN
0.7
1
MAX
1.4
1.7
2.2
3.1
3.7
0.7
1
UNIT
V
CC
1.65 V
2.3 V
V
T+
3 V
1.3
1.9
2.2
0.3
0.4
0.6
1.1
1.4
0.3
0.4
0.4
0.6
0.7
Positive-going input
threshold voltage
V
4.5 V
5.5 V
1.65 V
2.3 V
V
T−
3 V
1.3
2
Negative-going input
threshold voltage
V
V
4.5 V
5.5 V
2.5
0.8
0.9
1.1
1.3
1.4
1.65 V
2.3 V
∆V
T
3 V
Hysteresis
(V − V
)
T+ T−
4.5 V
5.5 V
I
I
I
I
I
I
I
I
I
I
I
I
= −100 µA
= −4 mA
= −8 mA
= −16 mA
= −24 mA
= −32 mA
= 100 µA
= 4 mA
1.65 V to 5.5 V
1.65 V
2.3 V
V
CC
−0.1
OH
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
1.2
1.9
2.4
2.3
3.8
V
OH
V
3 V
4.5 V
1.65 V to 5.5 V
1.65 V
0.1
0.45
0.3
0.4
0.55
0.55
5
= 8 mA
2.3 V
V
OL
V
= 16 mA
= 24 mA
= 32 mA
3 V
4.5 V
0 to 5.5 V
0
I
I
I
A input V = 5.5 V or GND
µA
µA
µA
µA
pF
I
I
V or V = 5.5 V
10
off
CC
I
O
V = 5.5 V or GND,
I
= 0
1.65 V to 5.5 V
3 V to 5.5 V
3.3 V
10
I
O
∆I
CC
One input at V
CC
− 0.6 V, Other inputs at V
CC
or GND
500
C
V = V
or GND
= 3.3 V, T = 25°C.
4
i
I
CC
†
All typical values are at V
CC
A
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
V
= 1.8 V
V
= 2.5 V
V
= 3.3 V
V
= 5 V
CC
0.15 V
CC
0.2 V
CC
0.3 V
CC
0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
3.9
MAX
MIN
1.9
MAX
MIN
2.2
MAX
MIN
MAX
4.3
t
pd
A
9.3
5.7
5.4
1.5
ns
Y
4
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SCES381E − JANUARY 2002 − REVISED SEPTEMBER 2003
operating characteristics, T = 25°C
A
V
= 1.8 V
V
= 2.5 V
V
= 3.3 V
V
= 5 V
CC
TYP
17
CC
TYP
18
CC
TYP
19
CC
TYP
21
PARAMETER
TEST CONDITIONS
UNIT
C
Power dissipation capacitance
f = 10 MHz
pF
pd
5
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SCES381E − JANUARY 2002 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
V
LOAD
Open
S1
R
L
From Output
Under Test
TEST
S1
GND
t
t
/t
Open
PLH PHL
/t
C
L
t
V
R
PLZ PZL
LOAD
GND
L
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
C
R
L
V
LOAD
L
∆
V
I
t /t
r f
1.8 V 0.15 V
2.5 V 0.2 V
3.3 V 0.3 V
5 V 0.5 V
V
V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
V
V
/2
/2
2 × V
2 × V
6 V
2 × V
CC
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
CC
CC
CC
CC
CC
CC
3 V
1.5 V
/2
V
CC
V
CC
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
su
h
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
V
0 V
t
t
t
t
t
PHL
PZL
PLZ
+ V
PLH
PHL
Output
Waveform 1
V
/2
OH
LOAD
V
V
V
M
Output
M
V
V
M
S1 at V
(see Note B)
V
LOAD
OL
∆
V
OL
V
OL
t
PLH
t
t
PZH
PHZ
− V
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
V
M
OH
∆
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS114 – FEBRUARY 2002
DCK (R-PDSO-G6)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
M
0,10
0,65
6
4
0,13 NOM
1,40 2,40
1,10 1,80
1
3
Gage Plane
2,15
1,85
0,15
0°–8°
0,46
0,26
Seating Plane
0,10
1,10
0,80
0,10
0,00
4093553-3/D 01/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-203
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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