SN74LVC1G14QDCKRQ1 [TI]
具有施密特触发输入的汽车类单路 1.65V 至 5.5V 反相器 | DCK | 5 | -40 to 125;
| 型号： | SN74LVC1G14QDCKRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有施密特触发输入的汽车类单路 1.65V 至 5.5V 反相器 | DCK | 5 | -40 to 125 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总25页 (文件大小：2127K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVC1G14-Q1
ZHCSDC2C –FEBRUARY 2015 –REVISED AUGUST 2021
SN74LVC1G14-Q1 单路施密特触发逆变器
1 特性
3 说明
• 符合汽车应用要求
• 具有符合AEC-Q100 标准的下列特性：
这款单路施密特触发反相器支持 1.65V 至 5.5V VCC 运
行。
– 器件温度等级1：–40°C 至+125°C 环境工作
温度范围
– 器件的人体放电模型(HBM) ESD 分类等级2
– 器件的充电器件模型(CDM) ESD 分类等级C5
• 支持5V VCC 运行
SN74LVC1G14-Q1 器件包含一个反相器并执行布尔函
数 Y = A。该器件可作为一个独立的反相器，但由于施
密特触发，它针对正向 (VT+) 和负向 (VT–) 信号的输入
阈值电平可能有所不同。
该器件完全符合使用 Ioff 的部分断电应用的规范要求。
Ioff 电路禁用输出，从而可防止其断电时破坏性电流从
该器件回流。
• 输入电压高达5.5V
• 3.3V 时tpd 最大值为4.6ns
• 低功耗，ICC 最大值为10µA
• 电压为3.3V 时，输出驱动为±24mA
• Ioff 支持局部断电模式运行
器件信息(1)
封装尺寸（标称值）
器件型号
封装
SC70 (5)
SON (6)
• 闩锁性能超过100mA，符合JESD 78 II 类规范
2.10mm × 2.00mm
1.45mm × 1.00mm
SN74LVC1G14-Q1
2 应用
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 车身控制模块
• 引擎控制模块
• 信息娱乐系统
• 远程信息处理
2
4
A
Y
简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCES865
SN74LVC1G14-Q1
ZHCSDC2C –FEBRUARY 2015 –REVISED AUGUST 2021
www.ti.com.cn
Table of Contents
8.2 Functional Block Diagram...........................................9
8.3 Feature Description.....................................................9
8.4 Device Functional Modes............................................9
9 Application and Implementation..................................10
9.1 Application Information............................................. 10
9.2 Typical Application.................................................... 10
10 Power Supply Recommendations..............................11
11 Layout........................................................................... 11
11.1 Layout Guidelines....................................................11
11.2 Layout Example.......................................................11
12 Device and Documentation Support..........................12
12.1 接收文档更新通知................................................... 12
12.2 支持资源..................................................................12
12.3 Trademarks.............................................................12
12.4 Electrostatic Discharge Caution..............................12
12.5 术语表..................................................................... 12
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics, CL = 15 pF........................ 6
6.7 Switching Characteristics, CL = 30 pF or 50 pF..........6
6.8 Operating Characteristics........................................... 6
6.9 Typical Characteristics................................................6
7 Parameter Measurement Information............................7
8 Detailed Description........................................................9
8.1 Overview.....................................................................9
Information.................................................................... 12
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (August 2019) to Revision C (August 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• Updated the pin numbers for VCC and N.C. in the Pin Functions table for the DRY package to match the pin
configuration....................................................................................................................................................... 3
• Updated the TPD Across Temperature at 3.3 V VCC image in the Typical Characteristics ................................6
Changes from Revision A (March 2017) to Revision B (August 2019)
Page
• 向器件信息表添加了SON (6) DRY 封装............................................................................................................1
• Added DRY package pinout to Pin Configurations and Functions section ........................................................3
Changes from Revision * (February 2015) to Revision A (March 2017)
Page
• 将器件信息表中的封装类型更改为DCK (SC70) 并更正了封装尺寸..................................................................1
• Deleted θJA from Absolute Maximum Ratings table..........................................................................................4
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5 Pin Configuration and Functions
1
2
3
6
5
4
VCC
N.C.
Y
N.C.
A
1
2
3
5
N.C.
A
VCC
GND
4
GND
Y
N.C. –No internal connection
See mechanical drawings for dimensions.
图5-1. DCK Package 5-Pin SC70 (Top View)
图5-2. DRY Package 6-Pin SON Transparent Top
View
Pin Functions
PIN
DCK (SC70) DRY (SON)
I/O
DESCRIPTION
NAME
NO.
2
NO.
2
A
I
Input
GND
N.C.
VCC
Y
3
3
Ground
—
—
—
O
1
1, 5
6
No internal connection.
Supply or power pin
Output
5
4
4
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.53
–0.5
–0.5
MAX
UNIT
V
VCC
VI
Supply voltage
6.5
6.5
Input voltage(2)
V
VO
VO
IIK
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high or low state(2) (3)
6.5
V
VCC + 0.5
V
Input clamp current
VI < 0
mA
mA
mA
mA
°C
–50
–50
±50
IOK
IO
Output clamp current
VO < 0
Continuous output current
Continuous current through VCC or GND
Storage temperature
±100
150
Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
6.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
See(1)
MIN
MAX UNIT
Operating
1.65
1.5
0
5.5
V
VCC Supply voltage
Data retention only
VI
Input voltage
5.5
VCC
–4
–8
–16
–24
–32
4
V
V
VO
Output voltage
0
VCC = 1.65 V
VCC = 2.3 V
IOH
High-level output current
mA
VCC = 3 V
VCC = 4.5 V
VCC = 1.65 V
VCC = 2.3 V
8
IOL
Low-level output current
16
mA
°C
VCC = 3 V
24
VCC = 4.5 V
32
TA
Operating free-air temperature
125
–40
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.
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6.4 Thermal Information
SN74LVC1G14-Q1
THERMAL METRIC(1)
DCK (SC70)
DRY (SON)
6 PINS
264
UNIT
5 PINS
280
66
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
167
67
142
Junction-to-top characterization parameter
Junction-to-board characterization parameter
2
26
66
142
ψJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V
2.3 V
MIN TYP(1) MAX
UNIT
0.79
1.11
1.16
1.56
1.87
2.74
3.33
0.64
0.89
1.16
1.79
2.29
0.62
0.77
0.87
1.04
1.11
VT+
Positive-going
input threshold
voltage
3 V
1.5
V
4.5 V
2.16
2.61
0.39
0.58
0.84
1.41
1.87
0.37
0.48
0.56
0.71
0.71
VCC –0.1
1.2
5.5 V
1.65 V
2.3 V
VT–
Negative-going
input threshold
voltage
3 V
V
V
4.5 V
5.5 V
1.65 V
2.3 V
ΔVT
Hysteresis
3 V
(VT+ –VT–
)
4.5 V
5.5 V
1.65 V to 4.5 V
1.65 V
2.3 V
IOL = –100 µA
IOL = –4 mA
IOL = –8 mA
IOL = –16 mA
IOL = –24 mA
IOL = –32 mA
IOL = 100 µA
IOL = 4 mA
1.9
VOH
V
2.4
3 V
2.3
4.5 V
1.65 V to 4.5 V
1.65 V
3.8
0.1
0.45
0.3
IOL = 8 mA
2.3 V
VOL
V
IOL = 16 mA
0.4
3 V
IOL = 24 mA
0.55
0.70
±5
IOL = 32 mA
4.5 V
0 to 5.5 V
0
II
A input
VI = 5.5 V or GND
VI or VO = 5.5 V
VI = 5.5 V or GND,
µA
µA
µA
µA
Ioff
±10
10
ICC
ΔICC
IO = 0
1.65 V to 5.5 V
3 V to 5.5 V
Other inputs at VCC or GND
500
One input at VCC –0.6 V,
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6.5 Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN TYP(1) MAX
UNIT
Ci
VI = VCC or GND
3.3 V
4.5
pF
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
6.6 Switching Characteristics, CL = 15 pF
over recommended operating free-air temperature range (unless otherwise noted) (see 图7-1)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX MIN MAX
9.9 1.6 5.5
MIN MAX
MIN MAX
tpd
A
Y
2.8
1.5
4.6
0.9
4.4
ns
6.7 Switching Characteristics, CL = 30 pF or 50 pF
over recommended operating free-air temperature range (unless otherwise noted) (see 图7-2)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX MIN MAX
13
MIN MAX
MIN MAX
tpd
A
Y
3.8
2
8
1.8
6.5
1.2
6
ns
6.8 Operating Characteristics
TA = 25°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
VCC = 5 V
TYP
PARAMETER
TEST CONDITIONS
UNIT
TYP
TYP
TYP
Cpd Power dissipation capacitance
f = 10 MHz
20
21
22
25
pF
6.9 Typical Characteristics
8
7
6
5
4
3
2
1
3.8
3.7
3.6
3.5
3.4
3.3
3.2
3.1
TPD
TPD
0
0
-100
-50
0
50
100
150
1
2
3
VCC (V)
4
5
6
Temperature (°C)
D001
D002
图6-2. TPD Across VCC at 25°C
图6-1. TPD Across Temperature at 3.3 V VCC
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7 Parameter Measurement Information
V
LOAD
S1
Open
R
L
From Output
Under Test
TEST
/t
S1
GND
t
t
Open
PLH PHL
C
L
t
/t
PLZ PZL
V
R
L
LOAD
GND
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
LOAD
C
L
R
L
V
D
V
I
t /t
r f
1.8 V 0.15 V
2.5 V 0.2 V
3.3 V 0.3 V
5 V 0.5 V
V
V
≤2 ns
≤2 ns
V
/2
/2
2 × V
2 × V
15 pF
15 pF
15 pF
15 pF
1 MW
1 MW
1 MW
1 MW
0.15 V
0.15 V
0.3 V
CC
CC
CC
V
CC
CC
CC
3 V
≤2.5 ns
≤2.5 ns
1.5 V
/2
6 V
2 × V
CC
V
CC
V
CC
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
h
su
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
0 V
t
t
t
t
t
PHL
PZL
PLZ
PLH
Output
V
V
OH
V
V
/2
LOAD
Waveform 1
S1 at V
V
V
V
M
M
Output
V
V
M
LOAD
V
+ V
D
OL
OL
(see Note B)
OL
t
PHL
PLH
t
t
PHZ
PZH
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
− V
D
V
M
OH
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, Z = 50 W.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
t
and t
and t
are the same as t .
dis
PLZ
PZL
PLH
PHZ
t
are the same as t .
en
PZH
G.
t
and t
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
图7-1. Load Circuit and Voltage Waveforms
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V
LOAD
S1
Open
R
L
From Output
Under Test
TEST
/t
S1
GND
t
t
Open
PLH PHL
C
L
t
/t
PLZ PZL
V
R
L
LOAD
GND
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
LOAD
C
L
R
L
V
D
V
I
t /t
r f
1.8 V 0.15 V
2.5 V 0.2 V
3.3 V 0.3 V
5 V 0.5 V
V
V
≤2 ns
≤2 ns
V
/2
/2
2 × V
2 × V
30 pF
30 pF
50 pF
50 pF
1 kW
500 W
500 W
500 W
0.15 V
0.15 V
0.3 V
CC
CC
CC
V
CC
CC
CC
3 V
≤2.5 ns
≤2.5 ns
1.5 V
/2
6 V
2 × V
CC
V
CC
V
CC
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
h
su
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
0 V
t
t
t
t
t
PHL
PZL
PLZ
PLH
Output
V
V
OH
V
V
/2
LOAD
Waveform 1
S1 at V
V
V
V
M
M
Output
V
V
M
LOAD
V
+ V
D
OL
OL
(see Note B)
OL
t
PHL
PLH
t
t
PHZ
PZH
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
− V
D
V
M
OH
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, Z = 50 W.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
t
and t
and t
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
t
are the same as t
.
PZH
en
G.
t
and t
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
图7-2. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SN74LVC1G14-Q1 device contains one Schmitt Trigger Inverter and performs the Boolean function Y = A.
The device functions as an independent inverter, but because of Schmitt Trigger action, it will have different input
threshold levels for a positive-going (Vt+) and negative-going (Vt-) signals.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuit disables the output,
preventing damaging current back-flow through the device when it is powered down.
8.2 Functional Block Diagram
2
4
A
Y
8.3 Feature Description
• Wide operating voltage range
• Operates from 1.65 V to 5 V VCC and Input Operation
• Inputs Accept Voltages to 5.5 V
• Allows down voltage translation
• ±24-mA Output Drive at 3.3 V
• Ioff Supports Partial-Power-Down Mode Operation which allows voltages on the inputs and outputs, when VCC
is 0 V
8.4 Device Functional Modes
表8-1 shows the functional modes of the SN74LVC1G14-Q1 device.
表8-1. Function Table
INPUT
A
OUTPUT
Y
H
L
L
H
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The SN74LVC1G14-Q1 is a high drive CMOS device that can be used for a multitude of buffer type functions
where the input is slow or noisy. It can produce 24 mA of drive current at 3.3 V making it ideal for driving multiple
outputs and good for high speed applications up to 100 MHz. The inputs are 5.5-V tolerant allowing it to translate
down to VCC
.
9.2 Typical Application
RF
~2.2 MΩ
SN74LVC1G14-Q1
C
RS
50 pF
~1 kΩ
CL
C1
C2
16 pF
~32 pF
~32 pF
Copyright © 2017, Texas Instruments Incorporated
图9-1. Typical Application Schematic
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads
so routing and load conditions should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions
• Rise time and fall time specs. See (Δt/ΔV) in the Recommended Operating Conditions table.
• Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table.
• Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended Operating
Conditions table at any valid VCC
.
2. Recommended Output Conditions
• Load currents should not exceed (IO max) per output and should not exceed (continuous current through
VCC or GND) total current for the part. These limits are located in the Absolute Maximum Ratings table.
• Outputs should not be pulled above VCC
.
Copyright © 2022 Texas Instruments Incorporated
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SN74LVC1G14-Q1
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www.ti.com.cn
9.2.3 Application Curve
10
9
8
7
6
5
4
3
2
1
0
Icc 1.8V
Icc 2.5V
Icc 3.3V
Icc 5V
0
20
40
Frequency - MHz
60
80
D003
图9-2. ICC vs Frequency
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply a 0.1-µF capacitor is recommended and if there are multiple VCC pins then a 0.01-µF or 0.022-µF
capacitor is recommended for each power pin. It is ok to parallel multiple bypass capacitors to reject different
frequencies of noise. 0.1-µF and 1-µF capacitors are commonly used in parallel. The bypass capacitor should be
installed as close to the power pin as possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions
of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only
3 of the 4 buffer gates are used. Such input terminals should not be left unconnected because the undefined
voltages at the outside connections result in undefined operational states. Specified below are the rules that
must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high
or low bias to prevent them from floating. The logic level that should be applied to any particular unused input
depends on the function of the device. Generally they will be tied to GND or VCC whichever make more sense or
is more convenient.
11.2 Layout Example
V
Input
CC
Unused Input
Output
Unused Input
Output
Input
图11-1. Layout Schematic
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SN74LVC1G14-Q1
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12 Device and Documentation Support
12.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
12
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重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
7-Apr-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN74LVC1G14QDCKRQ1
SN74LVC1G14QDRYRQ1
ACTIVE
ACTIVE
SC70
SON
DCK
DRY
5
6
3000 RoHS & Green
5000 RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
(SJJ, SJM)
FE
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Apr-2022
OTHER QUALIFIED VERSIONS OF SN74LVC1G14-Q1 :
Catalog : SN74LVC1G14
•
Enhanced Product : SN74LVC1G14-EP
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC1G14QDCKRQ1 SC70
SN74LVC1G14QDRYRQ1 SON
DCK
DRY
5
6
3000
5000
178.0
180.0
9.0
9.5
2.4
1.2
2.5
1.2
0.7
4.0
4.0
8.0
8.0
Q3
Q1
1.65
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LVC1G14QDCKRQ1
SN74LVC1G14QDRYRQ1
SC70
SON
DCK
DRY
5
6
3000
5000
190.0
189.0
190.0
185.0
30.0
36.0
Pack Materials-Page 2
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DRY 6
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4207181/G
PACKAGE OUTLINE
DRY0006B
USON - 0.55 mm max height
S
C
A
L
E
8
.
5
0
0
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
A
B
PIN 1 INDEX AREA
1.5
1.4
C
0.55 MAX
SEATING PLANE
0.08 C
0.05
0.00
3X 0.6
SYMM
(0.127) TYP
(0.05) TYP
3
4
4X
0.5
SYMM
2X
1
6
1
0.25
6X
0.15
PIN 1 ID
(OPTIONAL)
0.1
C A
C
B
0.05
0.35
0.25
6X
4222207/B 02/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DRY0006B
USON - 0.55 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
6X (0.3)
1
6
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(0.6)
LAND PATTERN EXAMPLE
1:1 RATIO WITH PKG SOLDER PADS
SCALE:40X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222207/B 02/2016
NOTES: (continued)
3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DRY0006B
USON - 0.55 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
6X (0.3)
1
6
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(0.6)
SOLDER PASTE EXAMPLE
BASED ON 0.075 - 0.1 mm THICK STENCIL
SCALE:40X
4222207/B 02/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
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