SN74LVC1G08DRYR [TI]
SINGLE 2-INPUT POSITIVE-AND GATE; 单路2输入正与门![SN74LVC1G08DRYR](http://pdffile.icpdf.com/pdf1/p00100/img/icpdf/SN74LVC1G08_534797_icpdf.jpg)
型号: | SN74LVC1G08DRYR |
厂家: | ![]() |
描述: | SINGLE 2-INPUT POSITIVE-AND GATE |
文件: | 总17页 (文件大小:598K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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SN74LVC1G08
SINGLE 2-INPUT POSITIVE-AND GATE
www.ti.com
SCES217T–APRIL 1999–REVISED FEBRUARY 2007
FEATURES
•
Available in the Texas Instruments
NanoFree™ Package
•
•
•
Ioff Supports Partial-Power-Down Mode
Operation
•
•
•
•
•
Supports 5-V VCC Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Inputs Accept Voltages to 5.5 V
Max tpd of 3.6 ns at 3.3 V
ESD Protection Exceeds JESD 22
–
–
–
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
Low Power Consumption, 10-µA Max ICC
±24-mA Output Drive at 3.3 V
1000-V Charged-Device Model (C101)
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
DRL PACKAGE
(TOP VIEW)
1
2
3
5
4
A
B
VCC
1
2
3
5
A
B
VCC
1
2
3
5
4
VCC
A
B
GND
Y
4
GND
Y
GND
Y
DRY PACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOM VIEW)
3
2
1
4
GND
B
Y
1
2
3
6
5
4
A
B
VCC
NC
Y
5
A
VCC
GND
NC – No internal connection
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
Y = A • B or Y = A + B
The SN74LVC1G08 performs the Boolean function or
in positive logic.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1999–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LVC1G08
SINGLE 2-INPUT POSITIVE-AND GATE
www.ti.com
SCES217T–APRIL 1999–REVISED FEBRUARY 2007
ORDERING INFORMATION
ORDERABLE PART
TA
PACKAGE(1)
TOP-SIDE MARKING(2)
NUMBER
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP
(Pb-free)
Reel of 3000
SN74LVC1G08YZPR
_ _ _CE_
SON – DRY
Reel of 5000
Reel of 3000
Reel of 250
Reel of 3000
Reel of 250
Reel of 4000
SN74LVC1G08DRYR
SN74LVC1G08DBVR
SN74LVC1G08DBVT
SN74LVC1G08DCKR
SN74LVC1G08DCKT
SN74LVC1G08DRLR
CE _
C08_
–40°C to 85°C
SOT (SOT-23) – DBV
SOT (SC-70) – DCK
CE_
SOT (SOT-553) – DRL
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DBV/DCK/DRL/DRY: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
FUNCTION TABLE
INPUTS
OUTPUT
Y
A
H
L
B
H
X
L
H
L
L
X
LOGIC DIAGRAM (POSITIVE LOGIC)
2
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SN74LVC1G08
SINGLE 2-INPUT POSITIVE-AND GATE
www.ti.com
SCES217T–APRIL 1999–REVISED FEBRUARY 2007
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
–0.5
MAX
6.5
UNIT
V
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high or low state(2)(3)
6.5
V
VO
VO
IIK
6.5
V
VCC + 0.5
–50
V
Input clamp current
VI < 0
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
–50
Continuous ouput current
Continuous current through VCC or GND
±50
±100
206
DBV package
DCK package
DRL package
DRY package
YZP package
252
θJA
Package thermal impedance(4)
142
°C/W
°C
234
132
Tstg
Storage temperature range
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
3
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SN74LVC1G08
SINGLE 2-INPUT POSITIVE-AND GATE
www.ti.com
SCES217T–APRIL 1999–REVISED FEBRUARY 2007
Recommended Operating Conditions(1)
MIN
1.65
MAX UNIT
Operating
5.5
V
VCC Supply voltage
Data retention only
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
1.5
0.65 × VCC
1.7
VIH
High-level input voltage
Low-level input voltage
V
2
0.7 × VCC
0.35 × VCC
0.7
VIL
V
0.8
0.3 × VCC
5.5
VCC
–4
VI
Input voltage
0
0
V
V
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
–8
IOH
High-level output current
Low-level output current
–16
–24
–32
4
mA
mA
VCC = 3 V
VCC = 4.5 V
VCC = 1.65 V
VCC = 2.3 V
8
IOL
16
VCC = 3 V
24
VCC = 4.5 V
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
20
∆t/∆v Input transition rise or fall rate
10
ns/V
5
TA
Operating free-air temperature
–40
85
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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SN74LVC1G08
SINGLE 2-INPUT POSITIVE-AND GATE
www.ti.com
SCES217T–APRIL 1999–REVISED FEBRUARY 2007
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 5.5 V
1.65 V
MIN TYP(1)
VCC – 0.1
MAX UNIT
IOH = –100 µA
IOH = –4 mA
IOH = –8 mA
IOH = –16 mA
IOH = –24 mA
IOH = –32 mA
IOL = 100 µA
IOL = 4 mA
1.2
1.9
2.4
2.3
3.8
2.3 V
VOH
V
3 V
4.5 V
1.65 V to 5.5 V
1.65 V
0.1
0.45
IOL = 8 mA
2.3 V
0.3
V
VOL
IOL = 16 mA
IOL = 24 mA
IOL = 32 mA
VI = 5.5 V or GND
VI or VO = 5.5 V
0.4
3 V
0.55
0.55
4.5 V
0 to 5.5 V
0
II
A or B inputs
±5
±10
10
µA
µA
µA
µA
pF
Ioff
ICC
VI = 5.5 V or GND,
IO = 0
1.65 V to 5.5 V
3 V to 5.5 V
3.3 V
∆ICC
One input at VCC – 0.6 V, Other inputs at VCC or GND
VI = VCC or GND
500
Ci
4
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
Switching Characteristics
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
7.2
MIN
MAX
4.4
MIN MAX
MIN MAX
0.8 3.4
tpd
A or B
Y
1.5
0.7
0.8
3.6
ns
Switching Characteristics
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN MAX
MIN
MAX
tpd
A or B
Y
2.4
8
1.1
5.5
1
4.5
1
4
ns
Operating Characteristics
TA = 25°C
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
VCC = 3.3 V VCC = 5 V
TEST
CONDITIONS
PARAMETER
UNIT
TYP
TYP
Cpd
Power dissipation capacitance
f = 10 MHz
21
24
26
31
pF
5
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SN74LVC1G08
SINGLE 2-INPUT POSITIVE-AND GATE
www.ti.com
SCES217T–APRIL 1999–REVISED FEBRUARY 2007
PARAMETER MEASUREMENT INFORMATION
VLOAD
Open
S1
RL
From Output
Under Test
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
GND
Open
VLOAD
GND
CL
(see Note A)
RL
LOAD CIRCUIT
INPUTS
VCC
VM
VLOAD
CL
RL
V
D
VI
tr/tf
VCC
VCC
3 V
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
£2 ns
£2 ns
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6 V
15 pF
15 pF
15 pF
15 pF
1 MW
0.15 V
0.15 V
0.3 V
1 MW
1 MW
1 MW
£2.5 ns
£2.5 ns
2 × VCC
0.3 V
VI
Timing Input
Data Input
VM
0 V
tW
tsu
th
VI
VI
Input
VM
VM
VM
VM
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VI
Output
Control
VM
VM
Input
VM
VM
0 V
0 V
tPZL
tPLZ
tPLH
tPHL
VM
Output
Waveform 1
S1 at VLOAD
VOH
VOL
VLOAD/2
VM
VM
Output
Output
VOL + V
D
VOL
(see Note B)
tPHL
tPLH
tPZH
tPHZ
VOH
VOL
Output
Waveform 2
S1 at GND
VOH
VOH – V
D
VM
VM
VM
»0 V
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
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SN74LVC1G08
SINGLE 2-INPUT POSITIVE-AND GATE
www.ti.com
SCES217T–APRIL 1999–REVISED FEBRUARY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
VLOAD
Open
S1
RL
From Output
Under Test
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
GND
Open
VLOAD
GND
CL
(see Note A)
RL
LOAD CIRCUIT
INPUTS
VCC
VM
VLOAD
CL
RL
V
D
VI
tr/tf
VCC
VCC
3 V
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
£2 ns
£2 ns
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6 V
30 pF
30 pF
50 pF
50 pF
1 kW
0.15 V
0.15 V
0.3 V
500 W
500 W
500 W
£2.5 ns
£2.5 ns
2 × VCC
0.3 V
VI
Timing Input
Data Input
VM
0 V
tW
tsu
th
VI
VI
Input
VM
VM
VM
VM
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VI
Output
Control
VM
VM
Input
VM
VM
0 V
0 V
tPZL
tPLZ
tPLH
tPHL
VM
Output
Waveform 1
S1 at VLOAD
VOH
VOL
VLOAD/2
VOL
VM
VM
Output
Output
VOL + V
D
(see Note B)
tPHL
tPLH
tPZH
tPHZ
VOH
VOL
Output
Waveform 2
S1 at GND
VOH
VOH – V
D
VM
VM
VM
»0 V
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
7
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PACKAGE OPTION ADDENDUM
www.ti.com
22-Oct-2007
PACKAGING INFORMATION
Orderable Device
SN74LVC1G08DBVR
SN74LVC1G08DBVRE4
SN74LVC1G08DBVRG4
SN74LVC1G08DBVT
SN74LVC1G08DBVTE4
SN74LVC1G08DBVTG4
SN74LVC1G08DCKR
SN74LVC1G08DCKRE4
SN74LVC1G08DCKRG4
SN74LVC1G08DCKT
SN74LVC1G08DCKTE4
SN74LVC1G08DCKTG4
SN74LVC1G08DRLR
SN74LVC1G08DRLRG4
SN74LVC1G08DRYR
SN74LVC1G08DRYRG4
SN74LVC1G08YZPR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOT-23
DBV
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
5
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SC70
SC70
SC70
SC70
SC70
SC70
SOT
DBV
DBV
DBV
DBV
DBV
DCK
DCK
DCK
DCK
DCK
DCK
DRL
DRL
DRY
DRY
YZP
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
4000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOT
4000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SON
5000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SON
5000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
WCSP
3000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
22-Oct-2007
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
180
0
(mm)
SN74LVC1G08DBVR
SN74LVC1G08DBVR
SN74LVC1G08DBVT
SN74LVC1G08DBVT
SN74LVC1G08DCKR
SN74LVC1G08DCKT
SN74LVC1G08DRLR
SN74LVC1G08DRYR
SN74LVC1G08YZPR
SN74LVC1G08YZPR
DBV
DBV
DBV
DBV
DCK
DCK
DRL
DRY
YZP
YZP
5
5
5
5
5
5
5
6
5
5
SITE 34
SITE 45
SITE 34
SITE 45
SITE 34
SITE 34
SITE 35
SITE 48
SITE 55
SITE 12
9
0
3.23
3.23
3.23
10.6
2.24
2.24
1.78
1.2
3.17
3.17
3.17
15.8
2.34
2.34
1.78
1.65
1.52
1.52
1.37
1.37
1.37
4.9
4
4
8
8
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q1
Q1
Q1
180
330
180
180
180
179
180
180
9
4
8
16
9
16
4
24
8
1.22
1.22
0.69
0.7
9
4
8
9
4
8
8
4
8
8
1.02
1.02
0.66
0.66
4
8
8
4
8
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
SN74LVC1G08DBVR
SN74LVC1G08DBVR
SN74LVC1G08DBVT
SN74LVC1G08DBVT
SN74LVC1G08DCKR
SN74LVC1G08DCKT
SN74LVC1G08DRLR
SN74LVC1G08DRYR
SN74LVC1G08YZPR
SN74LVC1G08YZPR
DBV
DBV
DBV
DBV
DCK
DCK
DRL
DRY
YZP
YZP
5
5
5
5
5
5
5
6
5
5
SITE 34
SITE 45
SITE 34
SITE 45
SITE 34
SITE 34
SITE 35
SITE 48
SITE 55
SITE 12
205.0
0.0
200.0
185.0
192.0
0.0
33.0
220.0
26.0
0.0
201.0
0.0
205.0
201.0
202.0
220.0
220.0
220.0
200.0
192.0
201.0
205.0
220.0
220.0
33.0
26.0
28.0
50.0
34.0
0.0
Pack Materials-Page 2
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