SN74LVC157ADBR [TI]
QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS; 四路2号线到1线数据选择器/多路复用器
| 型号： | SN74LVC157ADBR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS |
| 文件： | 总16页 (文件大小：551K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢂ ꢃ ꢄꢅꢆꢇ ꢂ ꢈ ꢉꢊ ꢀꢁꢈ ꢃꢄꢅ ꢆꢇ ꢂꢈ ꢉ
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SCAS292O − JANUARY 1993 − REVISED FEBRUARY 2004
D
D
D
D
D
Operate From 1.65 V to 3.6 V
D
D
D
Typical V
(Output V
Undershoot)
OHV
OH
>2 V at V
= 3.3 V, T = 25°C
CC
A
Specified From −40°C to 85°C,
−40°C to 125°C, and −55°C to 125°C
Inputs Accept Voltages to 5.5 V
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
Max t of 5.2 ns at 3.3 V
pd
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
= 3.3 V, T = 25°C
A
− 1000-V Charged-Device Model (C101)
SN54LVC157A . . . J OR W PACKAGE
SN74LVC157A . . . D, DB, NS,
OR PW PACKAGE
SN74LVC157A . . . RGY PACKAGE
(TOP VIEW)
SN54LVC157A . . . FK PACKAGE
(TOP VIEW)
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
G
A/B
1A
1B
1Y
2A
2B
2Y
GND
1
16
CC
3
2
1 20 19
18
1A
1B
1Y
2A
2B
2Y
1B
1Y
NC
2A
2B
4A
4B
NC
2
3
4
5
6
7
G
4
5
6
7
8
15
14
13
17
16
4A
4B
4A
4B
4Y
3A
3B
3Y
15 4Y
12 4Y
14
9 10 11 12 13
3A
11
10
3A
3B
8
9
NC − No internal connection
description/ordering information
These quadruple 2-line to 1-line data selectors/multiplexers are designed for 1.65-V to 3.6-V V
operation.
CC
The ’LVC157A devices feature a common strobe (G) input. When G is high, all outputs are low. When G is low,
a 4-bit word is selected from one of two sources and is routed to the four outputs. The devices provide true data.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
−40°C to 85°C
QFN − RGY
SOIC − D
Reel of 1000
Tube of 40
SN74LVC157ARGYR
SN74LVC157AD
LC157A
Reel of 2500
Reel of 250
Reel of 2000
Reel of 2000
Tube of 90
SN74LVC157ADR
SN74LVC157ADT
SN74LVC157ANSR
SN74LVC157ADBR
SN74LVC157APW
SN74LVC157APWR
SN74LVC157APWT
SNJ54LVC157AJ
SNJ54LVC157AW
SNJ54LVC157AFK
LVC157A
SOP − NS
LVC157A
LC157A
−40°C to 125°C
SSOP − DB
Reel of 2000
Reel of 250
Tube of 25
TSSOP − PW
LC157A
CDIP − J
CFP − W
LCCC − FK
SNJ54LVC157AJ
SNJ54LVC157AW
SNJ54LVC157AFK
Tube of 150
Tube of 55
−55°C to 125°C
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
ꢕ ꢚ ꢥ ꢝ ꢜꢨ ꢣꢢ ꢠꢡ ꢢꢜ ꢞꢥ ꢧꢙ ꢟꢚ ꢠ ꢠꢜ ꢗꢓ ꢄꢒ ꢏꢎ ꢯ ꢒꢰꢱꢂ ꢰꢂꢊ ꢟꢧꢧ ꢥꢟ ꢝ ꢟ ꢞꢤ ꢠꢤꢝ ꢡ ꢟ ꢝ ꢤ ꢠꢤ ꢡꢠꢤ ꢨ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢂꢈ ꢉ ꢊ ꢀ ꢁꢈ ꢃ ꢄꢅ ꢆꢇ ꢂ ꢈꢉ
ꢋꢌ ꢉ ꢍꢎ ꢌ ꢏꢄ ꢐ ꢑ ꢒꢄꢓ ꢁ ꢐ ꢔ ꢕ ꢇ ꢒꢄꢓ ꢁ ꢐ ꢍꢉꢔꢉ ꢀꢐ ꢄꢐ ꢆꢔꢕ ꢎꢀꢖ ꢗꢌ ꢄꢔ ꢓꢏ ꢄꢐ ꢘꢐꢎꢀ
SCAS292O − JANUARY 1993 − REVISED FEBRUARY 2004
description/ordering information (continued)
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
FUNCTION TABLE
INPUTS
OUTPUT
Y
G
H
L
A/B
X
A
X
L
B
X
X
X
L
L
L
L
L
L
H
X
X
H
L
L
H
L
H
H
H
logic diagram (positive logic)
2
1A
4
1Y
2Y
3Y
4Y
3
1B
5
2A
7
9
6
2B
11
3A
10
3B
14
4A
12
13
4B
15
G
1
A/B
Pin numbers shown are for the D, DB, J, NS, PW, RGY, and W packages.
2
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ꢋ ꢌꢉꢍ ꢎꢌꢏ ꢄ ꢐ ꢑ ꢒꢄ ꢓꢁꢐ ꢔ ꢕ ꢇ ꢒꢄ ꢓꢁꢐ ꢍꢉꢔꢉ ꢀꢐ ꢄꢐ ꢆꢔꢕ ꢎꢀꢖ ꢗꢌ ꢄꢔ ꢓ ꢏꢄ ꢐꢘ ꢐ ꢎꢀ
SCAS292O − JANUARY 1993 − REVISED FEBRUARY 2004
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
I
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
OK
O
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous current through V
O
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CC
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
(see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
Power dissipation, P (T = −40°C to 125°C) (see Notes 5 and 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW
tot
A
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of V is provided in the recommended operating conditions table.
CC
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
5. For the D package, above 70°C the value of P derates linearly with 8 mW/K.
tot
6. For the DB, NS, and PW packages, above 60°C the value of P derates linearly with 5.5 mW/K.
tot
3
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ꢋꢌ ꢉ ꢍꢎ ꢌ ꢏꢄ ꢐ ꢑ ꢒꢄꢓ ꢁ ꢐ ꢔ ꢕ ꢇ ꢒꢄꢓ ꢁ ꢐ ꢍꢉꢔꢉ ꢀꢐ ꢄꢐ ꢆꢔꢕ ꢎꢀꢖ ꢗꢌ ꢄꢔ ꢓꢏ ꢄꢐ ꢘꢐꢎꢀ
SCAS292O − JANUARY 1993 − REVISED FEBRUARY 2004
recommended operating conditions (see Note 7)
SN54LVC157A
−55 TO 125°C
UNIT
MIN
2
MAX
Operating
3.6
V
Supply voltage
V
CC
Data retention only
1.5
2
V
V
V
V
High-level input voltage
Low-level input voltage
Input voltage
V
V
= 2.7 V to 3.6 V
V
V
V
V
IH
IL
I
CC
= 2.7 V to 3.6 V
0.8
5.5
CC
0
0
Output voltage
V
CC
O
V
CC
V
CC
V
CC
V
CC
= 2.7 V
= 3 V
−12
−24
12
I
High-level output current
Low-level output current
mA
mA
OH
OL
= 2.7 V
= 3 V
I
24
NOTE 7: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
recommended operating conditions (see Note 7)
SN74LVC157A
T
= 25°C
−40 TO 85°C
−40 TO 125°C
UNIT
V
A
MIN
MAX
MIN
MAX
MIN
MAX
Operating
1.65
1.5
3.6
1.65
1.5
3.6
1.65
1.5
3.6
V
V
Supply voltage
CC
Data retention only
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
0.65 × V
0.65 × V
1.7
0.65 × V
1.7
CC
CC
CC
High-level input
voltage
1.7
2
V
IH
2
2
0.35 × V
0.7
0.35 × V
0.7
0.35 × V
0.7
CC
CC
CC
Low-level input
voltage
V
IL
V
0.8
0.8
0.8
V
V
Input voltage
0
0
5.5
0
0
5.5
0
0
5.5
V
V
I
Output voltage
V
V
V
O
CC
−4
CC
−4
CC
−4
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V
= 2.3 V
= 2.7 V
= 3 V
−8
−8
−8
High-level
output current
I
mA
OH
OL
−12
−24
4
−12
−24
4
−12
−24
4
= 1.65 V
= 2.3 V
= 2.7 V
= 3 V
8
8
8
Low-level
output current
I
mA
12
24
12
24
12
24
∆t/∆v
Input transition rise or fall rate
10
10
10
ns/V
NOTE 7: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅꢆꢇ ꢂ ꢈ ꢉꢊ ꢀꢁꢈ ꢃꢄꢅ ꢆꢇ ꢂꢈ ꢉ
ꢋ ꢌꢉꢍ ꢎꢌꢏ ꢄ ꢐ ꢑ ꢒꢄ ꢓꢁꢐ ꢔ ꢕ ꢇ ꢒꢄ ꢓꢁꢐ ꢍꢉꢔꢉ ꢀꢐ ꢄꢐ ꢆꢔꢕ ꢎꢀꢖ ꢗꢌ ꢄꢔ ꢓ ꢏꢄ ꢐꢘ ꢐ ꢎꢀ
SCAS292O − JANUARY 1993 − REVISED FEBRUARY 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVC157
A
PARAMETER
TEST CONDITIONS
UNIT
V
CC
−55 TO 125°C
MIN
−0.2
MAX
I
I
= −100 µA
2.7 V to 3.6 V
2.7 V
V
OH
CC
2.2
V
V
= −12 mA
V
V
OH
OH
3 V
2.4
2.2
I
I
I
I
= −24 mA
= 100 µA
= 12 mA
= 24 mA
3 V
OH
OL
OL
OL
2.7 V to 3.6 V
2.7 V
0.2
0.4
0.55
5
OL
3 V
I
I
All inputs V = 5.5 V or GND
3.6 V
µA
µA
µA
I
I
V = V
CC
or GND
I = 0
O
3.6 V
10
CC
I
∆I
CC
One input at V
CC
− 0.6 V, Other inputs at V
or GND
2.7 V to 3.6 V
500
CC
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN74LVC157A
T
A
= 25°C
−40 TO 85°C −40 TO 125°C
PARAMETER
TEST CONDITIONS
UNIT
V
CC
MIN
−0.2
TYP
MAX
MIN
−0.2
MAX
MIN
MAX
I
I
I
= −100 µA
= −4 mA
= −8 mA
1.65 V to 3.6 V
1.65 V
2.3 V
V
CC
V
V
−0.3
OH
OH
OH
CC
1.2
CC
1.29
1.9
2.2
2.4
2.3
1.05
1.7
2.2
2.4
2.2
1.55
2.05
2.25
2
V
V
OH
OL
2.7 V
I
= −12 mA
OH
3 V
I
I
I
I
I
I
= −24 mA
= 100 µA
= 4 mA
3 V
OH
OL
OL
OL
OL
OL
1.65 V to 3.6 V
1.65 V
2.3 V
0.1
0.24
0.3
0.4
0.55
1
0.2
0.45
0.7
0.4
0.55
5
0.3
0.6
0.75
0.6
0.8
20
= 8 mA
V
V
= 12 mA
= 24 mA
2.7 V
3 V
I
I
All inputs V = 5.5 V or GND
3.6 V
µA
µA
I
I
V = V
or GND
I
CC
I
O
= 0
3.6 V
1
10
40
CC
One input at V
Other inputs at V
CC
− 0.6 V,
or GND
CC
∆I
CC
2.7 V to 3.6 V
3.3 V
500
500
5000
µA
C
V = V
I CC
or GND
5
pF
i
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢂꢈ ꢉ ꢊ ꢀ ꢁꢈ ꢃ ꢄꢅ ꢆꢇ ꢂ ꢈꢉ
ꢋꢌ ꢉ ꢍꢎ ꢌ ꢏꢄ ꢐ ꢑ ꢒꢄꢓ ꢁ ꢐ ꢔ ꢕ ꢇ ꢒꢄꢓ ꢁ ꢐ ꢍꢉꢔꢉ ꢀꢐ ꢄꢐ ꢆꢔꢕ ꢎꢀꢖ ꢗꢌ ꢄꢔ ꢓꢏ ꢄꢐ ꢘꢐꢎꢀ
SCAS292O − JANUARY 1993 − REVISED FEBRUARY 2004
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
SN54LVC157A
FROM
(INPUT)
TO
(OUTPUT)
−55 TO 125°C
PARAMETER
V
UNIT
CC
MIN
MAX
6.2
2.7 V
3.3 V 0.3 V
2.7 V
A or B
A/B
G
0.8
5.4
8.2
7
Y
t
pd
ns
0.8
0.8
3.3 V 0.3 V
2.7 V
7.8
6.5
3.3 V 0.3 V
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
SN74LVC157A
FROM
(INPUT)
TO
(OUTPUT)
T
A
= 25°C
TYP
5.5
3.2
3.6
3
−40 TO 85°C −40 TO 125°C
PARAMETER
V
UNIT
CC
MIN
1
MAX
13.5
7.4
5.7
5
MIN
1
MAX
14
MIN
1
MAX
15.5
10
1.8 V 0.15 V
2.5 V 0.2 V
2.7 V
1
1
7.9
5.9
5.2
16
1
A or B
A/B
G
1
1
1
7.4
1
1
1
6.4
3.3 V 0.3 V
1.8 V 0.15 V
2.5 V 0.2 V
2.7 V
1
6
15.5
9.6
7.9
6.6
13.5
9.3
7.6
6.3
1
1
17.5
12.2
10
1
3.7
4.1
3.4
5.9
3.5
3.9
3.3
1
10.1
8.1
6.8
14
1
Y
t
pd
ns
1
1
1
1
1
1
8.4
3.3 V 0.3 V
1.8 V 0.15 V
2.5 V 0.2 V
2.7 V
1
1
1
15.5
11.9
9.3
1
1
9.8
7.8
6.5
2
1
1
1
1
1
1
1
7.9
3.3 V 0.3 V
1.8 V 0.15 V
2.5
t
ns
sk(o)
3.3 V 0.3 V
1
1.5
operating characteristics, T = 25°C
A
TEST
CONDITIONS
PARAMETER
V
CC
TYP
UNIT
1.8 V
2.5 V
3.3 V
14*
15*
16
C
Power dissipation capacitance
f = 10 MHz
pF
pd
* On products compliant to MIL-PRF-38535, this parameter does not apply.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅꢆꢇ ꢂ ꢈ ꢉꢊ ꢀꢁꢈ ꢃꢄꢅ ꢆꢇ ꢂꢈ ꢉ
ꢋ ꢌꢉꢍ ꢎꢌꢏ ꢄ ꢐ ꢑ ꢒꢄ ꢓꢁꢐ ꢔ ꢕ ꢇ ꢒꢄ ꢓꢁꢐ ꢍꢉꢔꢉ ꢀꢐ ꢄꢐ ꢆꢔꢕ ꢎꢀꢖ ꢗꢌ ꢄꢔ ꢓ ꢏꢄ ꢐꢘ ꢐ ꢎꢀ
SCAS292O − JANUARY 1993 − REVISED FEBRUARY 2004
PARAMETER MEASUREMENT INFORMATION
V
LOAD
Open
S1
R
L
From Output
Under Test
TEST
S1
GND
t
t
/t
Open
PLH PHL
/t
C
L
t
V
R
PLZ PZL
LOAD
GND
L
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
C
R
L
V
LOAD
L
∆
V
I
t /t
r f
1.8 V 0.15 V
2.5 V 0.2 V
2.7 V
V
V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
V
V
/2
/2
2 × V
2 × V
6 V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
CC
CC
CC
CC
CC
CC
2.7 V
2.7 V
1.5 V
1.5 V
3.3 V 0.3 V
6 V
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
su
h
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
V
0 V
t
t
t
t
t
PHL
PZL
PLZ
+ V
PLH
PHL
Output
Waveform 1
V
/2
OH
LOAD
V
V
V
M
Output
M
V
V
M
S1 at V
(see Note B)
V
LOAD
OL
∆
V
OL
V
OL
t
PLH
t
t
PZH
PHZ
− V
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
V
M
OH
∆
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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