SN74LV594A-Q1 [TI]
具有输出寄存器的汽车类八位移位寄存器;
| 型号： | SN74LV594A-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有输出寄存器的汽车类八位移位寄存器 移位寄存器 |
| 文件： | 总25页 (文件大小：1912K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LV594A-Q1
ZHCSPK4 –DECEMBER 2022
SN74LV594A-Q1 汽车类8 位并行输出串行移位寄存器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准：
SN74LV594A-Q1 器件是 8 位移位寄存器，可在 2V 至
5.5V VCC 下运行。
– 器件温度等级1：–40°C 至+125°C，TA
– 器件HBM ESD 分类等级2
封装信息(1)
– 器件CDM ESD 分类等级C6
• 采用可湿侧面QFN (WBQB) 封装
• 2 V 至5.5 V VCC 运行
封装尺寸（标称值）
器件型号
封装
SN74LV594A-Q1
BQB（WQFN，16） 3.60mm × 2.60mm
• 5V 时tpd 最大值为6.5ns
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• VOLP（输出接地反弹）典型值小于0.8V（VCC
3.3V、TA = 25°C 时）
• 支持所有端口上的混合模式电压运行
• 具有存储功能的8 位串行输入、并行输出移位寄存
器
=
13
RCLR
12
RCLK
10
SRCLR
11
• 移位寄存器和存储寄存器上的独立直接覆盖清零
• 移位寄存器和存储寄存器的独立时钟
• 闩锁性能超过100mA，符合JESD 78 II 类规范
SRCLK
14
SER
D
R
Q
Q
D
R
15
1
Q
Q
QA
2 应用
D
R
D
R
• 输出扩展
• LED 矩阵控制
• 7 段显示控制
QB
QC
2
3
4
5
6
QD
QE
QF
QG
D
R
Q
D
R
7
9
Q
QH
QH’
逻辑图（正逻辑）
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCLS887
SN74LV594A-Q1
ZHCSPK4 –DECEMBER 2022
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Table of Contents
8 Detailed Description......................................................12
8.1 Overview...................................................................12
8.2 Functional Block Diagram.........................................12
8.3 Feature Description...................................................13
8.4 Device Functional Modes..........................................13
9 Application and Implementation..................................14
9.1 Application Information............................................. 14
9.2 Typical Application.................................................... 14
10 Power Supply Recommendations..............................16
11 Layout...........................................................................17
11.1 Layout Guidelines................................................... 17
11.2 Layout Example...................................................... 17
12 Device and Documentation Support..........................18
12.1 接收文档更新通知................................................... 18
12.2 支持资源..................................................................18
12.3 Trademarks.............................................................18
12.4 Electrostatic Discharge Caution..............................18
12.5 术语表..................................................................... 18
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics: VCC = 2.5 V ± 0.2 V...........6
6.7 Switching Characteristics: VCC = 3.3 V ± 0.3 V...........7
6.8 Switching Characteristics: VCC = 5 V ± 0.5 V..............7
6.9 Timing Requirements: VCC = 2.5 V ± 0.2 V.................8
6.10 Timing Requirements: VCC = 3.3 V ± 0.3 V...............8
6.11 Timing Requirements: VCC = 5 V ± 0.5 V..................8
6.12 Noise Characteristics................................................9
6.13 Operating Characteristics......................................... 9
6.14 Typical Characteristics............................................10
7 Parameter Measurement Information.......................... 11
Information.................................................................... 18
4 Revision History
DATE
REVISION
NOTES
December 2022
*
Initial Release
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5 Pin Configuration and Functions
QB
1
VCC
16
QC
2
15 QA
QD
QE
QF
QG
QH
3
4
5
6
7
SER
14
13
RCLR
RCLK
PAD
12
11
10
SRCLK
SRCLR
8
9
GND QH`
图5-1. D, DB, or PW Package 16-Pin SOIC, SSOP, or TSSOP (Top View)
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
QB
NO.
1
O
O
O
O
O
O
O
Output B
Output C
Output D
Output E
Output F
Output G
Output H
QC
2
QD
3
QE
4
QF
5
QG
6
QH
7
GND
8
G
Ground pin
QH'
9
O
I
QH inverted
Serial clear
Serial clock
Storage clock
Storage clear
Serial input
Output A
SRCLR
SRCLK
RCLK
RCLR
SER
10
11
12
13
14
15
I
I
I
I
QA
O
Vcc
16
P
-
Power pin
Thermal Pad
Thermal Pad(1)
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
−0.5
−0.5
−0.5
−0.5
−20
−50
−25
−65
MAX
UNIT
V
VCC
VI
Supply voltage
7
Input voltage(2)
7
7
V
VO
VO
IIK
Voltage range applied to any output in the high-impedance or power-off state(2)
Output voltage(2) (3)
V
VCC + 0.5
V
Input clamp current
VI < 0
mA
mA
mA
°C
IOK
IO
Output clamp current
Continuous output current
Storage temperature
VO< 0
VO = 0 to VCC
25
150
Tstg
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value is limited to 5.5 V maximum.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100-002 HBM ESD
Classification Level 2 (1)
±2000
V(ESD)
Electrostatic discharge
V
±1000
Charged device model (CDM), per AEC Q100-011 CDM ESD
Classification Level C6
(1) AEC Q100-002 indicate that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX UNIT
VCC
Supply voltage
2
1.5
5.5
V
VCC = 2 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 2 V
VCC × 0.7
VCC × 0.7
VCC × 0.7
VIH
High-level input voltage
V
0.5
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC × 0.3
VIL
Low-level input voltage
V
VCC × 0.3
VCC × 0.3
5.5
VI
Input voltage
0
0
V
V
VO
Output voltage
VCC
–50
–2
6
VCC = 2 V
µA
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 2 V
IOH
High-level input current
Low-level output current
mA
µA
–12
50
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
2
IOL
6
mA
12
200
Input transition rise or fall rate
Operating free-air temperature
100 ns/V
20
Δt/Δv
125
TA
°C
–40
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report
Implications of Slow or Floating CMOS Inputs, SCBA004.
6.4 Thermal Information
SN74LV594A-Q1
THERMAL METRIC(1)
BQB (WQFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
86.0
RθJC(top)
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
82.6
54.9
9.5
RθJB
ψJT
ψJB
ψJC
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-bottom characterization parameter
54.9
32.5
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
CC –0.1
2
TYP
MAX
UNIT
2 V to 5.5 V
IOH = –50 µA
V
2.3 V
3 V
IOH = –2 µA
VOH
V
2.48
IOH = –6 µA
4.5 V
2 V to 5.5 V
2.3 V
3 V
3.8
IOH = –12 µA
0.1
0.4
0.44
0.55
±1
IOH = –50 µA
IOH = –2 µA
VOL
V
IOH = –6 µA
4.5 V
0 to 5.5 V
5.5 V
0
IOH = –12 µA
II
VI = 5.5 V or GND
VI = VCC of GND, IO = 0
VI or VO = 0 to 5.5 V
µA
µA
µA
ICC
Ioff
20
5
Ci
VI = VCC or GND
3.3 V
3.5
pF
6.6 Switching Characteristics: VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range (unless otherwise noted). See 图6-1.
TA = 25°C
–40°C TO 125°C
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
LOAD CAPACITANCE
UNIT
MIN
65
TYP
80
MAX
MIN
35
30
1
MAX
CL = 15 pF
CL = 50 pF
fmax
MHz
60
70
tPLH
tPHL
tPLH
tPHL
6.4
10.6
10.4
12.1
11.6
12.7
11.9
14.1
15.5
15.7
16.1
17.4
16.5
12.5
12.5
15
QA –QH
SRCLK
RCLK
6.3
1
7.4
1
QH’
CL = 15 pF
ns
7.2
1
15
7.9
1
15.5
15.5
17
QA –QH
tPHL
QH’
7.4
1
tPLH
tPHL
tPLH
tPHL
9.5
1
QA –QH
SRCLR
RCLR
10.8
10.6
11.3
12.1
11.6
1
19.5
18.5
20.5
21
1
QH’
CL = 50 pF
ns
1
1
QA –QH
tPHL
QH’
1
20.6
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6.7 Switching Characteristics: VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted). See 图6-1.
TA = 25°C
–40°C TO 125°C
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
LOAD CAPACITANCE
UNIT
MIN
80
TYP
120
105
4.6
4.9
5.4
5.5
6
MAX
MIN
60
40
1
MAX
CL = 15 pF
CL = 50 pF
fmax
MHz
55
tPLH
tPHL
tPLH
tPHL
8
8.2
9.1
9.2
9.8
9.2
10.5
10.5
11.5
11.6
12.1
12
QA –QH
SRCLK
RCLK
1
1
QH’
CL = 15 pF
ns
1
1
QA –QH
tPHL
QH’
5.6
1
tPLH
tPHL
tPLH
tPHL
1
12.5
15
QA –QH
SRCLR
RCLR
1
1
14
QH’
CL = 50 pF
ns
1
15.5
16.1
16
1
QA –QH
tPHL
QH’
1
6.8 Switching Characteristics: VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted). See 图6-1.
TA = 25°C
–40°C TO 125°C
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
LOAD CAPACITANCE
UNIT
MIN
135
120
TYP
170
140
3.3
3.7
3.7
4.1
4.5
4.1
4.9
5.8
5.5
6
MAX
CL = 15 pF
CL = 50 pF
105
85
1
fmax
MHz
tPLH
tPHL
tPLH
tPHL
6.2
6.5
6.8
7.2
7.6
7.1
7.8
8.9
8.6
9.2
10
8
QA –QH
SRCLK
RCLK
1
8.5
8.5
9
1
QH’
CL = 15 pF
ns
1
1
9.5
9
QA –QH
tPHL
QH’
1
tPLH
tPHL
tPLH
tPHL
1
9.6
11
QA –QH
SRCLR
RCLR
1
1
10.5
11.5
12
QH’
CL = 50 pF
ns
1
6.6
6
1
QA –QH
tPHL
QH’
9.2
1
11.5
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6.9 Timing Requirements: VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range. See 图6-1.
TA = 25°C
–40°C TO 125°C
UNIT
MAX
MIN
7
MAX
MIN
8.5
7.5
6
RCLK or SRCLK high or low
tw
Pulse duration
ns
RCKR or SCRCLR low
6
5.5
8
SER before SRCLK↑
10
SRCLK↑before RCLK↑
SCRCLR low before RCLK↑(1)
SRCLR high (inactive) before SRCLK↑
RCLK high (inactive) before RCLK↑
SER after SRCLK↑
8.5
6
10.5
7.5
8.5
2
tsu
Setup time
Hold time
ns
ns
6.7
1.5
th
(1) This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case
the shift register is one clock pulse ahead of the storage register.
6.10 Timing Requirements: VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range. See 图6-1.
TA = 25°C
–40°C TO 125°C
UNIT
MIN
5.5
5
MAX
MIN
6.5
6
MAX
RCLK or SRCLK high or low
RCKR or SCRCLR low
tw
Pulse duration
ns
3.5
8
4
SER before SRCLK↑
9.5
10
5.5
6
SRCLK↑before RCLK↑
SCRCLR low before RCLK↑(1)
SRCLR high (inactive) before SRCLK↑
RCLK high (inactive) before RCLK↑
SER after SRCLK↑
8
tsu
Setup time
Hold time
ns
ns
4.2
4.6
1.5
2
th
(1) This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case
the shift register is one clock pulse ahead of the storage register.
6.11 Timing Requirements: VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range. See 图6-1.
TA = 25°C
–40°C TO 125°C
UNIT
MIN
5
MAX
MIN
6
MAX
RCLK or SRCLK high or low
RCKR or SCRCLR low
tw
Pulse duration
ns
5.2
3
6.2
3.5
6
SER before SRCLK↑
5
SRCLK↑before RCLK↑
SCRCLR low before RCLK↑(1)
SRCLR high (inactive) before SRCLK↑
RCLK high (inactive) before RCLK↑
SER after SRCLK↑
5
5.5
4
tsu
Setup time
Hold time
ns
ns
2.9
3.2
2
4.5
2.5
th
(1) This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case
the shift register is one clock pulse ahead of the storage register.
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6.12 Noise Characteristics
over operating free-air temperature range (unless otherwise noted), VCC = 3.3 V, CL = 50 pF, TA = 25°C(1)
PARAMETER
Quiet output, maximum dynamic VOL
Quiet output, minimum dynamic VOL
Quiet output, minimum dynamic VOH
High-level dynamic input voltage
Low-level dynamic input voltage
MIN
TYP
MAX
0.8
UNIT
VOL(P)
VOL(V)
VOH(V)
VIH(V)
VIL(V)
0.5
V
V
V
V
V
–0.1
2.8
–0.8
2.31
0.99
(1) Characteristics are for surface-mount packages only.
6.13 Operating Characteristics
TA = 25°C
PARAMETER
TEST CONDITIONS
f = 10 MHz
VCC
3.3 V
5 V
TYP UNIT
93
pF
112
Cpd
Power dissipation capacitance
图6-1. Timing Diagram
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6.14 Typical Characteristics
6
7
6
5
4
3
2
1
0
5
4
3
2
1
0
-100
-50
0
Temperature
50
100
150
0
1
2
3
Vcc
4
5
6
D001
D002
图6-2. TPD vs. Temperature at 3.3 V
图6-3. TPD vs. Vcc at 25°C
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7 Parameter Measurement Information
图7-1. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SN74LV594A-Q1 devices are 8-bit shift registers designed for 2-V to 5.5-V VCC operation.
These devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register.
Separate clocks (RCLK, SRCLK) and direct overriding clear (RCLR, SRCLR) inputs are provided on the shift
and storage registers. A serial output (QH′) is provided for cascading purposes. The shift-register (SRCLK) and
storage-register (RCLK) clocks are positive-edge triggered. If the clocks are tied together, then the shift register
always is one clock pulse ahead of the storage register.
8.2 Functional Block Diagram
13
RCLR
12
RCLK
10
SRCLR
11
SRCLK
14
Q
Q
SER
D
R
D
R
15
1
Q
Q
QA
D
R
D
R
QB
QC
2
3
4
5
6
QD
QE
QF
QG
Q
D
R
D
R
7
9
Q
QH
QH’
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8.3 Feature Description
The device’s wide operating range allows it to be used in a variety of systems that use different logic levels.
The low propagation delay allows fast switching and higher speeds of operation. In addition, the low ground
bounce stabilizes the performance of non-switching outputs while another output is switching.
8.4 Device Functional Modes
表8-1. Function Table
INPUTS
FUNCTION
SER
SRCLK
SRCLR
RCLK
RCLR
X
X
L
X
X
Shift register is cleared.
First stage of shift register goes low. Other stages
store the data of previous stage, repectively.
L
H
H
X
X
X
X
↑
↑
First stage of shift register goes high. Other stages
store the data of previous stage, respectively.
H
L
X
X
X
H
X
X
X
X
X
X
L
Shift register state is not changed.
Storage register is cleared.
↓
X
X
H
H
Shift register data is stored in the storage register.
Storage register state is not changed.
↑
↓
X
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The SN74LV594A-Q1 is a low drive CMOS device that can be used for a multitude of bus interface type
applications where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and
undershoot on the outputs.
9.2 Typical Application
VCC
VCC
Seven Segment
R1
C1
QA
QB
QC
QD
QE
QF
QG
QH
g
a
SRCLR
RCLR
f
f
b
c
a
SER
b
DP
c
g
SRCLK
RCLK
MCU
e
d
e
d
DP
GND
QH‘
VCC
VCC
SRCLR
Seven Segment
R2
C2
QA
QB
QC
QD
QE
QF
QG
QH
g
a
f
RCLR
f
b
c
a
SER
b
DP
c
g
SRCLK
RCLK
e
d
e
d
DP
GND
QH‘
图9-1. Typical Application Schematic
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9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads,
so consider routing and load conditions to prevent ringing.
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9.2.2 Detailed Design Procedure
• Recommended input conditions:
– Rise time and fall time specs. See (Δt/ΔV) in 节6.3.
– Specified high and low levels. See (VIH and VIL) in 节6.3.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC
• Recommended output conditions:
.
– Load currents should not exceed 25 mA per output and 50 mA total for the part.
– Outputs should not be pulled above VCC
.
9.2.3 Application Curves
SER
QA
SER
QA
QB
QC
QD
QE
QF
QG
QB
QC
QD
QE
QF
QG
QH
QH
QH‘
QH‘
SRCLK rising edge shifts data
in the serial registers only
RCLK rising edge shifts data
to the output registers
图9-2. Simplified functional diagram showing clock operation
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. For devices with a single supply, TI recommends a 0.1-μF capacitor and if there are multiple VCC
terminals then TI recommends a 0.01-μF or 0.022-μF capacitor for each power terminal. Multiple bypass
capacitors can be paralleled to reject different frequencies of noise. Frequencies of 0.1 μF and 1 μF are
commonly used in parallel. The bypass capacitor should be installed as close as possible to the power terminal
for best results.
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11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only three of the four buffer gates are used. Such input pins should
not be left unconnected because the undefined voltages at the outside connections result in undefined
operational states. Specified below are the rules that must be observed under all circumstances. All unused
inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic
level that should be applied to any particular unused input depends on the function of the device. Generally they
will be tied to GND or VCC whichever make more sense or is more convenient. Floating outputs is generally
acceptable, unless the part is a transceiver. If the transceiver has an output enable pin, then it will disable the
outputs section of the part when asserted. This will not disable the input section of the I.O’s so they also cannot
float when disabled.
11.2 Layout Example
图11-1. Layout Example
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12 Device and Documentation Support
12.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
31-Jan-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN74LV594AQWBQBRQ1
ACTIVE
WQFN
BQB
16
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV594Q
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LV594A-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
31-Jan-2023
Catalog : SN74LV594A
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
GENERIC PACKAGE VIEW
BQB 16
2.5 x 3.5, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226161/A
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PACKAGE OUTLINE
WQFN - 0.8 mm max height
INDSTNAME
BQB0016B
A
2.6
2.4
B
PIN 1 INDEX AREA
3.6
3.4
0.1 MIN
(0.13)
SECTION A-A
TYPICAL
C
0.8 MAX
SEATING PLANE
0.05
0.00
0.08 C
1.1
0.9
2X 0.5
(0.2) TYP
9
8
10X 0.5
7
10
(0.16)
SYMM
SYMM
2X
2.5
17
2.1
1.9
0.3
16X
0.2
0.1
0.05
C A B
C
15
2
PIN 1 ID
(OPTIONAL)
1
16
0.5
0.3
16X
SYMM
4226135/A 08/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
WQFN - 0.8 mm max height
INDSTNAME
BQB0016B
(2.3)
(1)
1
16
16X (0.6)
16X (0.25)
2
15
10X (0.5)
SYMM
17
(2)
(3.3)
2X (0.75)
10
7
(R0.05) TYP
(Ø 0.2) VIA
TYP
8
9
2X (0.5)
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
4226135/A 08/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271)
.
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
WQFN - 0.8 mm max height
INDSTNAME
BQB0016B
(2.3)
(0.95)
1
16
16X (0.6)
16X (0.25)
2
15
17
10X (0.5)
SYMM
(1.79)
(3.3)
2X (0.75)
10
7
(R0.05) TYP
METAL TYP
8
9
2X (0.5)
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
85% PRINTED COVERAGE BY AREA
SCALE: 20X
4226135/A 08/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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Copyright © 2023，德州仪器 (TI) 公司
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