SN74LV165APWRG3 [TI]
PARALLEL-LOAD 8-BIT SHIFT REGISTERS; 并联负载8位移位寄存器
| 型号： | SN74LV165APWRG3 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | PARALLEL-LOAD 8-BIT SHIFT REGISTERS |
| 文件： | 总20页 (文件大小：598K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LV165A, SN74LV165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SCLS402L − APRIL 1998 − REVISED MAY 2010
D
D
D
D
2-V to 5.5-V V Operation
D
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
CC
Max t of 10.5 ns at 5 V
pd
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
Support Mixed-Mode Voltage Operation on
All Ports
I
off
Supports Partial-Power-Down Mode
− 1000-V Charged-Device Model (C101)
Operation
SN54LV165A . . . J OR W PACKAGE
SN74LV165A . . . D, DB, DGV, NS,
OR PW PACKAGE
SN74LV165A . . . RGY PACKAGE
(TOP VIEW)
SN54LV165A . . . FK PACKAGE
(TOP VIEW)
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SH/LD
CLK
E
VCC
CLK INH
D
C
B
A
SER
QH
1
16
CLK
E
F
G
H
QH
15
14
13
12
11
10
2
3
4
5
6
7
CLK INH
D
C
B
A
SER
3
2
1
20 19
18
4
5
6
7
8
D
C
NC
B
A
E
F
NC
G
F
G
H
17
16
15
14
QH
GND
H
9 10 11 12 13
8
9
NC − No internal connection
description/ordering information
The ’LV165A devices are parallel-load, 8-bit shift registers designed for 2-V to 5.5-V V operation.
CC
When the devices are clocked, data is shifted toward the serial output Q . Parallel-in access to each stage is
H
provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/LD) input.
The ’LV165A devices feature a clock-inhibit function and a complemented serial output, Q .
H
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
QFN − RGY
SOIC − D
Reel of 1000
Tube of 40
SN74LV165ARGYR
SN74LV165AD
LV165A
LV165A
Reel of 2500
Reel of 2000
Reel of 2000
Tube of 90
SN74LV165ADR
SN74LV165ANSR
SN74LV165ADBR
SN74LV165APW
SN74LV165APWR
SN74LV165APWT
SN74LV165ADGVR
SNJ54LV165AJ
SOP − NS
74LV165A
LV165A
SSOP − DB
−40°C to 85°C
Reel of 2000
Reel of 250
Reel of 2000
Tube of 25
TSSOP − PW
LV165A
TVSOP − DGV
CDIP − J
LV165A
SNJ54LV165AJ
SNJ54LV165AW
SNJ54LV165AFK
−55°C to 125°C
CFP − W
Tube of 150
Tube of 55
SNJ54LV165AW
SNJ54LV165AFK
LCCC − FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2010, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV165A, SN74LV165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SCLS402L − APRIL 1998 − REVISED MAY 2010
description/ordering information (continued)
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and clock
inhibit (CLK INH) is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a
low-to-high transition of CLK INH accomplishes clocking, CLK INH should be changed to the high level only
while CLK is high. Parallel loading is inhibited when SH/LD is held high. The parallel inputs to the register are
enabled while SH/LD is held low, independently of the levels of CLK, CLK INH, or SER.
These devices are fully specified for partial-power-down applications using I . The I circuitry disables the
off
off
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
INPUTS
OPERATION
SH/LD CLK CLK INH
L
X
H
X
L
X
X
H
↑
L
Parallel load
H
H
H
H
Q
Q
0
0
Shift
Shift
↑
logic diagram (positive logic)
A
B
C
D
E
F
G
H
11
12
13
14
3
4
5
6
1
SH/LD
15
CLK INH
2
CLK
S
9
7
S
S
S
S
S
S
S
Q
Q
H
H
C1
C1
1D
C1
C1
C1
C1
C1
C1
10
1D
1D
R
1D
R
1D
R
1D
R
1D
R
1D
R
SER
R
R
Pin numbers shown are for the D, DB, DGV, J, NS, PW, RGY, and W packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV165A, SN74LV165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SCLS402L − APRIL 1998 − REVISED MAY 2010
typical shift, load, and inhibit sequences
CLK
CLK INH
SER
L
SH/LD
A
H
L
B
C
H
Data
Inputs
L
D
E
F
H
L
H
H
G
H
L
L
L
Q
H
L
H
L
H
L
H
L
H
L
H
Q
H
H
H
H
Inhibit
Serial Shift
Load
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV165A, SN74LV165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SCLS402L − APRIL 1998 − REVISED MAY 2010
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
IK
I
Output clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
OK
O
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
O
O
CC
Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
CC
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
(see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
(see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV165A, SN74LV165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SCLS402L − APRIL 1998 − REVISED MAY 2010
recommended operating conditions (see Note 5)
SN54LV165A
SN74LV165A
UNIT
MIN
2
MAX
MIN
2
MAX
V
V
Supply voltage
5.5
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
1.5
× 0.7
1.5
× 0.7
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
V
V
V
V
V
V
CC
CC
High-level input voltage
V
V
IH
× 0.7
× 0.7
× 0.7
× 0.7
CC
CC
CC
CC
0.5
0.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
V
CC
V
CC
V
CC
× 0.3
× 0.3
× 0.3
5.5
V
CC
V
CC
V
CC
× 0.3
× 0.3
× 0.3
5.5
V
IL
Low-level input voltage
V
V
Input voltage
0
0
0
0
V
V
I
Output voltage
V
CC
V
CC
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
−50
−50
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
−2
−6
−2
−6
−12
50
2
I
High-level output current
Low-level output current
OH
mA
−12
50
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
2
I
OL
6
6
mA
12
12
200
100
20
85
200
100
20
∆t/∆v Input transition rise or fall rate
ns/V
T
Operating free-air temperature
−55
125
−40
°C
A
NOTE 5: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV165A
SN74LV165A
PARAMETER
TEST CONDITIONS
UNIT
V
CC
MIN
−0.1
2
TYP
MAX
MIN
−0.1
2
TYP
MAX
I
I
I
I
I
I
I
I
= −50 µA
= −2 mA
= −6 mA
= −12 mA
= 50 µA
= 2 mA
2 V to 5.5 V
2.3 V
V
CC
V
CC
OH
OH
OH
OH
OL
OL
OL
OL
V
OH
V
OL
V
3 V
2.48
3.8
2.48
3.8
4.5 V
2 V to 5.5 V
2.3 V
0.1
0.4
0.44
0.55
1
0.1
0.4
0.44
0.55
1
V
= 6 mA
3 V
= 12 mA
4.5 V
I
I
V = 5.5 V or GND
0 to 5.5 V
5.5 V
µA
µA
µA
pF
I
I
V = V or GND,
I = 0
O
20
20
CC
I
CC
I
off
V or V = 0 to 5.5 V
0
5
5
I
O
C
V = V or GND
3.3 V
1.7
1.7
i
I
CC
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV165A, SN74LV165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SCLS402L − APRIL 1998 − REVISED MAY 2010
timing requirements over recommended operating free-air temperature range, VCC = 2.5 V 0.2 V
(unless otherwise noted) (see Figure 1)
T = 25°C
SN54LV165A SN74LV165A
A
UNIT
MIN
8.5
11
7
MAX
MIN
9
MAX
MIN
9
MAX
CLK high or low
t
t
Pulse duration
Setup time
ns
w
SH/LD low
13
8.5
9.5
7
13
8.5
9.5
7
SH/LD high before CLK↑
SER before CLK↑
8.5
7
ns
ns
su
CLK INH before CLK↑
Data before SH/LD↑
SER data after CLK↑
Parallel data after SH/LD↑
SH/LD high after CLK↑
11.5
−1
0
12
0
12
0
t
h
Hold time
0.5
0
0.5
0
0
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V 0.3 V
(unless otherwise noted) (see Figure 1)
T = 25°C
SN54LV165A SN74LV165A
A
UNIT
MIN
6
MAX
MIN
7
MAX
MIN
7
MAX
CLK high or low
t
t
Pulse duration
Setup time
ns
w
SH/LD low
7.5
5
9
9
SH/LD high before CLK↑
SER before CLK↑
6
6
5
6
6
ns
ns
su
CLK INH before CLK↑
Data before SH/LD↑
SER data after CLK↑
Parallel data after SH/LD↑
SH/LD high after CLK↑
5
5
5
7.5
0
8.5
0
8.5
0
t
h
Hold time
0.5
0
0.5
0
0.5
0
timing requirements over recommended operating free-air temperature range, VCC = 5 V 0.5 V
(unless otherwise noted) (see Figure 1)
T = 25°C
SN54LV165A SN74LV165A
A
UNIT
MIN
4
MAX
MIN
4
MAX
MIN
4
MAX
CLK high or low
t
t
Pulse duration
Setup time
ns
w
SH/LD low
5
6
6
SH/LD high before CLK↑
SER before CLK↑
4
4
4
4
4
4
ns
ns
su
CLK INH before CLK↑
Data before SH/LD↑
SER data after CLK↑
Parallel data after SH/LD↑
SH/LD high after CLK↑
3.5
5
3.5
5
3.5
5
0.5
1
0.5
1
0.5
1
t
h
Hold time
0.5
0.5
0.5
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV165A, SN74LV165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SCLS402L − APRIL 1998 − REVISED MAY 2010
switching characteristics over recommended operating free-air temperature range,
VCC = 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)
T = 25°C
SN54LV165A SN74LV165A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A
PARAMETER
UNIT
MIN
50*
40
TYP
80*
65
MAX
MIN
45*
35
MAX
MIN
45
35
1
MAX
C = 15 pF
L
f
MHz
max
pd
C = 50 pF
L
CLK
SH/LD
H
12.2* 19.8*
13.1* 21.5*
12.9* 21.7*
1*
22*
22
23.5
24
t
1* 23.5*
1
ns
ns
Q
Q
or Q
or Q
C = 15 pF
L
H
H
H
1*
24*
1
CLK
SH/LD
H
15.3
16.1
15.9
23.3
25.1
25.3
1
1
1
26
28
28
1
1
1
26
28
28
t
pd
C = 50 pF
L
H
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
CC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
V
T = 25°C
SN54LV165A SN74LV165A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A
PARAMETER
UNIT
MIN
65*
60
TYP
115*
90
MAX
MIN
55*
50
MAX
MIN
55
50
1
MAX
C = 15 pF
L
f
MHz
max
pd
C = 50 pF
L
CLK
SH/LD
H
8.6* 15.4*
9.1* 15.8*
8.9* 14.1*
1*
18*
18
18.5
16.5
16.9
22
1* 18.5*
1* 16.5*
1
Q
Q
or Q
or Q
C = 15 pF
L
t
ns
ns
H
H
H
1
CLK
SH/LD
H
10.9
11.3
11.1
14.9
19.3
17.6
1
1
1
16.9
22
1
t
pd
1
C = 50 pF
L
H
20
1
20
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
T = 25°C
SN54LV165A SN74LV165A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A
PARAMETER
UNIT
MIN
110*
95
TYP
165*
125
6*
MAX
MIN
90*
85
MAX
MIN
90
85
1
MAX
C = 15 pF
L
f
MHz
max
pd
C = 50 pF
L
CLK
SH/LD
H
9.9*
9.9*
9*
1* 11.5*
1* 11.5*
1* 10.5*
11.5
11.5
10.5
13.5
13.5
12.5
6*
1
Q
Q
or Q
or Q
C = 15 pF
L
t
ns
ns
H
H
H
6*
1
CLK
SH/LD
H
7.7
7.7
7.6
11.9
11.9
11
1
1
1
13.5
13.5
12.5
1
t
pd
1
C = 50 pF
L
H
1
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
operating characteristics, TA = 25°C
PARAMETER
TEST CONDITIONS
f = 10 MHz
V
TYP
36.1
37.5
UNIT
CC
3.3 V
C
Power dissipation capacitance
C = 50 pF,
pF
pd
L
5 V
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV165A, SN74LV165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SCLS402L − APRIL 1998 − REVISED MAY 2010
PARAMETER MEASUREMENT INFORMATION
V
CC
S1
Open
R = 1 kΩ
L
TEST
/t
S1
From Output
Under Test
Test
Point
From Output
Under Test
GND
t
t
Open
PLH PHL
t
C
C
L
/t
V
CC
L
PLZ PZL
(see Note A)
(see Note A)
/t
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
Timing Input
CC
0 V
t
w
t
h
t
V
su
CC
V
CC
50% V
50% V
Input
Input
CC
CC
50% V
50% V
CC
Data Input
0 V
CC
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
50% V
50% V
50% V
50% V
t
CC
CC
CC
CC
0 V
0 V
t
t
t
t
PZL
PLH
PHL
PLZ
Output
Waveform 1
V
≈V
OH
CC
In-Phase
Output
50% V
50% V
CC
50% V
CC
CC
V
+ 0.3 V
OL
S1 at V
CC
V
OL
V
OL
(see Note B)
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
V
OH
OH
Out-of-Phase
Output
V
OH
− 0.3 V
50% V
50% V
50% V
CC
CC
CC
OL
V
≈0 V
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time, with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
.
PLZ
PZL
PHL
PHZ
dis
are the same as t
PZH
en
are the same as t .
PLH pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
27-May-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
SN74LV165AD
SN74LV165ADBR
SN74LV165ADBRE4
SN74LV165ADBRG4
SN74LV165ADE4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SSOP
SSOP
SSOP
SOIC
D
DB
DB
DB
D
16
16
16
16
16
16
16
16
16
16
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
2000
2000
2000
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
Purchase Samples
Purchase Samples
Purchase Samples
Purchase Samples
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SN74LV165ADG4
SN74LV165ADGVR
SN74LV165ADGVRE4
SN74LV165ADGVRG4
SN74LV165ADR
SOIC
D
40
Green (RoHS
& no Sb/Br)
TVSOP
TVSOP
TVSOP
SOIC
DGV
DGV
DGV
D
2000
2000
2000
2500
2500
Green (RoHS
& no Sb/Br)
Contact TI Distributor
or Sales Office
Green (RoHS
& no Sb/Br)
Contact TI Distributor
or Sales Office
Green (RoHS
& no Sb/Br)
Contact TI Distributor
or Sales Office
Green (RoHS
& no Sb/Br)
Contact TI Distributor
or Sales Office
SN74LV165ADRE4
SOIC
D
Green (RoHS
& no Sb/Br)
Contact TI Distributor
or Sales Office
SN74LV165ADRG3
SN74LV165ADRG4
PREVIEW
ACTIVE
SOIC
SOIC
D
D
16
16
2500
2500
TBD
Call TI
Call TI
Samples Not Available
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Contact TI Distributor
or Sales Office
SN74LV165ANSR
SN74LV165ANSRE4
SN74LV165ANSRG4
SN74LV165APW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SO
SO
NS
NS
NS
PW
16
16
16
16
2000
2000
2000
90
Green (RoHS
& no Sb/Br)
Purchase Samples
Purchase Samples
Purchase Samples
Purchase Samples
Green (RoHS
& no Sb/Br)
SO
Green (RoHS
& no Sb/Br)
TSSOP
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
27-May-2010
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
SN74LV165APWE4
SN74LV165APWG4
SN74LV165APWR
SN74LV165APWRE4
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
16
16
16
16
90
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
2000
2000
Green (RoHS
& no Sb/Br)
Contact TI Distributor
or Sales Office
Green (RoHS
& no Sb/Br)
Contact TI Distributor
or Sales Office
SN74LV165APWRG3
SN74LV165APWRG4
PREVIEW
ACTIVE
TSSOP
TSSOP
PW
PW
16
16
2000
2000
TBD
Call TI
Call TI
Samples Not Available
Request Free Samples
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
SN74LV165APWT
SN74LV165APWTE4
SN74LV165APWTG4
SN74LV165ARGYR
SN74LV165ARGYRG4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
VQFN
PW
PW
16
16
16
16
16
250
250
Green (RoHS
& no Sb/Br)
Purchase Samples
Purchase Samples
Green (RoHS
& no Sb/Br)
PW
250
Green (RoHS
& no Sb/Br)
Purchase Samples
RGY
RGY
3000
3000
Green (RoHS
& no Sb/Br)
Request Free Samples
Request Free Samples
VQFN
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
27-May-2010
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LV165A :
Enhanced Product: SN74LV165A-EP
•
NOTE: Qualified Version Definitions:
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
15-May-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LV165ADBR
SN74LV165ADGVR
SN74LV165ADR
SSOP
TVSOP
SOIC
DB
DGV
D
16
16
16
16
16
16
2000
2000
2500
2000
2000
3000
330.0
330.0
330.0
330.0
330.0
180.0
16.4
12.4
16.4
16.4
12.4
12.4
8.2
6.8
6.5
8.2
7.0
3.8
6.6
4.0
2.5
1.6
2.1
2.5
1.6
1.5
12.0
8.0
16.0
12.0
16.0
16.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
10.3
10.5
5.6
8.0
SN74LV165ANSR
SN74LV165APWR
SN74LV165ARGYR
SO
NS
12.0
8.0
TSSOP
VQFN
PW
RGY
4.3
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-May-2010
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LV165ADBR
SN74LV165ADGVR
SN74LV165ADR
SSOP
TVSOP
SOIC
DB
DGV
D
16
16
16
16
16
16
2000
2000
2500
2000
2000
3000
346.0
346.0
333.2
346.0
346.0
190.5
346.0
346.0
345.9
346.0
346.0
212.7
33.0
29.0
28.6
33.0
29.0
31.8
SN74LV165ANSR
SN74LV165APWR
SN74LV165ARGYR
SO
NS
TSSOP
VQFN
PW
RGY
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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相关型号：
SN74LV165DBR
LV/LV-A/LVX/H SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, PDSO16, PLASTIC, SSOP-16
TI
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