SN74LV165ABQBR [TI]
并联负载 8 位移位寄存器 | BQB | 16 | -40 to 125;型号: | SN74LV165ABQBR |
厂家: | TEXAS INSTRUMENTS |
描述: | 并联负载 8 位移位寄存器 | BQB | 16 | -40 to 125 移位寄存器 |
文件: | 总17页 (文件大小:470K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢂ ꢈꢉ ꢀꢁꢊ ꢃꢄꢅ ꢆꢇ ꢂꢈ
ꢋꢈꢌꢈ ꢄꢄ ꢍꢄ ꢎꢄ ꢏ ꢈꢐ ꢑ ꢎꢒꢓ ꢔ ꢀꢕ ꢓꢖ ꢔ ꢌꢍ ꢗ ꢓꢀ ꢔꢍ ꢌ ꢀ
SCLS402K − APRIL 1998 − REVISED APRIL 2005
D
D
D
D
2-V to 5.5-V V
Operation
D
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
CC
Max t of 10.5 ns at 5 V
pd
Support Mixed-Mode Voltage Operation on
All Ports
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
I
Supports Partial-Power-Down Mode
off
− 1000-V Charged-Device Model (C101)
Operation
SN54LV165A . . . J OR W PACKAGE
SN74LV165A . . . D, DB, DGV, NS,
OR PW PACKAGE
SN74LV165A . . . RGY PACKAGE
(TOP VIEW)
SN54LV165A . . . FK PACKAGE
(TOP VIEW)
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SH/LD
CLK
E
V
CC
CLK INH
1
16
CLK
E
F
G
H
Q
H
15
14
13
12
11
10
2
3
4
5
6
7
CLK INH
D
C
B
A
SER
3
2
1
20 19
18
D
C
B
A
4
5
6
7
8
D
C
NC
B
A
E
F
NC
G
F
G
H
17
16
15
14
Q
SER
H
H
9 10 11 12 13
GND
Q
H
8
9
NC − No internal connection
description/ordering information
The ’LV165A devices are parallel-load, 8-bit shift registers designed for 2-V to 5.5-V V
operation.
CC
When the devices are clocked, data is shifted toward the serial output Q . Parallel-in access to each stage is
H
provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/LD) input.
The ’LV165A devices feature a clock-inhibit function and a complemented serial output, Q .
H
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
QFN − RGY
SOIC − D
Reel of 1000
Tube of 40
SN74LV165ARGYR
SN74LV165AD
LV165A
LV165A
Reel of 2500
Reel of 2000
Reel of 2000
Tube of 90
SN74LV165ADR
SN74LV165ANSR
SN74LV165ADBR
SN74LV165APW
SN74LV165APWR
SN74LV165APWT
SN74LV165ADGVR
SNJ54LV165AJ
SOP − NS
74LV165A
LV165A
SSOP − DB
−40°C to 85°C
Reel of 2000
Reel of 250
Reel of 2000
Tube of 25
TSSOP − PW
LV165A
TVSOP − DGV
CDIP − J
LV165A
SNJ54LV165AJ
SNJ54LV165AW
SNJ54LV165AFK
−55°C to 125°C
CFP − W
Tube of 150
Tube of 55
SNJ54LV165AW
SNJ54LV165AFK
LCCC − FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2005, Texas Instruments Incorporated
ꢘ ꢁ ꢄꢍꢀꢀ ꢏ ꢔꢕ ꢍꢌꢙ ꢓꢀ ꢍ ꢁ ꢏꢔꢍꢐ ꢚꢛ ꢜꢝ ꢞꢟꢠ ꢡꢢꢣ ꢤꢚ ꢠꢟ ꢤꢚꢥ ꢜꢤꢝ ꢋꢌ ꢏ ꢐ ꢘ ꢦꢔ ꢓꢏ ꢁ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢂꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆ ꢇꢂ ꢈ
ꢋꢈ ꢌ ꢈꢄ ꢄ ꢍꢄ ꢎꢄ ꢏꢈ ꢐ ꢑ ꢎꢒꢓ ꢔ ꢀ ꢕꢓ ꢖꢔ ꢌꢍ ꢗ ꢓꢀ ꢔꢍ ꢌꢀ
SCLS402K − APRIL 1998 − REVISED APRIL 2005
description/ordering information (continued)
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and clock
inhibit (CLK INH) is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a
low-to-high transition of CLK INH accomplishes clocking, CLK INH should be changed to the high level only
while CLK is high. Parallel loading is inhibited when SH/LD is held high. The parallel inputs to the register are
enabled while SH/LD is held low, independently of the levels of CLK, CLK INH, or SER.
These devices are fully specified for partial-power-down applications using I . The I circuitry disables the
off
off
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
INPUTS
OPERATION
SH/LD CLK CLK INH
L
X
H
X
L
X
X
H
↑
L
Parallel load
H
H
H
H
Q
Q
0
0
Shift
Shift
↑
logic diagram (positive logic)
A
B
C
D
E
F
G
H
11
12
13
14
3
4
5
6
1
SH/LD
15
CLK INH
2
CLK
S
9
7
S
S
S
S
S
S
S
Q
Q
H
H
C1
C1
1D
C1
C1
C1
C1
C1
C1
10
1D
1D
R
1D
R
1D
R
1D
R
1D
R
1D
R
SER
R
R
Pin numbers shown are for the D, DB, DGV, J, NS, PW, RGY, and W packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢂ ꢈꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢂꢈ
ꢖ
ꢋꢈ
ꢌ
ꢈ
ꢄ
ꢄ
ꢍ
ꢄ
ꢎ
ꢄ
ꢏ
ꢈ
ꢐ
ꢑ
ꢎ
ꢒ
ꢓ
ꢔ
ꢀ
ꢕ
ꢓ
ꢔ
ꢌ
ꢍ
ꢗ
ꢓꢀ
ꢔ
ꢍ
ꢌ
ꢀ
SCLS402K − APRIL 1998 − REVISED APRIL 2005
typical shift, load, and inhibit sequences
CLK
CLK INH
L
SER
SH/LD
A
H
L
B
C
H
Data
Inputs
L
D
E
F
H
L
H
H
G
H
L
L
L
Q
H
H
L
H
L
H
L
H
L
H
L
Q
H
H
H
H
Inhibit
Serial Shift
Load
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢂꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆ ꢇꢂ ꢈ
ꢋꢈ ꢌ ꢈꢄ ꢄ ꢍꢄ ꢎꢄ ꢏꢈ ꢐ ꢑ ꢎꢒꢓ ꢔ ꢀ ꢕꢓ ꢖꢔ ꢌꢍ ꢗ ꢓꢀ ꢔꢍ ꢌꢀ
SCLS402K − APRIL 1998 − REVISED APRIL 2005
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
O
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
O
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
(see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
(see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢂ ꢈꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢂꢈ
ꢋꢈꢌꢈ ꢄꢄ ꢍꢄ ꢎꢄ ꢏ ꢈꢐ ꢑ ꢎꢒꢓ ꢔ ꢀꢕ ꢓꢖ ꢔ ꢌꢍ ꢗ ꢓꢀ ꢔꢍ ꢌ ꢀ
SCLS402K − APRIL 1998 − REVISED APRIL 2005
recommended operating conditions (see Note 5)
SN54LV165A
SN74LV165A
UNIT
MIN
2
MAX
MIN
2
MAX
V
V
Supply voltage
5.5
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
1.5
1.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
V
× 0.7
× 0.7
× 0.7
V
CC
V
CC
V
CC
× 0.7
× 0.7
× 0.7
CC
CC
CC
High-level input voltage
V
IH
V
V
0.5
0.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
V
V
V
× 0.3
× 0.3
× 0.3
5.5
V
V
V
× 0.3
CC
CC
CC
CC
CC
CC
V
IL
Low-level input voltage
V
× 0.3
× 0.3
5.5
V
V
Input voltage
0
0
0
0
V
V
I
Output voltage
V
V
CC
O
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
−50
−2
−50
−2
−6
−12
50
2
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
I
High-level output current
Low-level output current
OH
OL
−6
mA
−12
50
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
2
I
6
6
mA
12
12
200
100
20
85
200
100
20
∆t/∆v Input transition rise or fall rate
ns/V
T
Operating free-air temperature
−55
125
−40
°C
A
NOTE 5: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV165A
SN74LV165A
PARAMETER
TEST CONDITIONS
UNIT
V
CC
MIN
−0.1
2
TYP
MAX
MIN
−0.1
2
TYP
MAX
I
I
I
I
I
I
I
I
= −50 µA
= −2 mA
= −6 mA
= −12 mA
= 50 µA
= 2 mA
2 V to 5.5 V
2.3 V
V
CC
V
CC
OH
OH
OH
OH
OL
OL
OL
OL
V
V
V
OH
3 V
2.48
3.8
2.48
3.8
4.5 V
2 V to 5.5 V
2.3 V
0.1
0.4
0.44
0.55
1
0.1
0.4
0.44
0.55
1
V
OL
= 6 mA
3 V
= 12 mA
4.5 V
I
I
I
V = 5.5 V or GND
0 to 5.5 V
5.5 V
µA
µA
µA
pF
I
I
V = V
CC
or GND,
I = 0
O
20
20
CC
off
I
V or V = 0 to 5.5 V
0
5
5
I
O
C
V = V
or GND
3.3 V
1.7
1.7
i
I
CC
ꢋ
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ꢟ
ꢤ
ꢠ
ꢟ
ꢤ
ꢠ
ꢣ
ꢨ
ꢤ
ꢝ
ꢩ
ꢨ
ꢟ
ꢞ
ꢡ
ꢞꢣ ꢝ ꢜ ꢰꢤ ꢩꢛ ꢥ ꢝ ꢣ ꢟꢧ ꢞꢣ ꢱ ꢣ ꢫꢟ ꢩꢢꢣ ꢤꢚꢬ ꢦ ꢛꢥ ꢨꢥ ꢠꢚ ꢣꢨ ꢜꢝ ꢚꢜ ꢠ ꢞꢥ ꢚꢥ ꢥꢤ ꢞ ꢟꢚ ꢛꢣꢨ
ꢠ
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ꢠ
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ꢠ ꢛꢥ ꢤ ꢰꢣ ꢟꢨ ꢞꢜ ꢝ ꢠ ꢟꢤ ꢚꢜ ꢤꢡꢣ ꢚ ꢛꢣ ꢝ ꢣ ꢩꢨ ꢟꢞ ꢡꢠꢚ ꢝ ꢮ ꢜꢚꢛ ꢟꢡꢚ ꢤꢟꢚ ꢜꢠꢣ ꢬ
ꢚ
ꢝ
ꢨ
ꢣ
ꢝ
ꢣ
ꢨ
ꢱ
ꢣ
ꢝ
ꢚ
ꢛ
ꢣ
ꢨ
ꢜ
ꢰ
ꢛ
ꢚ
ꢚ
ꢟ
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢂꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆ ꢇꢂ ꢈ
ꢋꢈ ꢌ ꢈꢄ ꢄ ꢍꢄ ꢎꢄ ꢏꢈ ꢐ ꢑ ꢎꢒꢓ ꢔ ꢀ ꢕꢓ ꢖꢔ ꢌꢍ ꢗ ꢓꢀ ꢔꢍ ꢌꢀ
SCLS402K − APRIL 1998 − REVISED APRIL 2005
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 2.5 V 0.2 V
CC
T
= 25°C
SN54LV165A SN74LV165A
A
UNIT
MIN
8.5
11
7
MAX
MIN
9
MAX
MIN
9
MAX
CLK high or low
t
t
Pulse duration
Setup time
ns
w
SH/LD low
13
8.5
9.5
7
13
8.5
9.5
7
SH/LD high before CLK↑
SER before CLK↑
8.5
7
ns
ns
su
CLK INH before CLK↑
Data before SH/LD↑
SER data after CLK↑
Parallel data after SH/LD↑
SH/LD high after CLK↑
11.5
−1
0
12
0
12
0
t
h
Hold time
0.5
0
0.5
0
0
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 3.3 V 0.3 V
CC
T
= 25°C
SN54LV165A SN74LV165A
A
UNIT
MIN
6
MAX
MIN
7
MAX
MIN
7
MAX
CLK high or low
t
t
Pulse duration
Setup time
ns
w
SH/LD low
7.5
5
9
9
SH/LD high before CLK↑
SER before CLK↑
6
6
5
6
6
ns
ns
su
CLK INH before CLK↑
Data before SH/LD↑
SER data after CLK↑
Parallel data after SH/LD↑
SH/LD high after CLK↑
5
5
5
7.5
0
8.5
0
8.5
0
t
h
Hold time
0.5
0
0.5
0
0.5
0
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 5 V 0.5 V
CC
T
= 25°C
SN54LV165A SN74LV165A
A
UNIT
MIN
4
MAX
MIN
4
MAX
MIN
4
MAX
CLK high or low
t
t
Pulse duration
Setup time
ns
w
SH/LD low
5
6
6
SH/LD high before CLK↑
SER before CLK↑
4
4
4
4
4
4
ns
ns
su
CLK INH before CLK↑
Data before SH/LD↑
SER data after CLK↑
Parallel data after SH/LD↑
SH/LD high after CLK↑
3.5
5
3.5
5
3.5
5
0.5
1
0.5
1
0.5
1
t
h
Hold time
0.5
0.5
0.5
ꢋ
ꢌ
ꢏ
ꢐ
ꢘ
ꢦ
ꢔ
ꢋ
ꢌ
ꢍ
ꢅ
ꢓ
ꢍ
ꢙ
ꢜ
ꢤ
ꢧ
ꢟ
ꢨ
ꢢ
ꢥ
ꢚ
ꢜ
ꢟ
ꢤ
ꢠ
ꢟ
ꢤ
ꢠꢣ
ꢨ
ꢤ
ꢝ
ꢩ
ꢨ
ꢟ
ꢞ
ꢡ
ꢠ
ꢚ
ꢝ
ꢜ
ꢤ
ꢚ
ꢛ
ꢣ
ꢧ
ꢟ
ꢨ
ꢢ
ꢥ
ꢚ
ꢜ
ꢱ
ꢣ
ꢟ
ꢨ
ꢞ
ꢣ
ꢝ
ꢣ
ꢥ
ꢜ
ꢠ
ꢤ
ꢰ
ꢤ
ꢩ
ꢛ
ꢤ
ꢞ
ꢥ
ꢝ
ꢝ
ꢠ
ꢣ
ꢥ
ꢟ
ꢟ
ꢧ
ꢞ
ꢣ
ꢤ
ꢱ
ꢣ
ꢰ
ꢝ
ꢫ
ꢟ
ꢟ
ꢥ
ꢣ
ꢩ
ꢫ
ꢩ
ꢢ
ꢣ
ꢔ
ꢞ
ꢤ
ꢣ
ꢡ
ꢚ
ꢬ
ꢭ
ꢠ
ꢦ
ꢛ
ꢤ
ꢜ
ꢥ
ꢝ
ꢚ
ꢨ
ꢚ
ꢛ
ꢥ
ꢠ
ꢚ
ꢢ
ꢣ
ꢨ
ꢣ
ꢤ
ꢜ
ꢤ
ꢝ
ꢚ
ꢟ
ꢚ
ꢝ
ꢚ
ꢜ
ꢠ
ꢨ
ꢠ
ꢞ
ꢥ
ꢨ
ꢚ
ꢱ
ꢥ
ꢣ
ꢥ
ꢤ
ꢣ
ꢞ
ꢟ
ꢚ
ꢛ
ꢚ
ꢣ
ꢨ
ꢝ
ꢩ
ꢜ
ꢧ
ꢜ
ꢠ
ꢥ
ꢚ
ꢜ
ꢟ
ꢨ
ꢣ
ꢞ
ꢣ
ꢡ
ꢝ
ꢜ
ꢰ
ꢝ
ꢬ
ꢥ
ꢚ
ꢝ
ꢓ
ꢨ
ꢡ
ꢣ
ꢝ
ꢣ
ꢝ
ꢚ
ꢛ
ꢨ
ꢜ
ꢰ
ꢛ
ꢚ
ꢟ
ꢠ
ꢛ
ꢰ
ꢣ
ꢟ
ꢨ
ꢜ
ꢝ
ꢤ
ꢚ
ꢜ
ꢤ
ꢣ
ꢚ
ꢛ
ꢣ
ꢨ
ꢟ
ꢝ
ꢮ
ꢟ
ꢡ
ꢚ
ꢜ
ꢣ
ꢬ
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢂ ꢈꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢂꢈ
ꢋꢈꢌꢈ ꢄꢄ ꢍꢄ ꢎꢄ ꢏ ꢈꢐ ꢑ ꢎꢒꢓ ꢔ ꢀꢕ ꢓꢖ ꢔ ꢌꢍ ꢗ ꢓꢀ ꢔꢍ ꢌ ꢀ
SCLS402K − APRIL 1998 − REVISED APRIL 2005
switching characteristics over recommended operating free-air temperature range,
V
= 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
80*
SN54LV165A SN74LV165A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
50*
40
MAX
MIN
45*
35
MAX
MIN
45
35
1
MAX
C
C
= 15 pF
= 50 pF
L
L
f
MHz
max
pd
65
CLK
SH/LD
H
12.2* 19.8*
13.1* 21.5*
12.9* 21.7*
1*
22*
22
23.5
24
t
1* 23.5*
1
ns
ns
Q
Q
or Q
or Q
C
C
= 15 pF
= 50 pF
H
H
H
L
1*
24*
1
CLK
SH/LD
H
15.3
16.1
15.9
23.3
25.1
25.3
1
1
1
26
28
28
1
1
1
26
28
28
t
pd
H
L
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
115*
90
SN54LV165A SN74LV165A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
65*
60
MAX
MIN
55*
50
MAX
MIN
55
50
1
MAX
C
C
= 15 pF
= 50 pF
L
L
f
MHz
max
pd
CLK
SH/LD
H
8.6* 15.4*
9.1* 15.8*
8.9* 14.1*
1*
18*
18
18.5
16.5
16.9
22
1* 18.5*
1* 16.5*
1
Q
Q
or Q
or Q
C
C
= 15 pF
= 50 pF
t
ns
ns
H
H
H
L
1
CLK
SH/LD
H
10.9
11.3
11.1
14.9
19.3
17.6
1
1
1
16.9
22
1
t
pd
1
H
L
20
1
20
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
V
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
165*
125
6*
SN54LV165A SN74LV165A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
110*
95
MAX
MIN
90*
85
MAX
MIN
90
85
1
MAX
C
C
= 15 pF
= 50 pF
L
L
f
MHz
max
pd
CLK
SH/LD
H
9.9*
9.9*
9*
1* 11.5*
1* 11.5*
1* 10.5*
11.5
11.5
10.5
13.5
13.5
12.5
6*
1
Q
Q
or Q
or Q
C
C
= 15 pF
= 50 pF
t
ns
ns
H
H
H
L
6*
1
CLK
SH/LD
H
7.7
11.9
11.9
11
1
1
1
13.5
13.5
12.5
1
t
pd
7.7
1
H
L
7.6
1
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
= 50 pF, f = 10 MHz
L
V
TYP
36.1
37.5
UNIT
CC
3.3 V
C
Power dissipation capacitance
C
pF
pd
5 V
ꢋ
ꢌ
ꢏ
ꢐ
ꢘ
ꢦ
ꢔ
ꢋ
ꢌ
ꢍ
ꢅ
ꢓ
ꢍ
ꢙ
ꢜ
ꢤ
ꢧ
ꢟ
ꢨ
ꢢ
ꢥ
ꢚ
ꢜ
ꢟ
ꢤ
ꢠ
ꢟ
ꢤ
ꢠ
ꢣ
ꢨ
ꢤ
ꢝ
ꢩ
ꢨ
ꢟ
ꢞ
ꢡ
ꢞꢣ ꢝ ꢜ ꢰꢤ ꢩꢛ ꢥ ꢝ ꢣ ꢟꢧ ꢞꢣ ꢱ ꢣ ꢫꢟ ꢩꢢꢣ ꢤꢚꢬ ꢦ ꢛꢥ ꢨꢥ ꢠꢚ ꢣꢨ ꢜꢝ ꢚꢜ ꢠ ꢞꢥ ꢚꢥ ꢥꢤ ꢞ ꢟꢚ ꢛꢣꢨ
ꢠ
ꢚ
ꢝ
ꢜ
ꢤ
ꢚ
ꢛ
ꢣ
ꢧ
ꢟ
ꢨ
ꢢ
ꢥ
ꢚ
ꢜ
ꢱ
ꢣ
ꢟ
ꢨ
ꢝ
ꢩ
ꢣ
ꢠ
ꢜ
ꢧ
ꢜ
ꢠ
ꢥ
ꢚ
ꢜ
ꢟ
ꢤ
ꢝ
ꢥ
ꢨ
ꢣ
ꢞ
ꢣ
ꢝ
ꢜ
ꢰ
ꢤ
ꢰ
ꢟ
ꢥ
ꢫ
ꢝ
ꢬ
ꢔ
ꢣ
ꢭ
ꢥ
ꢝ
ꢓ
ꢤ
ꢝ
ꢚ
ꢨ
ꢡ
ꢢ
ꢣ
ꢤ
ꢠ ꢛꢥ ꢤ ꢰꢣ ꢟꢨ ꢞꢜ ꢝ ꢠ ꢟꢤ ꢚꢜ ꢤꢡꢣ ꢚ ꢛꢣ ꢝ ꢣ ꢩꢨ ꢟꢞ ꢡꢠꢚ ꢝ ꢮ ꢜꢚꢛ ꢟꢡꢚ ꢤꢟꢚ ꢜꢠꢣ ꢬ
ꢚ
ꢝ
ꢨ
ꢣ
ꢝ
ꢣ
ꢨ
ꢱ
ꢣ
ꢝ
ꢚ
ꢛ
ꢣ
ꢨ
ꢜ
ꢰ
ꢛ
ꢚ
ꢚ
ꢟ
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢂꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆ ꢇꢂ ꢈ
ꢋꢈ ꢌ ꢈꢄ ꢄ ꢍꢄ ꢎꢄ ꢏꢈ ꢐ ꢑ ꢎꢒꢓ ꢔ ꢀ ꢕꢓ ꢖꢔ ꢌꢍ ꢗ ꢓꢀ ꢔꢍ ꢌꢀ
SCLS402K − APRIL 1998 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
GND
t
t
/t
Open
PLH PHL
/t
C
C
L
t
V
CC
L
PLZ PZL
/t
(see Note A)
(see Note A)
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
CC
Timing Input
0 V
t
w
t
h
t
V
CC
su
V
CC
50% V
CC
50% V
CC
Input
Input
50% V
CC
50% V
CC
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
50% V
CC
50% V
50% V
CC
50% V
CC
CC
0 V
0 V
t
t
t
t
t
PLZ
PLH
PHL
PZL
Output
Waveform 1
V
≈V
OH
CC
In-Phase
Output
50% V
50% V
CC
50% V
CC
CC
V
V
OL
+ 0.3 V
S1 at V
(see Note B)
CC
V
OL
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
V
OH
OH
Out-of-Phase
Output
V
OH
− 0.3 V
50% V
CC
50% V
50% V
CC
CC
OL
V
≈0 V
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time, with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PLH
are the same as t
.
dis
PLZ
PZL
PHL
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
9-Aug-2005
PACKAGING INFORMATION
Orderable Device
SN74LV165AD
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV165ADBR
SN74LV165ADBRE4
SN74LV165ADE4
SN74LV165ADGVR
SN74LV165ADGVRE4
SN74LV165ADR
SSOP
SSOP
SOIC
DB
DB
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TVSOP
TVSOP
SOIC
DGV
DGV
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV165ADRE4
SN74LV165ANSR
SN74LV165ANSRE4
SN74LV165APW
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
NS
NS
PW
PW
PW
PW
PW
PW
PW
PW
RGY
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
QFN
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV165APWE4
SN74LV165APWG4
SN74LV165APWR
SN74LV165APWRE4
SN74LV165APWRG4
SN74LV165APWT
SN74LV165APWTE4
SN74LV165ARGYR
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Aug-2005
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
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Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
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