SN74LV164ADBRG4 [TI]
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS; 8位并行输出串行移位寄存器
| 型号： | SN74LV164ADBRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS |
| 文件： | 总21页 (文件大小：701K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LV164A, SN74LV164A
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS403H − APRIL 1998 − REVISED APRIL 2005
D
D
D
D
D
2-V to 5.5-V V Operation
D
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
CC
Max t of 10.5 ns at 5 V
pd
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
Typical V
(Output Ground Bounce)
OLP
<0.8 V at V = 3.3 V, T = 25°C
CC
A
Typical V
(Output V Undershoot)
OHV
OH
− 1000-V Charged-Device Model (C101)
>2.3 V at V = 3.3 V, T = 25°C
CC
A
Support Mixed-Mode Voltage Operation on
All Ports
SN74LV164A . . . RGY PACKAGE
(TOP VIEW)
SN54LV164A . . . FK PACKAGE
(TOP VIEW)
SN54LV164A . . . J OR W PACKAGE
SN74LV164A . . . D, DB, DGV, NS,
OR PW PACKAGE
(TOP VIEW)
1
14
1
2
3
4
5
6
7
14
13
12
11
10
9
3
2
1
20 19
18
A
B
QA
QB
QC
VCC
QH
QG
QF
QE
QG
NC
QF
QA
NC
QB
NC
QC
B
QA
QB
QC
QD
13 QH
12 QG
2
3
4
5
6
4
5
6
7
8
17
16
11
10
9
QF
QE
CLR
15 NC
14
9 10 11 12 13
QE
QD
GND
CLR
CLK
7
8
8
NC − No internal connection
description/ordering information
The ’LV164A devices are 8-bit parallel-out serial shift registers designed for 2-V to 5.5-V V operation.
CC
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
QFN − RGY
SOIC − D
Reel of 1000
Tube of 50
SN74LV164ARGYR
SN74LV164AD
LV164A
LV164A
Reel of 2500
Reel of 2000
Reel of 2000
Tube of 90
SN74LV164ADR
SN74LV164ANSR
SN74LV164ADBR
SN74LV164APW
SN74LV164APWR
SN74LV164APWT
SN74LV164ADGVR
SNJ54LV164AJ
SOP − NS
74LV164A
LV164A
SSOP − DB
−40°C to 85°C
Reel of 2000
Reel of 250
Reel of 2000
Tube of 25
TSSOP − PW
LV164A
TVSOP − DGV
CDIP − J
LV164A
SNJ54LV164AJ
SNJ54LV164AW
SNJ54LV164AFK
−55°C to 125°C
CFP − W
Tube of 150
Tube of 55
SNJ54LV164AW
SNJ54LV164AFK
LCCC − FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2005, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV164A, SN74LV164A
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS403H − APRIL 1998 − REVISED APRIL 2005
description/ordering information (continued)
These devices feature AND-gated serial (A and B) inputs and an asynchronous clear (CLR) input. The gated
serial inputs permit complete control over incoming data, as a low at either input inhibits entry of the new data
and resets the first flip-flop to the low level at the next clock pulse. A high-level input enables the other input,
which then determines the state of the first flip-flop. Data at the serial inputs can be changed while the clock
is high or low, provided the minimum setup time requirements are met. Clocking occurs on the low-to-high-level
transition of the clock (CLK) input.
FUNCTION TABLE
INPUTS
OUTPUTS
CLR
L
CLK
A
X
X
H
L
B
X
X
H
X
L
Q
Q
. . . Q
B
A
H
X
L
↑
↑
↑
L
L
L
H
Q
Q
Q
Q
Q
Q
H0
Q
Gn
Q
Gn
Q
Gn
A0
B0
An
An
An
H
H
H
L
L
H
X
Q
, Q , Q = the level of Q , Q , or Q , respectively,
B0 H0 A B H
A0
before the indicated steady-state input conditions were
established.
Q
, Q = the level of Q or Q before the most recent
An
Gn A G
↑ transition of the clock: indicates a 1-bit shift.
logic diagram (positive logic)
8
CLK
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
1
2
A
B
R
R
R
R
R
R
R
R
9
CLR
3
4
5
6
10
11
12
13
Q
Q
Q
Q
Q
Q
Q
Q
H
A
B
C
D
E
F
G
Pin numbers shown are for the D, DB, DGV, J, NS, PW, RGY, and W packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV164A, SN74LV164A
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS403H − APRIL 1998 − REVISED APRIL 2005
typical clear, shift, and clear sequences
CLR
A
B
CLK
Q
Q
Q
Q
A
B
C
D
Q
E
Q
F
Q
G
Q
H
Clear
Clear
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV164A, SN74LV164A
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS403H − APRIL 1998 − REVISED APRIL 2005
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
IK
I
Output clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
OK
O
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
O
O
CC
Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
CC
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
JA
(see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
(see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV164A, SN74LV164A
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS403H − APRIL 1998 − REVISED APRIL 2005
recommended operating conditions (see Note 5)
SN54LV164A
SN74LV164A
UNIT
MIN
2
MAX
MIN
2
MAX
V
V
Supply voltage
5.5
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
1.5
1.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
V
V
V
× 0.7
V
V
V
× 0.7
CC
CC
CC
CC
CC
CC
High-level input voltage
V
V
IH
× 0.7
× 0.7
× 0.7
× 0.7
0.5
0.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
V
V
V
× 0.3
V
V
V
× 0.3
CC
CC
V
IL
Low-level input voltage
× 0.3
× 0.3
× 0.3
× 0.3
CC
CC
CC
CC
V
V
Input voltage
0
0
5.5
0
0
5.5
V
V
I
Output voltage
V
CC
V
CC
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
−50
−50
μA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
−2
−6
−2
−6
−12
50
2
I
High-level output current
Low-level output current
OH
mA
−12
50
μA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
2
I
OL
6
6
mA
12
12
200
100
20
85
200
100
20
Δt/Δv
Input transition rise or fall rate
Operating free-air temperature
ns/V
T
−55
125
−40
°C
A
NOTE 5: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV164A
SN74LV164A
PARAMETER
TEST CONDITIONS
UNIT
V
CC
MIN
−0.1
2
TYP
MAX
MIN
−0.1
2
TYP
MAX
I
I
I
I
I
I
I
I
= −50 μA
= −2 mA
= −6 mA
= −12 mA
= 50 μA
= 2 mA
2 V to 5.5 V
2.3 V
V
CC
V
CC
OH
OH
OH
OH
OL
OL
OL
OL
V
OH
V
OL
V
3 V
2.48
3.8
2.48
3.8
4.5 V
2 V to 5.5 V
2.3 V
0.1
0.4
0.44
0.55
1
0.1
0.4
0.44
0.55
1
V
= 6 mA
3 V
= 12 mA
4.5 V
I
I
V = 5.5 V or GND
0 to 5.5 V
5.5 V
μA
μA
μA
pF
I
I
V = V or GND,
I = 0
O
20
20
CC
I
CC
I
off
V or V = 0 to 5.5 V
0
5
5
I
O
C
V = V or GND
3.3 V
2.2
2.2
i
I
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV164A, SN74LV164A
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS403H − APRIL 1998 − REVISED APRIL 2005
timing requirements over recommended operating free-air temperature range, VCC = 2.5 V 0.2 V
(unless otherwise noted) (see Figure 1)
T
= 25°C
SN54LV164A SN74LV164A
A
UNIT
MIN
6
MAX
MIN
6.5
7.5
8.5
3
MAX
MIN
6.5
7.5
8.5
3
MAX
CLR low
t
w
Pulse duration
ns
CLK high or low
Data before CLK↑
CLR inactive
6.5
6.5
3
Setup time
Hold time
t
t
ns
ns
su
Data after CLK↑
−0.5
0
0
h
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V 0.3 V
(unless otherwise noted) (see Figure 1)
T
= 25°C
SN54LV164A SN74LV164A
A
UNIT
MIN
5
MAX
MIN
5
MAX
MIN
5
MAX
CLR low
t
w
Pulse duration
ns
CLK high or low
Data before CLK↑
CLR inactive
5
5
5
5
6
6
Setup time
Hold time
t
t
ns
ns
su
2.5
0
2.5
0
2.5
0
Data after CLK↑
h
timing requirements over recommended operating free-air temperature range, VCC = 5 V 0.5 V
(unless otherwise noted) (see Figure 1)
T
= 25°C
SN54LV164A SN74LV164A
A
UNIT
MIN
5
MAX
MIN
5
MAX
MIN
5
MAX
CLR low
t
w
Pulse duration
ns
CLK high or low
Data before CLK↑
CLR inactive
5
5
5
4.5
2.5
1
4.5
2.5
1
4.5
2.5
1
Setup time
Hold time
t
t
ns
ns
su
Data after CLK↑
h
switching characteristics over recommended operating free-air temperature range,
VCC = 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
105*
85
SN54LV164A SN74LV164A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MHz
ns
MIN
55*
45
MAX
MIN
50*
40
MAX
MIN
50
40
1
MAX
C = 15 pF
L
f
max
C = 50 pF
L
t
t
t
t
CLK
CLR
CLK
CLR
9.2* 17.6*
1*
20*
18*
24
20
18
24
22
Q
Q
Q
Q
pd
C = 15 pF
L
8.6*
11.5
10.8
16*
21.1
19.5
1*
1
1
1
1
PHL
pd
C = 50 pF
L
ns
1
22
PHL
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV164A, SN74LV164A
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS403H − APRIL 1998 − REVISED APRIL 2005
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
SN54LV164A SN74LV164A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MHz
ns
MIN
80*
50
MAX
MIN
65*
45
1*
MAX
MIN
65
45
1
MAX
C = 15 pF
L
155*
120
f
t
max
C = 50 pF
L
CLK
CLR
CLK
CLR
6.4* 12.8*
6* 12.8*
15*
15*
15
15
pd
Q
Q
C = 15 pF
L
t
t
1*
1
PHL
8.3
7.9
16.3
16.3
1
18.5
18.5
1
18.5
18.5
pd
ns
C = 50 pF
L
t
1
1
PHL
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
220*
165
4.5*
4.2*
6
SN54LV164A SN74LV164A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MHz
ns
MIN
125*
85
MAX
MIN
105*
75
MAX
MIN
105
75
1
MAX
C = 15 pF
L
f
t
max
C = 50 pF
L
CLK
CLR
CLK
CLR
9*
8.6*
11
1* 10.5*
10.5
10
pd
Q
Q
C = 15 pF
L
t
t
1*
1
10*
12.5
12.5
1
PHL
1
12.5
12.5
pd
ns
C = 50 pF
L
t
5.8
10.6
1
1
PHL
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 6)
SN74LV164A
PARAMETER
UNIT
MIN
TYP
0.28
MAX
V
OL(P)
V
OL(V)
V
OH(V)
V
IH(D)
V
IL(D)
Quiet output, maximum dynamic V
0.8
V
V
V
V
V
OL
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
−0.22
3.09
−0.8
OL
OH
2.31
0.99
NOTE 6: Characteristics are for surface-mount packages only.
operating characteristics, TA = 25°C
PARAMETER
TEST CONDITIONS
f = 10 MHz
V
TYP
48.1
47.5
UNIT
CC
3.3 V
5 V
C
Power dissipation capacitance
C = 50 pF,
pF
pd
L
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV164A, SN74LV164A
8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS
SCLS403H − APRIL 1998 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
S1
Open
R
= 1 kΩ
L
TEST
/t
S1
From Output
Under Test
Test
Point
From Output
Under Test
GND
t
t
Open
PLH PHL
t
C
C
L
/t
V
CC
L
PLZ PZL
(see Note A)
(see Note A)
/t
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
Timing Input
CC
0 V
t
w
t
h
t
V
su
CC
V
CC
50% V
50% V
Input
Input
CC
CC
50% V
50% V
CC
Data Input
0 V
CC
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
50% V
50% V
50% V
50% V
CC
CC
CC
CC
0 V
0 V
t
t
t
t
t
PLH
PHL
PZL
PLZ
Output
Waveform 1
V
≈V
OH
CC
In-Phase
Output
50% V
50% V
CC
50% V
CC
CC
V
V
+ 0.3 V
OL
S1 at V
CC
V
OL
V
OL
(see Note B)
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
OH
V
OH
Out-of-Phase
Output
− 0.3 V
OH
50% V
50% V
50% V
CC
CC
CC
≈0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time, with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
.
PLZ
PZL
PHL
PHZ
dis
are the same as t
PZH
en
are the same as t .
PLH pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
8-Dec-2009
PACKAGING INFORMATION
Orderable Device
SN74LV164AD
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV164ADBR
SN74LV164ADBRE4
SN74LV164ADBRG4
SN74LV164ADE4
SSOP
SSOP
SSOP
SOIC
DB
DB
DB
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV164ADG4
SN74LV164ADGVR
SN74LV164ADGVRE4
SN74LV164ADGVRG4
SN74LV164ADR
SOIC
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TVSOP
TVSOP
TVSOP
SOIC
DGV
DGV
DGV
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV164ADRE4
SN74LV164ADRG4
SN74LV164ANSR
SN74LV164ANSRE4
SN74LV164ANSRG4
SN74LV164APW
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
NS
NS
NS
PW
PW
PW
PW
PW
PW
PW
PW
PW
RGY
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
VQFN
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV164APWE4
SN74LV164APWG4
SN74LV164APWR
SN74LV164APWRE4
SN74LV164APWRG4
SN74LV164APWT
SN74LV164APWTE4
SN74LV164APWTG4
SN74LV164ARGYR
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Dec-2009
Orderable Device
SN74LV164ARGYRG4
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
ACTIVE
VQFN
RGY
14
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Aug-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LV164ADBR
SN74LV164ADGVR
SN74LV164ADR
SSOP
TVSOP
SOIC
DB
DGV
D
14
14
14
14
14
14
14
2000
2000
2500
2000
2000
250
330.0
330.0
330.0
330.0
330.0
330.0
330.0
16.4
12.4
16.4
16.4
12.4
12.4
12.4
8.2
6.8
6.5
8.2
6.9
6.9
3.75
6.6
4.0
2.5
1.6
2.1
2.5
1.6
1.6
1.15
12.0
8.0
16.0
12.0
16.0
16.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
9.0
8.0
SN74LV164ANSR
SN74LV164APWR
SN74LV164APWT
SN74LV164ARGYR
SO
NS
10.5
5.6
12.0
8.0
TSSOP
TSSOP
VQFN
PW
PW
RGY
5.6
8.0
3000
3.75
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Aug-2010
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LV164ADBR
SN74LV164ADGVR
SN74LV164ADR
SSOP
TVSOP
SOIC
DB
DGV
D
14
14
14
14
14
14
14
2000
2000
2500
2000
2000
250
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
33.0
29.0
33.0
33.0
29.0
29.0
29.0
SN74LV164ANSR
SN74LV164APWR
SN74LV164APWT
SN74LV164ARGYR
SO
NS
TSSOP
TSSOP
VQFN
PW
PW
RGY
3000
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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相关型号：
SN74LV164ANSE4
LV/LV-A/LVX/H SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO14, PLASTIC, SO-14
TI
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