SN74HC7032D-00 [TI]
HC/UH SERIES, QUAD 2-INPUT OR GATE, PDSO14;
| 型号： | SN74HC7032D-00 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HC/UH SERIES, QUAD 2-INPUT OR GATE, PDSO14 输入元件 光电二极管 逻辑集成电路 |
| 文件： | 总12页 (文件大小：592K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCLS036E − MARCH 1984 − REVISED NOVEMBER 2004
SN54HC7032 . . . J OR W PACKAGE
SN74HC7032 . . . D, N, OR NS PACKAGE
(TOP VIEW)
D
D
Wide Operating Voltage Range of 2 V to 6 V
Operation From Very Slow Input
Transitions
14
13
12
11
10
9
1A
1B
V
CC
1
2
3
4
5
6
7
D
D
D
D
D
D
D
Same Pinouts as ’HC32
4B
4A
4Y
3B
3A
3Y
Outputs Can Drive Up To 10 LSTTL Loads
1Y
Low Power Consumption, 20-µA Max I
Typical t = 14 ns
pd
4-mA Output Drive at 5 V
CC
2A
2B
2Y
8
GND
Low Input Current of 1 µA Max
Temperature-Compensated Threshold
Levels
SN54HC7032 . . . FK PACKAGE
(TOP VIEW)
D
High Noise Immunity
description/ordering information
3
2
1
20 19
18
4A
NC
4Y
In these devices, each circuit functions as a
quadruple OR gate. They perform the Boolean
1Y
NC
2A
4
5
6
7
8
17
16
Y + A • B or Y + A ) B
function
in positive
15 NC
14
9 10 11 12 13
NC
2B
logic. However, because of the Schmitt action, the
inputs have different input threshold levels for
positive- and negative-going signals.
3B
These circuits are temperature compensated and
can be triggered from the slowest of input ramps
and still give clean jitter-free output signals.
NC − No internal connection
ORDERING INFORMATION
ORDERABLE
TOP-SIDE
MARKING
†
PACKAGE
T
A
PART NUMBER
SN74HC7032N
SN74HC7032D
SN74HC7032DR
SN74HC7032DT
SN74HC7032NSR
SNJ54HC7032J
SNJ54HC7032W
SNJ54HC7032FK
PDIP − N
SOIC − D
Tube of 25
Tube of 50
Reel of 2500
Reel of 250
Reel of 2000
Tube of 25
Tube of 150
Tube of 55
SN74HC7032N
−40°C to 85°C
HC7032
SOP − NS
CDIP − J
HC7032
SNJ54HC7032J
SNJ54HC7032W
SNJ54HC7032FK
−55°C to 125°C
CFP − W
LCCC − FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
Y
A
B
X
H
L
H
X
L
H
H
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢈꢉ ꢊ ꢀ ꢁꢆ ꢃ ꢄꢅꢆ ꢇ ꢈ ꢉ
ꢋꢌ ꢍ ꢎꢏ ꢌ ꢐꢑ ꢒ ꢐꢓ ꢀꢔ ꢕ ꢔ ꢖꢒ ꢗꢓ ꢏ ꢘ ꢍꢕꢒ ꢀ
ꢙꢔ ꢕ ꢄ ꢀꢅ ꢄ ꢚꢔ ꢕ ꢕꢗꢕ ꢏꢔ ꢘ ꢘꢒ ꢏ ꢔ ꢁꢐ ꢌꢕ ꢀ
SCLS036E − MARCH 1984 − REVISED NOVEMBER 2004
logic diagram, each gate (positive logic)
A
Y
B
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HC7032
MIN NOM MAX
SN74HC7032
UNIT
MIN NOM
MAX
V
V
V
Supply voltage
2
0
5
6
2
0
5
6
V
V
CC
Input voltage
V
V
V
V
I
CC
CC
Output voltage
0
0
V
O
CC
CC
85
T
A
Operating free-air temperature
−55
125
−40
°C
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
CC
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2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCLS036E − MARCH 1984 − REVISED NOVEMBER 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
TYP
1.2
2.5
3.3
0.6
1.6
2
SN54HC7032 SN74HC7032
A
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
0.7
1.55
2.1
0.3
0.9
1.2
0.2
0.4
0.5
MAX
1.5
3.15
4.2
1
MIN
0.7
1.55
2.1
0.3
0.9
1.2
0.2
0.4
0.5
1.9
4.4
5.9
3.7
5.2
MAX
1.5
3.15
4.2
1
MIN
0.7
MAX
1.5
3.15
4.2
1
2 V
4.5 V
6 V
1.55
2.1
V
T+
V
T−
V
T+
V
2 V
0.3
4.5 V
6 V
2.45
3.2
1.2
2.1
2.5
2.45
3.2
1.2
2.1
2.5
0.9
2.45
3.2
1.2
2.1
2.5
V
V
1.2
2 V
0.6
0.9
1.3
0.2
4.5 V
6 V
0.4
− V
T−
0.5
2 V
1.9 1.998
4.4 4.499
5.9 5.999
1.9
4.5 V
6 V
4.4
I
= −20 µA
OH
5.9
V
V
V = V or V
IH
V
V
OH
OL
I
IL
I
I
= −4 mA
4.5 V
6 V
3.98
5.48
4.3
5.8
3.84
5.34
OH
= −5.2 mA
OH
2 V
0.002
0.001
0.001
0.17
0.15
0.1
0.1
0.1
0.1
0.26
0.26
100
2
0.1
0.1
0.1
0.1
4.5 V
6 V
I
= 20 µA
OL
0.1
0.1
V = V or V
I
IH
IL
I
I
= 4 mA
4.5 V
6 V
0.4
0.33
0.33
1000
20
OL
= 5.2 mA
0.4
OL
I
I
V = V
I
or 0
6 V
1000
40
nA
µA
pF
I
CC
V = V
I
or 0,
I
O
= 0
6 V
CC
CC
C
2 V to 6 V
3
10
10
10
i
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
60
SN54HC7032 SN74HC7032
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
MAX
130
26
MIN
MAX
195
39
MIN
MAX
163
33
2 V
4.5 V
6 V
18
t
A or B
Y
ns
pd
t
14
22
33
28
2 V
28
75
110
22
95
t
Any
4.5 V
6 V
8
15
19
ns
6
13
19
16
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance per gate
No load
20
pF
pd
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3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢇ ꢈꢉ ꢊ ꢀ ꢁꢆ ꢃ ꢄꢅꢆ ꢇ ꢈ ꢉ
ꢋꢌ ꢍ ꢎꢏ ꢌ ꢐꢑ ꢒ ꢐꢓ ꢀꢔ ꢕ ꢔ ꢖꢒ ꢗꢓ ꢏ ꢘ ꢍꢕꢒ ꢀ
ꢙꢔ ꢕ ꢄ ꢀꢅ ꢄ ꢚꢔ ꢕ ꢕꢗꢕ ꢏꢔ ꢘ ꢘꢒ ꢏ ꢔ ꢁꢐ ꢌꢕ ꢀ
SCLS036E − MARCH 1984 − REVISED NOVEMBER 2004
PARAMETER MEASUREMENT INFORMATION
V
CC
From Output
Under Test
Test
Point
Input
50%
50%
0 V
C
= 50 pF
L
t
t
PLH
PHL
90%
(see Note A)
V
V
OH
In-Phase
Output
90%
t
50%
10%
50%
10%
LOAD CIRCUIT
OL
t
r
f
f
t
t
PLH
PHL
90%
V
CC
V
V
90%
t
90%
OH
Input
50%
10%
50%
10%
90%
t
Out-of-Phase
Output
50%
10%
50%
10%
0 V
OL
t
r
f
t
r
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
C includes probe and test-fixture capacitance.
L
O
r
f
C. The outputs are measured one at a time, with one input transition per measurement.
D. and t are the same as t
t
.
PLH
PHL pd
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
20-Aug-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
SN74HC7032D
SN74HC7032DE4
SN74HC7032DG4
SN74HC7032DT
SN74HC7032DTE4
SN74HC7032DTG4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
D
D
D
D
D
14
14
14
14
14
14
50
50
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
50
Green (RoHS
& no Sb/Br)
250
250
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SN74HC7032N
ACTIVE
ACTIVE
PDIP
PDIP
N
N
14
14
25
25
Pb-Free (RoHS)
Pb-Free (RoHS)
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
SN74HC7032NE4
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
20-Aug-2011
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HC7032DT
SOIC
D
14
250
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC 14
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 38.0
SN74HC7032DT
D
250
Pack Materials-Page 2
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