SN74CBTU4411_技术文档

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SCDS192 − APRIL 2005

D

Supports SSTL_18 Signaling Levels

Suitable for DDR-II Applications

D

Internal 400-W Pulldown Resistors

D

Low Differential and Rising/Falling Edge

Skew

D−Port Outputs Are Precharged by Bias

Voltage (V

)

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

BIAS

Internal Termination for Control Inputs

High Bandwidth (334 MHz Min)

ESD Performance Tested Per JESD 22

− 2000-V Human-Body Model

(A114-B, Class II)

Low and Flat ON-State Resistance (r

on

)

Characteristics, (r = 17 W Max)

on

− 1000-V Charged-Device Model (C101)

description/ordering information

The SN74CBTU4411 is a high-bandwidth, SSTL_18 compatible FET multiplexer/demultiplexer with low

ON-state resistance (r ). The device utilizes an internal charge pump to elevate the gate voltage of the pass

on

transistor, providing a low and flat r . The low and flat r allows for minimal propagation delay and supports

on

rail-to-rail signaling on data input/output (I/O) ports. The device also features very low data I/O capacitance to

minimize capacitive loading and signal distortion on the data bus. Matched r and I/O capacitance among

on

channels results in extremely low differential and rising/falling edge skew. This allows the device to show optimal

performance in DDR-II applications.

The device is organized as an 11-bit 1-of-4 multiplexer/demultiplexer with a single switch-enable (EN) input.

When EN is low, the switch is enabled and the H port is connected to one of the D ports. Ports D0 to D9 for the

disabled channels are connected to V

for the disabled D10 ports. When DQS_EN is low, this voltage is V

D10 ports are connected to an internal voltage (V

through a 400 Ω resistor. DQS_EN determines the output voltage

BIAS

. When DQS_EN is high, the disabled

BIAS

) source, which is approximately equal to 0.7 V

.

BIAS_DQS

DD

When EN is high, all the channels are disabled. Ports D0 to D9 are connected to V

disabled output voltage is determined by the DQS_EN input. When DQS_EN is low, this voltage is V

. For the D10 port, the

BIAS

. When

BIAS

DQS_EN is high, this voltage is V

.

DD

The select (S0, S1) inputs control the data path of each multiplexer/demultiplexer. The EN and TC inputs

determine the internal termination for S0 and S1 inputs. When EN is low, the termination is determined by the

TC input. When both EN and TC are low, termination resistors are disconnected from the S inputs. When EN

is low and TC is high, both pullup and pulldown resistors are connected to the S inputs. When EN is high, only

the pulldown termination resistors are connected to the S inputs, regardless of the voltage level at the TC input.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

T

PACKAGE

LFBGA − GST

A

0°C to 85°C

Tape and reel

SN74CBTU4411GSTR

CTU4411

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Copyright  2005, Texas Instruments Incorporated

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1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCDS192 − APRIL 2005

GST PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

9

10 11

A

B

C

D

E

F

G

H

J

K

L

terminal assignments

1

2

DQS_EN

S0

3

4

5

6

7

8

9

10

0D2

H2

11

A

B

C

D

E

F

S1

TC

V

0D0

1D0

H0

2D0

3D0

1D1

0D1

2D1

H1

3D1

1D2

2D2

3D2

1D3

3D3

0D4

1D4

3D4

0D5

2D5

3D5

DD

GND

DD

V

EN

0D3

H3

REF

V

GND

3D10

H10

BIAS

2D10

1D10

0D10

3D9

2D3

GND

H4

G

H

J

GND

2D9

2D4

1D5

H5

1D9

H9

K

L

0D9

GND

2D8

H8

0D8

3D7

H7

0D7

1D7

GND

3D6

H6

0D6

1D6

3D8

1D8

2D7

2D6

V

DD

2

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SCDS192 − APRIL 2005

FUNCTION TABLES

INPUTS

DQS_EN

INPUT/OUTPUT

Hn

FUNCTION

EN

S1

S0

Hn = 0Dn

1Dn, 2Dn, 3Dn connected to V

L

0Dn

1Dn

2Dn

3Dn

BIAS

Hn = 1Dn

0Dn, 2Dn, 3Dn connected to V

L

H

L

Hn = 2Dn

0Dn, 1Dn, 3Dn connected to V

Hn = 3Dn

0Dn, 1Dn, 2Dn connected to V

H

H0−H9 = 0D0−0D9

1D0−1D9, 2D0−2D9, 3D0−3D9 connected to V

H10 = 0D10

BIAS

L

H

L

H

L

0Dn

1Dn

2Dn

3Dn

†

1D10, 2D10, 3D10 connected to V

BIAS_DQS

H0−H9 = 1D0−1D9

0D0−0D9, 2D0−2D9, 3D0−3D9 connected to V

H10 = 1D10

BIAS

†

0D10, 2D10, 3D10 connected to V

BIAS_DQS

H0−H9 = 2D0−2D9

0D0−0D9, 1D0−1D9, 3D0−3D9 connected to V

H10 = 2D10

BIAS

H

†

0D10, 1D10, 3D10 connected to V

BIAS_DQS

H0−H9 = 3D0−3D9

0D0−0D9, 1D0−1D9, 2D0−2D9 connected to V

H10 = 3D10

BIAS

H

†

0D10, 1D10, 2D10 connected to V

BIAS_DQS

H

L

X

Z

0Dn, 1Dn, 2Dn, 3Dn connected to V

BIAS

0D0−0D9, 1D0−1D9, 2D0−2D9, 3D0−3D9 connected to V

BIAS

H

0D10, 1D10, 2D10, 3D10 connected to V

DD

†

V

is an internal voltage condition.

BIAS_DQS

INPUTS

FUNCTION

EN

L

TC

L

Termination resistors disconnected from S inputs

Termination resistors connected with S inputs

L

H

Pulldown termination resistor connected and pullup

termination resistor disconnected from the S inputs

H

X

3

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SCDS192 − APRIL 2005

logic diagram (positive logic)

D1

V

BIAS

B5

A4

A5

A6

B6

H0

0D0

1D0

2D0

3D0

SW1

F2

G1

F1

E1

E2

0D10

H10

SW2

1D10

2D10

3D10

SW2

V

DD

C2

B1

EN

TC

†

M1

CONTROL DECODE

LOGIC

V

REF

†

r

1

B2

S0

†

r

2

†

M2

V

DD

†

M1

†

r

1

A1

S1

†

r

2

†

M2

A2

DQS_EN

†

r

+ r (M1), r + r (M2) = 160 Ω Typical.

on on

1

2

4

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SCDS192 − APRIL 2005

simplified schematic, each FET switch (SW1)

†

‡

D

H

V

DD

§

r

3

Charge

Pump

§

M3

¶

EN

V

BIAS

†

‡

§

¶

Applicable for ports H0 through H9

Applicable for ports D0 through D9

r

+ r (M3) = 400 Ω Typical.

on

3

EN is the internal enable signal applied to the switch.

simplified schematic, each FET switch (SW2)

V

DD

#

||

M4

EN_DQS1

||

r

4

H10

V

DD

V

D10

BIAS_DQS

r h

6

r k

5

Charge

Pump

#

EN_DQS2

M6h

M5k

#

EN2

#

EN1

V

BIAS

#

||

k

h

EN_DQS1, EN_DQS2, EN1, and EN2 are the internal enable signals applied to the switch.

r

4

r

5

r

6

+ r (M4) = 1 kΩ Typical.

on

+ r (M5) = 400 Ω Typical.

on

+ r (M6) = 2.3 kΩ Typical.

on

5

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SCDS192 − APRIL 2005

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 2.5 V

DD

Control input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 2.5 V

Switch I/O voltage range, V (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 2.5 V

Control input clamp current, I (V < 0 or V > 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

IN

I/O

IK IN

IN

I/O port clamp current, I

(V < 0 or V > 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

I/OK I/O

I/O

ON-state switch current, I (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

Continuous current through V

I/O

or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

DD

Package thermal impedance, θ (see Note 5)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD°C/W

JA

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltages are with respect to ground, unless otherwise specified.

2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

3. V and V are used to denote specific conditions for V

I/O

.

I

O

4. I and I are used to denote specific conditions for I .

I

O

I/O

5. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 6)

MIN

TYP

MAX

UNIT

V

Supply voltage

1.7

0.49 V

0

1.8

1.9

V

DD

Reference supply voltage

0.5 V

0.51 V

REF

BIAS

DD

BIAS supply voltage

0.3 V

0.33 V

High-level control input voltage (S)

High-level control input voltage (EN, TC, DQS_EN)

Low-level control input voltage (S)

Low-level control input voltage (EN, TC, DQS_EN)

Data input/output voltage

V

REF

+250 mV

V

IH

0.65 V

DD

V

−250 mV

REF

0.35 V

V

IL

DD

0

V

I/O

DD

85

T

A

Operating free-air temperature

°C

NOTE 6: All unused control inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

DD

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

6

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SCDS192 − APRIL 2005

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

T

= 70 °C

T = 0 °C TO 85 °C

A

PARAMETER

TEST CONDITIONS

UNIT

†

TYP

MIN MAX

MIN

MAX

−1.8

1.275

1.8

Control

inputs

‡

V

= 1.7 V,

I

= −18 mA

V

IK

DD

IN

DQS_EN = V

DD

§

V

D10

V

= 1.7 V,

1.1

BIAS_DQS

DD

V

D10

EN = V

DD

,

I

O

= 100 µA

1.6

OH

DQS_EN = V

DD,

Control

inputs

I

V

= 1.9 V,

V

= V

DD

or GND

1

µA

IN

DD

IN

§

= 0 to 1.9 V, Switch OFF,

open

O

¶

V

= 1.9 V,

10

OZ

DD

V = 0,

I

V

BIAS

I

= 0,

DD

I/O

S0, S1 = V or

Switch ON

or OFF

TC = GND,

EN = GND,

0.7

2.5

mA

IH

I

CC

V

IL

,

EN = V

DD

500

µA

I

= 0,

I/O

V

= 1.9 V,

DD

S0 or S1 input switching at

50% duty cycle, Data I/O are

open

#

0.5 mA/MHz

I

TC = GND,

EN = GND,

CCD

V

= 1.9 V,

EN = GND,

DD

TC = GND,

S port

2.5

3.5

pF

V

IN

= V

REF

250 mV

C

EN, TC,

DQS_EN

inputs

in

V

= 1.9 V,

V

IN

= 0 or 1.9 V

2.5

DD

= 0.5 V

I/O

DD

C

r

H port

Switch OFF,

Switch ON,

V

open

=

2.5

4.6

17

pF

Ω

io(OFF)

BIAS

0.4 V

V

I/O

0.4 V,

DD

BIAS

io(ON)

||

GND

V

= 1.7 V,

DD

V = 0.5 V

I

O

= 10 mA

6

10

on

0.5 V,

I

DD

= 1.7 V,

V

V = 0.5 V

I

0.25 V

0.5 V

1.5

2.5

3

5

Ω

DD

DQS_EN = V

DD

∆r (flat)

k

on

DD,

V = 0.5 V

I

O

= 10 mA

DD

V

= 1.7 V

110

280

160

400

210

520

3000

1300

r

S port

D0−D10

D10

DD

term

DQS_EN = GND

= 1.7 V

= 1.7 V,

Ω

r

DD

pulldown

DQS_EN = V

DD,

EN = GND

1600

700

2300

1000

DQS_EN = V

DD,

r

D10

pullup

V

†

‡

§

¶

#

and I refer to control inputs. V , V , I , and I refer to data pins.

IN I O I O

IN

All typical values are at V

= 1.8 V (unless otherwise noted), T = 25°C.

DD

A

V

refers to the clamp voltage due to the internal diode, which is connected from each control input to GND.

IK

For the leakage current test on S0 and S1, EN and TC inputs are set to low.

For I/O ports, the parameter I includes the input leakage current. I applies only to the H port.

OZ OZ

The frequency of S0 and S1 inputs, for example, for a data I/O rate of 533 Mbit/s, with a burst of 4, the required frequency is for S0 or S1 input

is ≅ 66 MHz (533/8). The total I due to switching S0, S1 will be approximately 27 mA (66 MHz × 0.4 mA/MHz).

Measured by the voltage drop between the D and H terminals at the indicated current through the switch. ON-state resistance is determined by

the lower of the voltages of the two (D or H) terminals.

CC

||

k

∆r (flat) is the difference of maximum r and minimum r for a specific channel in a specific device.

on

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢃꢃ ꢈꢈ

ꢈꢈꢉ ꢅ ꢊ ꢆ ꢈ ꢉꢋꢌ ꢉꢃ ꢌ ꢍ ꢆ ꢎꢇ ꢏꢆꢊ ꢐ ꢏ ꢍꢑ ꢍꢒ ꢓ ꢔꢍ ꢎꢇꢏꢆ ꢊꢐ ꢏꢍ ꢑꢍꢒ

ꢈꢕ ꢖꢉꢗ ꢔ ꢔꢒ ꢉꢊ ꢊ ꢀꢘ ꢊ ꢆꢄ ꢙ ꢘ ꢊ ꢆꢙ ꢄꢙ ꢚꢒꢛ ꢍ ꢐ ꢇꢎ ꢐ ꢚꢁꢔ ꢐꢒꢍ ꢄꢙꢚꢒ ꢛꢍ ꢔ ꢋ ꢇꢆ ꢐꢇꢆ ꢀ

SCDS192 − APRIL 2005

switching characteristics over recommended operating free-air temperature range (unless

otherwise noted) (see Figures 1 and 2)

T

= 70 °C

T = 0 °C TO 85 °C

A

FROM

(INPUT)

TO

(OUTPUT)

A

PARAMETER

UNIT

MIN

MAX

MIN

334

84

TYP

MAX

D or H port

f

MHz

max

†

S port

t

D or H

297

ps

H or D

pd

(t

‡

, t

)

D

750

2100

85

S

en PZL PZH

‡

)

dis PLZ PHZ

(t

, t

osk

esk

t

40

ps

§

20

µs

start

†

‡

§

EN = GND, TC = GND

= open

V

BIAS

t

is the time required for the charge-pump circuit output voltage to reach a steady state value after V

is applied.

DD

start

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢃꢃ ꢈꢈ

ꢈ

ꢉ

ꢙ

ꢅ

ꢊ

ꢄ

ꢆ

ꢙ

ꢈ

ꢚ

ꢉ

ꢋ

ꢒ

ꢌ

ꢛ

ꢉ

ꢍ

ꢃ

ꢌ

ꢐ

ꢍ

ꢇ

ꢆ

ꢎ

ꢐ

ꢇ

ꢚ

ꢏ

ꢁ

ꢆ

ꢔ

ꢊ

ꢐ

ꢏ

ꢒ

ꢍ

ꢑ

ꢄ

ꢍ

ꢙ

ꢒ

ꢚ

ꢓ

ꢔ

ꢍ

ꢎ

ꢒ ꢛꢍ ꢔ ꢋ ꢇꢆ ꢐ ꢇꢆꢀ

ꢇ

ꢏ

ꢆ

ꢊ

ꢐ

ꢏ

ꢍ

ꢑ

ꢍ

ꢒ

ꢈ

ꢕ

ꢖ

ꢉ

ꢗ

ꢔ

ꢒ

ꢉ

ꢊ

ꢀ

ꢘꢊ

ꢆ

ꢄ

ꢙ

ꢘ

ꢊ

ꢆ

SCDS192 − APRIL 2005

PARAMETER MEASUREMENT INFORMATION

(Enable and Disable Times)

V

DD

Z

O

= 40 Ω

V

IN

V

50 Ω

G1

TEST CIRCUIT

DUT

V

DD

2 y V

†

T1

Z

O

= 40 Ω

Z

O

= 40 Ω

R

V

I

V

O

DD

L

GND

120 Ω

C

R

L

G2

L

(see Note A)

†

T1

V

I

C

V

∆

R

V

DD

TEST

L

t

/t

1.8 V 0.1 V

2 y V

DD

1 kΩ

GND

6 pF

0.125 V

PLZ PZL

t

/t

PHZ PZH

GND

V

DD

Output

Control

V

+0.25 V

REF

V

REF

V

REF

(V

IN

)

−0.25 V

REF

(see Note B)

t

PZL

PLZ

Output

V

OH

Waveform 1 (V )

O

0.5 V

DD

†

T1 at 2 y V

(see Note C)

V

OL

+ V

DD

∆

V

OL

t

PZH

PHZ

Output

V

OH

Waveform 2 (V )

O

V

OH

− V

∆

0.5 V

DD

†

T1 at GND

(see Note C)

OL

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

†

T1 is an external terminal.

NOTES: A.

C includes probe and jig capacitance.

L

B. Output control applies to select (S0, S1) inputs.

C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

D. All input pulses are supplied by generators having the following characteristics: Z

E. The outputs are measured one at a time, with one transition per measurement.

= 50 Ω,rising and falling edge rate is 1 V/ns.

OS

F.

G.

t

and t

are the same as t

.

dis

PLZ

PZL

PHZ

PZH

are the same as t

.

en

Figure 1. Test Circuit and Voltage Waveforms

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇ ꢃꢃ ꢈꢈ

ꢈꢈꢉ ꢅ ꢊ ꢆ ꢈ ꢉꢋꢌ ꢉꢃ ꢌ ꢍ ꢆ ꢎꢇ ꢏꢆꢊ ꢐ ꢏ ꢍꢑ ꢍꢒ ꢓ ꢔꢍ ꢎꢇꢏꢆ ꢊꢐ ꢏꢍ ꢑꢍꢒ

ꢈ

ꢕ

ꢖ

ꢉ

ꢗ

ꢔ

ꢒ

ꢉ

ꢊ

ꢀ

ꢘ

ꢊ

ꢆ

ꢄ

ꢙ

ꢘ

ꢊ

ꢆꢙ

ꢄ

ꢙ

ꢚ

ꢒ

ꢛ

ꢍ

ꢐ

ꢇ

ꢎ

ꢐ

ꢚ

ꢁ

ꢔ

ꢐ

ꢒ

ꢍ

ꢄ

ꢙ

ꢚ

ꢒ

ꢛꢍ

ꢔ

ꢋ

ꢇ

ꢆ

ꢐ

ꢇ

ꢆ

ꢀ

SCDS192 − APRIL 2005

PARAMETER MEASUREMENT INFORMATION

(Skew and Propagation Delay Times)

V

DD

Z

O

= 40 Ω

V

IN

V

50 Ω

G1

G2

TEST CIRCUIT

DUT

V

DD

2 y V

†

Z

O

= 40 Ω

Z

O

= 40 Ω

T1

R

V

I

V

O

DD

L

GND

V

120 Ω

C

R

L

(see Note A)

†

T1

V

I

C

R

V

DD

TEST

L

t

1.8 V 0.1 V

V

DD

V

DD

V

DD

150 Ω

see Waveform

6 pF

pd

t

150 Ω

osk

t

esk

†

T1 is an external terminal.

V

REF

+0.35 V

Input

(H or D)

V

REF

−0.35 V

V

REF

+0.35 V

V

OH

50%

Input

(H or D)

Output 1

(D or H)

50%

V

REF

V

OL

−0.35 V

t

PLH

PHL

Skew

V

OH

V

OH

Output 2

(D or H)

50%

Output

(D or H)

OL

V

OL

SKEW BETWEEN ANY TWO OUTPUTS

(t ) (see Note B)

VOLTAGE WAVEFORMS

(t and t ) (see Note C)

osk

esk

pd

NOTES: A.

C

includes probe and jig capacitance.

is the difference in output voltage from channel to channel in a specific device.

L

B.

C.

t

osk

PLH

and t

are the same as t and t

= |t |

− t

PHL

pd esk

PLH PHL

D. All input pulses are supplied by generators having the following characteristics: Z

E. The outputs are measured one at a time, with one transition per measurement.

= 50 Ω,rising and falling edge rate is 1 V/ns.

OS

Figure 2. Test Circuit and Voltage Waveforms

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢃꢃ ꢈꢈ

ꢈꢈ ꢉꢅꢊ ꢆ ꢈ ꢉꢋ ꢌꢉ ꢃ ꢌ ꢍꢆ ꢎ ꢇꢏꢆ ꢊꢐ ꢏꢍ ꢑꢍꢒꢓ ꢔꢍꢎ ꢇꢏꢆꢊ ꢐ ꢏꢍ ꢑꢍ ꢒ

ꢈ ꢕ ꢖ ꢉꢗ ꢔꢔ ꢒꢉꢊ ꢊ ꢀ ꢘꢊ ꢆꢄ ꢙ ꢘ ꢊꢆ ꢙ ꢄꢙꢚ ꢒꢛ ꢍ ꢐꢇꢎ ꢐ ꢚꢁꢔ ꢐꢒꢍ ꢄꢙꢚꢒ ꢛꢍ ꢔ ꢋ ꢇꢆ ꢐ ꢇꢆꢀ

SCDS192 − APRIL 2005

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

13-Mar-2008

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SN74CBTU4411GSTR

SN74CBTU4411ZSTR

PREVIEW

ACTIVE

NFBGA

GST

72

2000

TBD

Call TI

ZST

Pb-Free

(RoHS)

SNAGCU

Level-3-260C-168 HR

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

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Applications

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Medical

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amplifier.ti.com

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interface.ti.com

logic.ti.com

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RF/IF and ZigBee® Solutions www.ti.com/lprf

www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	SN74CBTU4411
厂家：	TEXAS INSTRUMENTS
描述：	11-BIT 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER 1.8-V DDR-II SWITCH WITH CHARGE PUMP AND PRECHARGED OUTPUTS 11位1 -OF- 4的FET多路复用器/ 1.8 -V DDR-II与充电泵与预充电输出开关复用器开关输出元件双倍数据速率泵
文件：	总15页 (文件大小：386K)
中文：	中文翻译
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