SN74CBTR3244DGVR [TI]
CBT/FST/QS/5C/B SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDSO20, TVSOP-20;
| 型号： | SN74CBTR3244DGVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | CBT/FST/QS/5C/B SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDSO20, TVSOP-20 驱动 光电二极管 输出元件 电视 |
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SN74CBTR3244
OCTAL FET BUS SWITCH
SCDS079A – JULY 1998 – REVISED MAY 2000
DB, DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
Functionally Equivalent to QS3244
Standard ’244-Type Pinout
25-Ω Switch Connection Between Two
Ports
V
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
1OE
1A1
2B4
1A2
2B3
1A3
2B2
1A4
2B1
GND
CC
2OE
1B1
2A4
1B2
2A3
1B3
TTL-Compatible Input Levels
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB, DBQ), Thin Very Small-Outline (DGV),
and Thin Shrink Small-Outline (PW)
Packages
13 2A2
12 1B4
11 2A1
description
The SN74CBTR3244 provides eight bits of
high-speed TTL-compatible bus switching in a
standard ’244 device pinout. The low on-state
resistance of the switch allows connections to be
made with minimal propagation delay.
The device is organized as two 4-bit low-impedance switches with separate output-enable (OE) inputs. When
OE is low, the switch is on, and data can flow from port A to port B, or vice versa. When OE is high, the switch
is open, and a high-impedance state exists between the two ports.
The device has equivalent 25-Ω series resistors to reduce signal-reflection noise. This eliminates the need for
external terminating resistors.
The SN74CBTR3244 is characterized for operation from –40°C to 85 °C.
FUNCTION TABLE
(each 4-bit bus switch)
INPUT
FUNCTION
OE
L
A port = B port
Disconnect
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBTR3244
OCTAL FET BUS SWITCH
SCDS079A – JULY 1998 – REVISED MAY 2000
logic diagram (positive logic)
2
8
18
12
1A1
1A4
1B1
1B4
1
1OE
2A1
11
9
3
2B1
2B4
17
19
2A4
2OE
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
K
I/O
Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
MIN
4.5
2
MAX
UNIT
V
V
V
V
Supply voltage
5.5
CC
IH
IL
High-level control input voltage
Low-level control input voltage
Operating free-air temperature
V
0.8
70
V
T
A
0
°C
NOTE 3: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBTR3244
OCTAL FET BUS SWITCH
SCDS079A – JULY 1998 – REVISED MAY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
–1.2
±5
UNIT
V
V
IK
V
V
V
V
= 4.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
CC
CC
CC
CC
I
I
I
V = 5.5 V or GND
I
µA
µA
mA
pF
I
I
O
= 0,
V = V
I
or GND
50
CC
CC
‡
∆I
CC
Control inputs
Control inputs
One input at 3.4 V,
Other inputs at V
or GND
3.5
CC
C
C
V = 3 V or 0
I
i
V
= 3 V or 0,
= 4.5 V
OE = V
CC
pF
io(OFF)
O
I = 64 mA
I
V = 0
I
§
r
V
CC
I = 30 mA
I
Ω
on
V = 2.4 V,
I
I = 15 mA
I
†
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is determined
by the lowest voltage of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX
UNIT
¶
t
t
t
A or B
OE
B or A
A or B
A or B
ns
ns
ns
pd
en
OE
dis
¶
Thepropagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74CBTR3244
OCTAL FET BUS SWITCH
SCDS079A – JULY 1998 – REVISED MAY 2000
PARAMETER MEASUREMENT INFORMATION
7 V
Open
GND
TEST
S1
S1
500 Ω
t
Open
7 V
From Output
Under Test
pd
t
/t
PLZ PZL
t
/t
Open
C
= 50 pF
PHZ PZH
L
500 Ω
(see Note A)
3 V
0 V
Output
Control
(low-level
enabling)
1.5 V
1.5 V
LOAD CIRCUIT
t
PZL
t
PLZ
Output
Waveform 1
S1 at 7 V
3.5 V
3 V
0 V
1.5 V
1.5 V
1.5 V
Input
V
+ 0.3 V
OL
V
OL
(see Note B)
t
PHZ
t
PZH
t
t
PHL
PLH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
OH
V
OH
– 0.3 V
1.5 V
Output
1.5 V
1.5 V
0 V
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
andt
are the same as t
are the same as t
.
dis
en
PLZ
PZL
PLH
PHZ
PZH
PHL
.
are the same as t
.
pd
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
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Copyright 2000, Texas Instruments Incorporated
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