SN74CB3Q16811 [TI]
24-BIT SWITCH WITH PRECHARGED OUTPUTS 2.5-V/3.3-V LOW-VOLTAGE FET BUS SWITCH; 具有预充电输出2.5 V / 3.3 V低压FET总线开关24位开关![SN74CB3Q16811](http://pdffile.icpdf.com/pdf1/p00120/img/icpdf/SN74CB3Q16811DGGR_659123_icpdf.jpg)
型号: | SN74CB3Q16811 |
厂家: | ![]() |
描述: | 24-BIT SWITCH WITH PRECHARGED OUTPUTS 2.5-V/3.3-V LOW-VOLTAGE FET BUS SWITCH |
文件: | 总12页 (文件大小:174K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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SN74CB3Q16811
24-BIT SWITCH WITH PRECHARGED OUTPUTS
2.5-V/3.3-V LOW-VOLTAGE FET BUS SWITCH
www.ti.com
SCDS153B–OCTOBER 2003–REVISED MARCH 2005
FEATURES
•
Data and Control Inputs Provide Undershoot
Clamp Diodes
•
•
•
•
Member of the Texas Instruments Widebus™
Family
•
•
•
Low Power Consumption (ICC = 0.75 mA Typ)
VCC Operating Range From 2.3 V to 3.6 V
SN74CB3Q Bus Switches Are Equivalent to
IDTQS3VH Bus Switches
Data I/Os Support 0- to 5-V Signaling Levels
(0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
5-V Tolerant I/Os With Device Powered Up or
Powered Down
•
•
•
•
Control Inputs Can Be Driven by TTL or
5-V/3.3-V CMOS Outputs
Low and Flat ON-State Resistance (ron)
Characteristics Over Operating Range
(ron = 5 Ω Typ)
Ioff Supports Partial-Power-Down Mode
Operation
•
•
Rail-to-Rail Switching on Data I/O Ports
– 0- to 5-V Switching With 3.3-V VCC
– 0- to 3.3-V Switching With 2.5-V VCC
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
B-Port Outputs Are Precharged by Bias
Voltage (BIASV) to Minimize Signal Distortion
During Live Insertion and Hot Plugging
– 2000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
•
•
Supports PCI Hot Plug
•
Supports Both Digital and Analog
Applications: PCI Hot Plug, Hot Docking,
Memory Interleaving, Bus Isolation, and
Low-Distortion Signal Gating
Bidirectional Data Flow With Near-Zero
Propagation Delay
•
Low Input/Output Capacitance Minimizes
Loading and Signal Distortion
(Cio(OFF) = 4 pF Typ)
•
Fast Switching Frequency (fON = 20 MHz Max)
DESCRIPTION/ORDERING INFORMATION
The SN74CB3Q16811 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of
the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows
for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device
also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus.
Specifically designed to support high-bandwidth applications, the SN74CB3Q16811 provides an optimized
interface solution ideally suited for broadband communications, networking, and data-intensive computing
systems.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
SN74CB3Q16811DL
TOP-SIDE MARKING
CB3Q16811
Tube
SSOP – DL
Tape and reel
Tape and reel
Tape and reel
SN74CB3Q16811DLR
–40°C to 85°C
TSSOP – DGG
TVSOP – DGV
SN74CB3Q16811DGGR
SN74CB3Q16811DGVR
CB3Q16811
BW811
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The SN74CB3Q16811 is organized as two 12-bit bus switches with separate output-enable (1OE, 2OE) inputs. It
can be used as two 12-bit bus switches or as one 24-bit bus switch. When OE is low, the associated 12-bit bus
switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE
is high, the associated 12-bit bus switch is OFF, and a high-impedance state exists between the A and B ports.
The B port is precharged to bias voltage (BIASV) through the equivalent of a 10-kΩ resistor when OE is high or if
the device is powered down (VCC = 0 V).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74CB3Q16811
24-BIT SWITCH WITH PRECHARGED OUTPUTS
2.5-V/3.3-V LOW-VOLTAGE FET BUS SWITCH
www.ti.com
SCDS153B–OCTOBER 2003–REVISED MARCH 2005
During insertion (or removal) of a card into (or from) an active bus, the card's output voltage may be close to
GND. When the connector pins make contact, the card's parasitic capacitance tries to force the bus signal to
GND, creating a possible glitch on the active bus. This glitching effect can be reduced by using a bus switch with
precharged bias voltage (BIASV) of the bus switch equal to the input threshold voltage level of the receivers on
the active bus. This method ensures that any glitch produced by insertion (or removal) of the card does not cross
the input threshold region of the receivers on the active bus, minimizing the effects of live-insertion noise.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging
current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
BIASV
1A1
1OE
2OE
1B1
1B2
1B3
1B4
1B5
GND
1B6
1B7
1B8
1B9
1B10
1B11
1B12
2B1
2B2
2B3
GND
2B4
2B5
2B6
2B7
2B8
2B9
2B10
2B11
2B12
2
3
1A2
1A3
1A4
1A5
4
5
6
7
1A6
8
GND
1A7
1A8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1A9
1A10
1A11
1A12
2A1
2A2
V
CC
2A3
GND
2A4
2A5
2A6
2A7
2A8
2A9
2A10
2A11
2A12
Table 1. FUNCTION TABLE
(EACH 12-BIT BUS SWITCH)
INPUT
OE
INPUT/OUTPUT
FUNCTION
A
L
B
A port = B port
Disconnect
B port = BIASV
H
Z
2
SN74CB3Q16811
24-BIT SWITCH WITH PRECHARGED OUTPUTS
2.5-V/3.3-V LOW-VOLTAGE FET BUS SWITCH
www.ti.com
SCDS153B–OCTOBER 2003–REVISED MARCH 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
1
BIASV
1B1
2
54
1A1
SW
SW
14
56
42
1A12
1OE
1B12
15
41
29
2A1
SW
SW
2B1
28
55
2A12
2OE
2B12
3
SN74CB3Q16811
24-BIT SWITCH WITH PRECHARGED OUTPUTS
2.5-V/3.3-V LOW-VOLTAGE FET BUS SWITCH
www.ti.com
SCDS153B–OCTOBER 2003–REVISED MARCH 2005
SIMPLIFIED SCHEMATIC, EACH FET SWITCH (SW)
BIASV
A
B
V
CC
Charge
Pump
(1)
EN
(1) EN is the internal enable signal applied to the switch.
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
–0.5
MAX
4.6
UNIT
VCC
Supply voltage range
V
BIASV BIAS supply voltage range
7
7
V
VIN
VI/O
IIK
Control input voltage range(2)(3)
Switch I/O voltage range(2)(3)(4)
Control input clamp current
I/O port clamp current
V
7
V
VIN < 0
VI/O < 0
–50
–50
±64
±100
64
mA
mA
mA
mA
II/OK
II/O
ON-state switch current(5)
Continuous current through VCC or GND
DGG package
DGV package
DL package
θJA
Package thermal impedance(6)
48
°C/W
56
Tstg
Storage temperature range
–65
150
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground, unless otherwise specified.
(3) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(4) VI and VO are used to denote specific conditions for VI/O
(5) II and IO are used to denote specific conditions for II/O
(6) The package thermal impedance is calculated in accordance with JESD 51-7.
.
.
4
SN74CB3Q16811
24-BIT SWITCH WITH PRECHARGED OUTPUTS
2.5-V/3.3-V LOW-VOLTAGE FET BUS SWITCH
www.ti.com
SCDS153B–OCTOBER 2003–REVISED MARCH 2005
Recommended Operating Conditions(1)
MIN MAX UNIT
VCC
Supply voltage
Bias voltage
2.3
0
3.6
5
V
V
BIASV
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
1.7
2
5.5
5.5
0.7
0.8
5.5
85
VIH
VIL
High-level control input voltage
Low-level control input voltage
V
V
0
0
VI/O
TA
Data input/output voltage
0
V
Operating free-air temperature
–40
°C
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Electrical Characteristics(1)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
II = –18 mA
MIN TYP(2)
MAX UNIT
VIK
IIN
VCC = 3.6 V,
Control inputs VCC = 3.6 V,
–1.8
±1
V
VIN = 0 to 5.5 V
µA
BIASV = 2.4 V,
VO = 0,
Switch OFF,
VIN = VCC or GND
IO
B port
VCC = 3.V,
0.2
mA
VO = 0 to 5.5 V,
VI = 0,
Switch OFF,
VIN = VCC or GND
(3)
IOZ
Ioff
VCC = 3.6 V,
VCC = 0,
±1
1
µA
µA
mA
µA
VO = 0 to 5.5 V,
VI = 0
II/O = 0,
Switch ON or OFF,
ICC
VCC = 3.6 V,
VIN = VCC or GND
Other inputs at VCC or GND
1
3
(4)
(5)
∆ICC
ICCD
Cin
Control inputs VCC = 3.6 V,
One input at 3 V,
30
0.45
5
Per control
VCC = 3.6 V,
input
A and B ports open,
Control input switching at 50% duty cycle
mA/
MHz
0.38
3.5
4
Control inputs VCC = 3.3 V,
VIN = 5.5 V, 3.3 V, or 0
pF
Switch OFF,
VIN = VCC or GND,
Cio(OFF)
Cio(ON)
A port
VCC = 3.3 V,
VCC = 3.3 V,
VI/O = 5.5 V, 3.3 V, or 0
5
pF
Switch ON,
VIN = VCC or GND,
VI/O = 5.5 V, 3.3 V, or 0
10
12.5
pF
VI = 0,
IO = 30 mA
IO = –15 mA
IO = 30 mA
IO = –15 mA
5
5
5
5
8
9
VCC = 2.3 V,
TYP at VCC = 2.5 V
VI = 1.7 V,
VI = 0,
(6)
ron
Ω
6.5
8
VCC = 3 V
VI = 2.4 V,
(1) VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
(2) All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
(3) For I/O ports, the parameter IOZ includes the input leakage current.
(4) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
(5) This parameter specifies the dynamic power-supply current associated with the operating frequency of a single control input (see
Figure 2).
(6) Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is
determined by the lower of the voltages of the two (A or B) terminals.
5
SN74CB3Q16811
24-BIT SWITCH WITH PRECHARGED OUTPUTS
2.5-V/3.3-V LOW-VOLTAGE FET BUS SWITCH
www.ti.com
SCDS153B–OCTOBER 2003–REVISED MARCH 2005
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
FROM
(INPUT)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
MAX
(1)
fOE
OE
A or B
B or A
10
0.09
8
20
0.15
8
MHz
ns
(2)
tpd
A or B
tPZH
tPZL
tPHZ
tPLZ
BIASV = GND
BIASV = 3 V
BIASV = GND
BIASV = 3 V
1.5
1.5
1
1.5
1.5
1
A or B
A or B
ns
ns
OE
8
8
7.5
7.5
7.5
7.5
OE
1
1
(1) Maximum switching frequency for control input (VO > VCC, VI = 5 V, RL ≥ 1 MΩ, CL = 0)
(2) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
16
V
= 3.3 V
= 25°C
= -15 mA
CC
14
12
10
8
T
A
I
O
6
4
2
0
0
0.5
1
1.5
2
2.5
V - V
3
3.5
4
4.5
5
I
Figure 1. Typical ron vs VI
30
V
CC
= 3.3 V
T
= 25°C
A
25
20
15
A and B Ports Open
One OE Switching
10
5
0
0
5
10
15
20
25
OE Switching Frequency - MHz
Figure 2. Typical ICC vs OE Switching Frequency
6
SN74CB3Q16811
24-BIT SWITCH WITH PRECHARGED OUTPUTS
2.5-V/3.3-V LOW-VOLTAGE FET BUS SWITCH
www.ti.com
SCDS153B–OCTOBER 2003–REVISED MARCH 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
Input Generator
V
IN
50 Ω
50 Ω
V
G1
TEST CIRCUIT
DUT
2 × V
CC
Input Generator
S1
Open
GND
R
L
V
I
V
O
50 Ω
50 Ω
V
G2
C
L
R
L
(see Note A)
S1
V
I
C
L
V
∆
R
L
V
CC
TEST
2.5 V ± 0.2 V
3.3 V ± 0.3 V
Open
Open
500 Ω
500 Ω
V
V
or GND
or GND
30 pF
50 pF
CC
t
pd(s)
CC
2.5 V ± 0.2 V
3.3 V ± 0.3 V
2 × V
2 × V
500 Ω
500 Ω
GND
GND
30 pF
50 pF
0.15 V
0.3 V
CC
t
/t
PLZ PZL
CC
2.5 V ± 0.2 V
3.3 V ± 0.3 V
GND
GND
500 Ω
500 Ω
V
V
30 pF
50 pF
0.15 V
0.3 V
CC
t
/t
PHZ PZH
CC
Output
Control
(V
V
CC
V /2
CC
V /2
CC
)
IN
0 V
t
t
PLZ
PZL
Output
Waveform 1
V
V
CC
Output
Control
(V
V
CC
V /2
CC
S1 at 2 × V
V + V
∆
OL
V /2
CC
V /2
CC
CC
)
(see Note B)
IN
OL
0 V
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
- V
∆
V /2
CC
Output
V /2
CC
V /2
CC
0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (t
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
)
pd(s)
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
PZH
PHL
are the same as t
en
are the same as t
. The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance
pd(s)
of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Test Circuit and Voltage Waveforms
7
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
74CB3Q16811DGGRE4
74CB3Q16811DGVRE4
74CB3Q16811DLRG4
SN74CB3Q16811DGGR
SN74CB3Q16811DGVR
SN74CB3Q16811DL
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
56
56
56
56
56
56
56
56
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TVSOP
SSOP
TSSOP
TVSOP
SSOP
SSOP
SSOP
DGV
DL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DGG
DGV
DL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74CB3Q16811DLG4
SN74CB3Q16811DLR
DL
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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