SN74AXC4T245-Q1_V04 [TI]
SN74AXC4T245-Q1 Automotive 4-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation and Tri-State Outputs;型号: | SN74AXC4T245-Q1_V04 |
厂家: | TEXAS INSTRUMENTS |
描述: | SN74AXC4T245-Q1 Automotive 4-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation and Tri-State Outputs |
文件: | 总44页 (文件大小:3028K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SN74AXC4T245-Q1
SCES905E – JULY 2019 – REVISED DECEMBER 2021
SN74AXC4T245-Q1 Automotive 4-Bit Dual-Supply Bus Transceiver With Configurable
Voltage Translation and Tri-State Outputs
The SN74AXC4T245-Q1 device is designed for
asynchronous communication between data buses.
1 Features
•
•
•
AEC-Q100 qualified for automotive applications
Available in wettable flank QFN (WBQB) package
Fully-configurable dual-rail design allows each port
to operate with a power supply range from 0.65 V
to 3.6 V
Operating temperature from –40°C to +125°C
Multiple direction control pins to allow
simultaneous up and down translation
Glitch-free power supply sequencing
Up to 380 Mbps support when translating from 1.8
V to 3.3 V
The device transmits data from the A bus to the B bus
or from the B bus to the A bus, depending on the logic
level of the direction-control inputs (1DIR and 2DIR).
The output-enable inputs (1 OE and 2 OE) are used
to disable the outputs so the buses are effectively
isolated. The SN74AXC4T245-Q1 device is designed
so the control pins (xDIR and x OE) are referenced to
•
•
VCCA
.
•
•
To ensure the high-impedance state of the level shifter
I/Os during power up or power down, the x OE pins
should be tied to VCCA through a pull-up resistor.
•
VCC isolation feature:
This device is fully specified for partial-power-down
applications using the Ioff current. The Ioff protection
circuitry ensures that no excessive current is drawn
from or to an input, output, or combined I/O that
is biased to a specific voltage while the device is
powered down.
– If either VCC input is below 100 mV, all
I/O outputs are disabled and become high
impedance
Ioff supports partial-power-down mode operation
Compatible with AVC-family level shifters
Latch-up performance exceeds 100 mA per JESD
78, class II
ESD protection exceeds JEDEC JS-001
– 8000-V human-body model
– 1000-V charged-device model
•
•
•
The VCC isolation feature ensures that if either VCCA
or VCCB is less than 100 mV, both I/O ports enter a
high-impedance state by disabling their outputs.
•
Glitch-Free power supply sequencing allows either
supply rail to be powered on or off in any order while
providing robust power sequencing performance.
2 Applications
•
•
•
•
Infotainment head unit
ADAS fusion
ADAS front camera
Hybrid electric vehicles and electric vehicles
battery management system
Telematics control unit
Device Information
PART NUMBER
SN74AXC4T245PW-Q1
SN74AXC4T245BQB-Q1
PACKAGE(1) BODY SIZE (NOM)
TSSOP (16)
WQFN (16)
5.00 mm × 4.40 mm
2.50 mm × 3.50 mm
2.50 mm × 3.50 mm
2.60 mm × 1.80 mm
•
SN74AXC4T245WBQB-Q1 WQFN (16)
SN74AXC4T245RSV-Q1 UQFN (16)
3 Description
The SN74AXC4T245-Q1 AEC-Q100 qualified device
is a four-bit non-inverting bus transceiver that uses
two individually configurable power-supply rails. The
device is operational with both VCCA and VCCB
supplies as low as 0.65 V. The A port is designed
to track VCCA, which accepts any supply voltage from
0.65 V to 3.6 V. The B port is designed to track
VCCB, which also accepts any supply voltage from
0.65 V to 3.6 V. Additionally the SN74AXC4T245-Q1
is compatible with a single-supply system.
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
One of Two Transceiver Pairs
VCCA
VCCB
xDIR
xOE
xB1
xB2
xA1
xA2
Functional Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74AXC4T245-Q1
SCES905E – JULY 2019 – REVISED DECEMBER 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics, VCCA = 0.7 V ± 0.05 V.......7
6.7 Switching Characteristics, VCCA = 0.8 V ± 0.04 V.......8
6.8 Switching Characteristics, VCCA = 0.9 V ± 0.045 V.....9
6.9 Switching Characteristics, VCCA = 1.2 V ± 0.1 V.......10
6.10 Switching Characteristics, VCCA = 1.5 V ± 0.1 V..... 11
6.11 Switching Characteristics, VCCA = 1.8 V ± 0.15 V... 12
6.12 Switching Characteristics, VCCA = 2.5 V ± 0.2 V.....13
6.13 Switching Characteristics, VCCA = 3.3 V ± 0.3 V.....14
6.14 Operating Characteristics: TA = 25°C..................... 15
6.15 Typical Characteristics............................................17
7 Parameter Measurement Information..........................18
7.1 Load Circuit and Voltage Waveforms........................18
8 Detailed Description......................................................20
8.1 Overview...................................................................20
8.2 Functional Block Diagram.........................................20
8.3 Feature Description...................................................20
8.4 Device Functional Modes..........................................22
9 Application and Implementation..................................23
9.1 Application Information............................................. 23
9.2 Typical Application.................................................... 23
10 Power Supply Recommendations..............................25
11 Layout...........................................................................25
11.1 Layout Guidelines................................................... 25
11.2 Layout Example...................................................... 25
12 Device and Documentation Support..........................26
12.1 Documentation Support.......................................... 26
12.2 Receiving Notification of Documentation Updates..26
12.3 Support Resources................................................. 26
12.4 Trademarks.............................................................26
12.5 Electrostatic Discharge Caution..............................26
12.6 Glossary..................................................................26
13 Mechanical, Packaging, and Orderable
Information.................................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (September 2021) to Revision E (December 2021)
Page
•
Changed the status of the WBQB package from: Product Preview to: Production ........................................... 1
Changes from Revision C (March 2021) to Revision D (September 2021)
Page
•
Added BQB (WQFN) package for APL...............................................................................................................1
Changes from Revision B (July 2020) to Revision C (March 2021)
Page
•
Changed the status fo the BQB (WQFN) package option from preview to production ......................................1
Changes from Revision A (December 2019) to Revision B (July 2020)
Page
•
•
Updated the numbering format for tables, figures and cross-references throughout the document...................1
Added BQB (WQFN) package option to Device Information table .................................................................... 1
Changes from Revision * (July 2019) to Revision A (December 2019)
Page
•
Changed from Advance Information to Production Data ................................................................................... 1
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5 Pin Configuration and Functions
VCCA
1DIR
2DIR
1A1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCCB
1OE
2OE
1B1
1B2
2B1
2B2
GND
2
3
4
5
6
7
1DIR
2DIR
1A1
1A2
2A1
2A2
1OE
2OE
15
14
13 1B1
12 1B2
11 2B1
10 2B2
Thermal
Pad
1A2
2A1
2A2
GND
Figure 5-1. PW Package 16-Pin TSSOP Top View
Figure 5-2. BQB/WBQB Package 16-Pin WQFN
Transparent Top View
16 15 14 13
1
2
3
4
12
2B2
1OE
VCCB
11
GND
10
VCCA
GND
9
2A2
1DIR
5
6
7
8
Figure 5-3. RSV Package 16-Pin UQFN Transparent Top View
Table 5-1. Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
PW
4
RSV
6
BQB
4
1A1
1A2
1B1
1B2
1DIR
I/O
I/O
I/O
I/O
I
Input/output 1A1. Referenced to VCCA
5
7
5
Input/output 1A2. Referenced to VCCA
13
12
2
15
14
4
13
12
2
Input/output 1B1. Referenced to VCCB
Input/output 1B2. Referenced to VCCB
Direction-control input for ‘1’ ports. Referenced to VCCA
Tri-state output-mode enable. Pull OE high to place ‘1’ outputs in
tri-state mode. Referenced to VCCA
1 OE
15
1
15
I
2A1
2A2
2B1
2B2
2DIR
6
7
8
9
6
7
I/O
I/O
I/O
I/O
I
Input/output 2A1. Referenced to VCCA
Input/output 2A2. Referenced to VCCA
Input/output 2B1. Referenced to VCCB
Input/output 2B2. Referenced to VCCB
Direction-control input for ‘2’ ports. Referenced to VCCA
11
10
3
13
12
5
11
10
3
Tri-state output-mode enable. Pull OE high to place ‘2’ outputs in
tri-state mode. Referenced to VCCA
2 OE
14
16
14
I
GND
VCCA
VCCB
8, 9
1
10, 11
8, 9
1
—
—
—
Ground
3
2
A-port power supply voltage. 0.65 V ≤ VCCA ≤ 3.6 V
B-port power supply voltage. 0.65 V ≤ VCCB ≤ 3.6 V
16
16
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
MAX UNIT
VCCA Supply voltage A
VCCB Supply voltage B
4.2
4.2
4.2
4.2
4.2
4.2
4.2
V
V
I/O Ports (A Port)
I/O Ports (B Port)
Control Inputs
A Port
VI
Input Voltage(2)
V
VO
VO
Voltage applied to any output in the high-impedance or power-off state(2)
Voltage applied to any output in the high or low state(2) (3)
V
V
B Port
A Port
–0.5 VCCA + 0.2
–0.5 VCCB + 0.2
–50
B Port
IIK
IOK
IO
Input clamp current
VI < 0
mA
mA
Output clamp current
VO < 0
–50
Continuous output current
Continuous current through VCC or GND
Junction Temperature
–50
50 mA
100 mA
150 °C
150 °C
–100
Tj
Tstg
Storage temperature
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The output positive-voltage rating may be exceeded up to 4.2 V maximum if the output current rating is observed.
6.2 ESD Ratings
VALUE
±8000
±1000
UNIT
Human body model (HBM), per AEC Q100-002(1)
Charged device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
0.65
MAX UNIT
VCCA
VCCB
Supply voltage A
Supply voltage B
3.6
3.6
V
V
0.65
VCCI = 0.65 V - 0.75 V
VCCI = 0.76 V - 1 V
VCCI = 1.1 V - 1.95 V
VCCI = 2.3 V - 2.7 V
VCCI = 3 V - 3.6 V
VCCI x 0.70
VCCI x 0.70
VCCI x 0.65
1.6
Data Inputs
2
VIH
High-level input voltage
V
VCCA = 0.65 V - 0.75 V
VCCA = 0.76 V - 1 V
VCCA = 1.1 V - 1.95 V
VCCA = 2.3 V - 2.7 V
VCCA = 3 V - 3.6 V
VCCI = 0.65 V - 0.75 V
VCCI = 0.76 V - 1 V
VCCI = 1.1 V - 1.95 V
VCCI = 2.3 V - 2.7 V
VCCI = 3 V - 3.6 V
VCCA x 0.70
VCCA x 0.70
VCCA x 0.65
1.6
Control Inputs(xDIR, x OE)
Referenced to VCCA
2
VCCI x 0.30
VCCI x 0.30
VCCI x 0.35
0.7
Data Inputs
0.8
VIL
Low-level input voltage
V
VCCA = 0.65 V - 0.75 V
VCCA = 0.76 V - 1 V
VCCA = 1.1 V - 1.95 V
VCCA = 2.3 V - 2.7 V
VCCA = 3 V - 3.6 V
VCCA x 0.30
VCCA x 0.30
VCCA x 0.35
0.7
Control Inputs(xDIR, x OE)
Referenced to VCCA
0.8
VI
Input voltage (2)
Output voltage
0
0
0
3.6
V
V
Active State
Tri-State
VCCO
VO
3.6
Δt/Δv(2) Input transition rate
10 ns/V
125 °C
TA Operating free-air temperature
–40
(1) VCCI is the VCC associated with the input port. VCCO is the VCC associated with the output port.
(2) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs.
6.4 Thermal Information
SN74AXC4T245-Q1
BQB
(WQFN)
WBQB
(WQFN)
THERMAL METRIC(1)
PW (TSSOP) RSV (UQFN)
UNIT
16 PINS
126.9
49.3
74.3
8.1
16 PINS
130.1
70.3
57.4
4.6
16 PINS
73.0
35.1
42.8
4.6
16 PINS
72.9
69.6
41.9
4.6
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
73.4
NA
55.8
NA
42.8
10.2
41.9
19.9
RθJC(bottom)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted) (1) (2)
Operating free-air temperature (TA)
PARAMETER
TEST CONDITIONS
VCCA
VCCB
–40°C to 85°C
MIN TYP(4)
–40°C to 125°C
MIN TYP(4)
UNIT
MAX
MAX
VCCO
–
VCCO
–
IOH = –100 µA
0.7 V - 3.6 V
0.7 V - 3.6 V
0.1
0.1
IOH = –50 µA
IOH = –200 µA
IOH = –500 µA
0.65 V
0.76 V
0.85 V
1.1 V
0.65 V
0.76 V
0.85 V
1.1 V
0.55
0.58
0.65
0.85
1.05
1.2
0.55
0.58
0.65
0.85
1.05
1.2
High-level output
voltage
VOH
VI = VIH
V
IOH = –3 mA
IOH = –6 mA
IOH = –8 mA
IOH = –9 mA
IOH = –12 mA
IOL = 100 µA
IOL = 50 µA
IOL = 200 µA
IOL = 500 µA
IOL = 3 mA
1.4 V
1.4 V
1.65 V
2.3 V
1.65 V
2.3 V
1.75
2.3
1.75
2.3
3 V
3 V
0.7 V - 3.6 V
0.65 V
0.76 V
0.85 V
1.1 V
0.7 V - 3.6 V
0.65 V
0.76 V
0.85 V
1.1 V
0.1
0.1
0.1
0.1
0.18
0.2
0.18
0.2
Low-level output
voltage
VOL
VI = VIL
0.25
0.35
0.45
0.55
0.7
0.25
0.35
0.45
0.55
0.7
V
IOL = 6 mA
1.4 V
1.4 V
IOL = 8 mA
1.65 V
2.3 V
1.65 V
2.3 V
IOL = 9 mA
IOL = 12 mA
3 V
3 V
Control inputs (xDIR, x OE): VI
= VCCA or GND
0.65 V- 3.6 V
0.65 V- 3.6 V
0.65 V- 3.6 V
0.65 V- 3.6 V
–0.5
–4
0.5
4
–1
–8
1
8
µA
µA
Input leakage
current
II
Data Inputs (xAx, xBx)
VI = VCCI or GND
0 V
0 V - 3.6 V
0 V
–4
–4
4
4
–8
–8
8
8
Partial power
down current
A or B Port
VI or VO = 0 V - 3.6 V
Ioff
µA
µA
0 V - 3.6 V
A or B Port
Tri-state output
current (3)
IOZ
VI = VCCI or GND, VO = VCCO 3.6 V
or GND, OE = VIH
3.6 V
–4
–2
4
–8
8
0.65 V- 3.6 V
0.65 V- 3.6 V
3.6 V
13
26
VCCA supply
current
VI = VCCI
or GND
ICCA
IO = 0
0 V
–12
µA
µA
3.6 V
0 V
8
13
8
16
26
16
0.65 V- 3.6 V
0 V
0.65 V- 3.6 V
3.6 V
VCCB supply
current
VI = VCCI
or GND
ICCB
IO = 0
IO = 0
3.6 V
0 V
–2
–12
ICCA
ICCB
+
Combined
supply current
VI = VCCI
or GND
0.65 V- 3.6 V
3.3 V
0.65 V- 3.6 V
3.3 V
20
40
µA
pF
pF
Control input
capacitance
Ci
VI = 3.3 V or GND
4.5
6.6
4.5
6.6
Data I/O
capacitance
OE = VCCA, VO = 1.65V DC +1
MHz -16 dBm sine wave
Cio
3.3 V
3.3 V
(1) VCCI is the VCC associated with the input port.
(2) VCCO is the VCC associated with the output port.
(3) For I/O ports, the parameter IOZ includes the input leakage current.
(4) All typical data is taken at 25°C.
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6.6 Switching Characteristics, VCCA = 0.7 V ± 0.05 V
See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms.
B-Port Supply Voltage (VCCB
)
PARAMETER
FROM
TO
Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V
MIN MAX MIN MAX MIN MAX MIN MAX
1.5 ± 0.1 V
MIN MAX
1.8 ± 0.15 V
MIN MAX
2.5 ± 0.2 V
MIN MAX
3.3 ± 0.3 V
MIN MAX
UNIT
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
155
155
156
156
156
156
154
154
238
238
286
286
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
108
108
128
128
156
156
121
121
238
238
194
194
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
76
76
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
40
40
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
37
37
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
40
40
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
67
67
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
185
185
10
A
B
B
A
A
B
A
B
Propagation
delay
tpd
ns
106
106
156
156
101
101
238
238
146
146
55
21
15
11
55
21
15
11
10
156
156
55
156
156
54
156
156
56
156
156
65
156
156
125
125
238
238
146
146
OE
OE
OE
OE
tdis Disable time
ns
ns
55
54
56
65
238
238
94
238
238
76
238
238
70
238
238
69
ten Enable time
94
76
70
69
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6.7 Switching Characteristics, VCCA = 0.8 V ± 0.04 V
See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms.
B-Port Supply Voltage (VCCB
)
PARAMETER
FROM
TO
Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V
MIN MAX MIN MAX MIN MAX MIN MAX
1.5 ± 0.1 V
MIN MAX
1.8 ± 0.15 V
MIN MAX
2.5 ± 0.2 V
MIN MAX
3.3 ± 0.3 V
MIN MAX
UNIT
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
128
128
108
108
103
103
143
143
143
143
243
243
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
88
88
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
63
63
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
29
29
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
24
24
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
23
23
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
24
24
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
34
34
A
B
B
A
A
B
A
B
Propagation
delay
tpd
ns
88
70
38
21
15
11
10
88
70
38
21
15
11
10
103
103
110
110
143
143
172
172
103
103
90
103
103
42
103
103
36
103
103
36
103
103
37
103
103
47
OE
OE
OE
OE
tdis Disable time
ns
ns
90
42
36
36
37
47
143
143
129
129
143
143
79
143
143
60
143
143
54
143
143
48
143
143
53
ten Enable time
79
60
54
48
53
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6.8 Switching Characteristics, VCCA = 0.9 V ± 0.045 V
See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms.
B-Port Supply Voltage (VCCB
)
PARAMETER
FROM
TO
Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V
MIN MAX MIN MAX MIN MAX MIN MAX
1.5 ± 0.1 V
MIN MAX
1.8 ± 0.15 V
MIN MAX
2.5 ± 0.2 V
MIN MAX
3.3 ± 0.3 V
MIN MAX
UNIT
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
106
106
76
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
70
70
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
53
53
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
24
24
27
27
81
81
37
37
95
95
71
71
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
18
18
18
18
81
81
30
30
95
95
52
52
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
17
17
13
13
81
81
28
28
95
95
46
46
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
16
16
10
10
81
81
26
26
95
95
39
39
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
19
19
9
A
B
B
A
A
B
A
B
Propagation
delay
tpd
ns
63
53
76
63
53
9
81
81
81
81
81
30
30
95
95
39
39
OE
OE
OE
OE
81
81
81
tdis Disable time
ns
ns
138
138
95
105
105
95
84
84
95
95
95
95
ten Enable time
222
222
148
148
116
116
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6.9 Switching Characteristics, VCCA = 1.2 V ± 0.1 V
See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms.
B-Port Supply Voltage (VCCB
)
PARAMETER
FROM
TO
Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V
MIN MAX MIN MAX MIN MAX MIN MAX
1.5 ± 0.1 V
MIN MAX
1.8 ± 0.15 V
MIN MAX
2.5 ± 0.2 V
MIN MAX
3.3 ± 0.3 V
MIN MAX
UNIT
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
55
55
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
37
37
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
27
27
24
24
30
30
79
79
45
45
79
79
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
15
15
15
15
30
30
31
31
45
45
58
58
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
11
11
10
10
30
30
24
24
45
45
41
41
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
10
10
9
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
8
8
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
9
9
A
B
B
A
A
B
A
B
Propagation
delay
tpd
ns
41
29
7
6
41
29
9
7
6
30
30
30
30
21
21
45
45
35
35
30
30
18
18
45
45
27
27
30
30
18
18
45
45
24
24
OE
OE
OE
OE
30
30
tdis Disable time
ns
ns
132
132
45
99
99
45
45
45
ten Enable time
164
164
108
108
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6.10 Switching Characteristics, VCCA = 1.5 V ± 0.1 V
See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms.
B-Port Supply Voltage (VCCB
)
PARAMETER
FROM
TO
Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V
MIN MAX MIN MAX MIN MAX MIN MAX
1.5 ± 0.1 V
MIN MAX
1.8 ± 0.15 V
MIN MAX
2.5 ± 0.2 V
MIN MAX
3.3 ± 0.3 V
MIN MAX
UNIT
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
21
21
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
21
21
24
24
21
21
97
97
26
26
84
84
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
18
18
18
18
21
21
77
77
26
26
68
68
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
11
11
11
11
21
21
29
29
26
26
47
47
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
9
9
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
8
8
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
7
7
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
6
6
A
B
B
A
A
B
A
B
Propagation
delay
tpd
ns
37
9
8
5
5
37
9
8
5
5
21
21
21
21
21
26
26
35
35
21
21
19
19
26
26
29
29
21
21
15
15
26
26
22
22
21
21
15
15
26
26
20
20
OE
OE
OE
OE
21
tdis Disable time
ns
ns
131
131
26
26
ten Enable time
109
109
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6.11 Switching Characteristics, VCCA = 1.8 V ± 0.15 V
See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms.
B-Port Supply Voltage (VCCB
)
PARAMETER
FROM
TO
Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V
MIN MAX MIN MAX MIN MAX MIN MAX
1.5 ± 0.1 V
MIN MAX
1.8 ± 0.15 V
MIN MAX
2.5 ± 0.2 V
MIN MAX
3.3 ± 0.3 V
MIN MAX
UNIT
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
15
15
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
15
15
23
23
18
18
96
96
20
20
75
75
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
13
13
17
17
18
18
76
76
20
20
62
62
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
9
9
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
8
8
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
7
7
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
6
6
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
6
6
A
B
B
A
A
B
A
B
Propagation
delay
tpd
ns
40
10
10
18
18
28
28
20
20
41
41
8
7
5
4
40
8
7
5
4
18
18
18
21
21
20
20
32
32
18
18
18
18
20
20
27
27
18
18
15
15
20
20
20
20
18
18
14
14
20
20
18
18
OE
OE
OE
OE
18
tdis Disable time
ns
ns
130
130
20
20
ten Enable time
102
102
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6.12 Switching Characteristics, VCCA = 2.5 V ± 0.2 V
See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms.
B-Port Supply Voltage (VCCB
)
PARAMETER
FROM
TO
Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V
MIN MAX MIN MAX MIN MAX MIN MAX
1.5 ± 0.1 V
MIN MAX
1.8 ± 0.15 V
MIN MAX
2.5 ± 0.2 V
MIN MAX
3.3 ± 0.3 V
MIN MAX
UNIT
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
11
11
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
11
11
24
24
13
13
95
95
13
13
70
70
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
10
11
16
16
13
13
76
76
13
13
56
56
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
7
7
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
5
5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
5
5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
5
5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
5
5
A
B
B
A
A
B
A
B
Propagation
delay
tpd
ns
67
8
7
6
5
4
67
8
7
6
5
4
13
13
13
27
27
13
13
36
36
13
13
20
20
13
13
26
26
13
13
17
17
13
13
22
22
13
13
13
13
13
13
18
18
13
13
13
13
13
13
16
16
OE
OE
OE
OE
13
tdis Disable time
ns
ns
128
128
13
13
ten Enable time
120
120
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6.13 Switching Characteristics, VCCA = 3.3 V ± 0.3 V
See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms.
B-Port Supply Voltage (VCCB
)
PARAMETER
FROM
TO
Test Conditions 0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V
MIN MAX MIN MAX MIN MAX MIN MAX
1.5 ± 0.1 V
MIN MAX
1.8 ± 0.15 V
MIN MAX
2.5 ± 0.2 V
MIN MAX
3.3 ± 0.3 V
MIN MAX
UNIT
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
10
10
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
10
10
34
34
12
12
95
95
11
11
82
82
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
9
9
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
6
6
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
5
5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
4
4
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
4
4
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
4
4
A
B
B
A
A
B
A
B
Propagation
delay
tpd
ns
185
185
12
19
19
12
12
75
75
11
11
59
59
9
6
6
5
4
9
6
6
5
4
12
12
27
27
11
11
35
35
12
12
19
19
11
11
24
24
12
12
17
17
11
11
20
20
12
12
13
13
11
11
16
16
12
12
12
12
11
11
14
14
OE
OE
OE
OE
12
tdis Disable time
ns
ns
141
141
11
11
ten Enable time
189
189
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6.14 Operating Characteristics: TA = 25°C
PARAMETER
TEST CONDITIONS
VCCA
0.7 V
VCCB
0.7 V
MIN
TYP
2.2
MAX UNIT
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.7 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.7 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.7 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.7 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.7 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.7 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
2.1
2.1
Power Dissipation Capacitance
per transceiver (A to B: outputs
enabled)
2.1
CL = 0, RL = Open f = 1
MHz, tr = tf = 1 ns
pF
2.0
2.0
2.1
2.3
1.5
1.5
1.5
Power Dissipation Capacitance
per transceiver (A to B: outputs
disabled)
1.4
CL = 0, RL = Open f = 1
MHz, tr = tf = 1 ns
pF
pF
pF
1.4
1.4
1.4
1.6
CpdA
12.1
12.1
12.1
12.4
13.0
14.2
17.4
20.1
1.1
Power Dissipation Capacitance
per transceiver (B to A: outputs
enabled)
CL = 0, RL = Open f = 1
MHz, tr = tf = 1 ns
1.1
1.1
Power Dissipation Capacitance
per transceiver (B to A: outputs
disabled)
1.1
CL = 0, RL = Open f = 1
MHz, tr = tf = 1 ns
1.1
1.1
1.1
1.1
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6.14 Operating Characteristics: TA = 25°C (continued)
PARAMETER
TEST CONDITIONS
VCCA
VCCB
0.7 V
MIN
TYP
12.1
12.1
12.1
12.4
12.9
14.1
17.2
20.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.2
1.8
1.8
1.7
1.7
1.7
2
MAX UNIT
0.7 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.7 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.7 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.7 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.7 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.7 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0.7 V
0.8 V
0.9 V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
Power Dissipation Capacitance
per transceiver (A to B: outputs
enabled)
CL = 0, RL = Open f = 1
MHz, tr = tf = 1 ns
pF
pF
pF
pF
Power Dissipation Capacitance
per transceiver (A to B: outputs
disabled)
CL = 0, RL = Open f = 1
MHz, tr = tf = 1 ns
CpdB
Power Dissipation Capacitance
per transceiver (B to A: outputs
enabled)
CL = 0, RL = Open f = 1
MHz, tr = tf = 1 ns
2.5
1.1
1.8
1.8
1.7
1.7
1.7
2
Power Dissipation Capacitance
per transceiver (B to A: outputs
disabled)
CL = 0, RL = Open f = 1
MHz, tr = tf = 1 ns
2.1
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6.15 Typical Characteristics
3.4
3.2
3
1.25
1.2
VCC = 1.8V
VCC = 2.5V
VCC = 3.3V
1.15
1.1
1.05
1
2.8
2.6
2.4
2.2
2
0.95
0.9
0.85
0.8
0.75
0.7
1.8
1.6
1.4
0.65
0.6
VCC = 0.7V
VCC = 1.2V
0.55
0
0.5
1
1.5
2
2.5
IOH (mA)
3
3.5
4
4.5
5
0
2
4
6
8
10
IOH (mA)
12
14
16
18
20
D001
D001
Figure 6-2. Typical (TA=25°C) Output High Voltage
(VOH) vs Source Current (IOH
Figure 6-1. Typical (TA=25°C) Output High Voltage
(VOH) vs Source Current (IOH
)
)
700
650
600
550
500
450
400
350
300
250
200
150
100
50
220
200
180
160
140
120
100
80
60
40
VCC = 1.8V
VCC = 2.5V
VCC = 3.3V
VCC = 0.7V
VCC = 1.2V
20
0
-50
0
0
2
4
6
8
10
IOL (mA)
12
14
16
18
20
0
0.5
1
1.5
2
2.5
IOL (mA)
3
3.5
4
4.5
5
D001
D001
Figure 6-3. Typical (TA=25°C) Output High Voltage Figure 6-4. Typical (TA=25°C) Output High Voltage
(VOL) vs Sink Current (IOL (VOL) vs Sink Current (IOL
)
)
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7 Parameter Measurement Information
7.1 Load Circuit and Voltage Waveforms
Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:
•
•
•
f = 1 MHz
ZO = 50 Ω
dv/dt ≤ 1 ns/V
Measurement Point
2 x VCCO
Open
S1
RL
Output Pin
Under Test
GND
(1)
CL
RL
A. CL includes probe and jig capacitance.
Figure 7-1. Load Circuit
Table 7-1. Load Circuit Conditions
Parameter
VCCO
RL
CL
S1
VTP
N/A
Δt/Δv Input transition rise or fall rate
0.65 V – 3.6 V
1.1 V – 3.6 V
0.65 V – 0.95 V
3 V – 3.6 V
1 MΩ
2 kΩ
20 kΩ
2 kΩ
2 kΩ
2 kΩ
20 kΩ
2 kΩ
2 kΩ
2 kΩ
20 kΩ
15 pF
15 pF
15 pF
15 pF
15 pF
15 pF
15 pF
15 pF
15 pF
15 pF
15 pF
Open
Open
N/A
tpd
Propagation (delay) time
Open
N/A
2 × VCCO
2 × VCCO
2 × VCCO
2 × VCCO
GND
0.3 V
0.15 V
0.1 V
0.1 V
0.3 V
0.15 V
0.1 V
0.1 V
1.65 V – 2.7 V
1.1 V – 1.6 V
0.65 V – 0.95 V
3 V – 3.6 V
ten, tdis Enable time, disable time
ten, tdis Enable time, disable time
1.65 V – 2.7 V
1.1 V – 1.6 V
0.65 V – 0.95 V
GND
GND
GND
(1)
VCCI
(1)
VCCI
Input A, B
100 kHz
VCCI / 2
VCCI / 2
Input A, B
500 ps/V œ 100 ns/V
0 V
0 V
VOH
(2)
VOH
tpd
tpd
(2)
Output B, A
Ensure Monotonic
Rising and Falling Edge
(2)
VOL
Output B, A
VCCI / 2
VCCI / 2
(2)
1. VCCI is the supply pin associated with the input port.
2. VOH and VOL are typical output voltage levels that occur
with specified RL, CL, and S1
VOL
1. VCCI is the supply pin associated with the input port.
2. VOH and VOL are typical output voltage levels that occur
with specified RL, CL, and S1
Figure 7-3. Input Transition Rise or Fall Rate
Figure 7-2. Propagation Delay
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VCCA
OE
VCCA / 2
VCCA / 2
GND
tdis
ten
(3)
VCCO
Output(1)
VCCO / 2
VOL + VTP
(4)
VOL
(4)
VOH
VOH - VTP
Output(2)
VCCO / 2
GND
A. Output waveform on the condition that input is driven to a valid Logic Low.
B. Output waveform on the condition that input is driven to a valid Logic High.
C. VCCO is the supply pin associated with the output port.
D. VOH and VOL are typical output voltage levels with specified RL, CL, and S1.
Figure 7-4. Enable Time And Disable Time
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8 Detailed Description
8.1 Overview
The SN74AXC4T245-Q1 AEC-Q100 qualified device is a 4-bit, dual-supply noninverting bidirectional voltage
level translation device. Ax pins and control pins (1DIR, 2DIR,1 OE, and 2 OE) are referenced to VCCA logic
levels, and Bx pins are referenced to VCCB logic levels. The A port is able to accept I/O voltages ranging from
0.65 V to 3.6 V, while the B port can accept I/O voltages from 0.65 V to 3.6 V. A high on DIR allows data
transmission from A to B and a low on DIR allows data transmission from B to A when OE is set to low. When
OE is set to high, both Ax and Bx pins are in the high-impedance state. See Device Functional Modes for a
summary of the operation of the control logic.
8.2 Functional Block Diagram
One of Two Transceiver Pairs
VCCA
VCCB
xDIR
xOE
xB1
xB2
xA1
xA2
8.3 Feature Description
8.3.1 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum
input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the
Electrical Characteristics, using ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Recommended Operating
Conditions to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a
device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.
8.3.2 Balanced High-Drive CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The high drive capability of this device
creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at
all times.
8.3.3 Partial Power Down (Ioff)
The inputs and outputs for this device enter a high-impedance state when the device is powered down, inhibiting
current backflow into the device. The maximum leakage into or out of any input or output pin on the device is
specified by Ioff in the Electrical Characteristics.
8.3.4 VCC Isolation
The inputs and outputs for this device enter a high-impedance state when either supply is <100 mV.
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8.3.5 Over-Voltage Tolerant Inputs
Input signals to this device can be driven above the supply voltage so long as they remain below the maximum
input voltage value specified in the Recommended Operating Conditions.
8.3.6 Glitch-Free Power Supply Sequencing
Either supply rail may be powered on or off in any order without producing a glitch on the I/Os (that is,
where the output erroneously transitions to VCC when it should be held low). Glitches of this nature can be
misinterpreted by a peripheral as a valid data bit, which could trigger a false device reset of the peripheral,
a false device configuration of the peripheral, or even a false data initialization by the peripheral. For more
information regarding the power up glitch performance of the AXC family of level translators, see Glitch Free
Power Sequencing With AXC Level Translators.
8.3.7 Negative Clamping Diodes
The inputs and outputs to this device have negative clamping diodes as depicted in Figure 8-1.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to
the device. The input negative-voltage and output voltage ratings may be exceeded if the input and
output clamp-current ratings are observed.
VCC
Device
Input
Output
Logic
GND
-IIK
-IOK
Figure 8-1. Electrical Placement of Clamping Diodes for Each Input and Output
8.3.8 Fully Configurable Dual-Rail Design
Both the VCCA and VCCB pins can be supplied at any voltage from 0.65 V to 3.6 V, making the device suitable for
translating between any of the voltage nodes (0.7 V, 0.8 V, 0.9 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V).
8.3.9 Supports High-Speed Translation
The SN74AXC4T245-Q1 device can support high data-rate applications. The translated signal data rate can be
up to 380 Mbps when the signal is translated from 1.8 V to 3.3 V.
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8.3.10 Wettable Flanks
This device includes wettable flanks for at least one package. See the Features section on the front page of the
data sheet for which packages include this feature.
Package
Package
Solder
Standard Lead
We able Flank Lead
Pad
PCB
Figure 8-2. Simplified Cutaway View of Wettable-Flank QFN Package and Standard QFN Package After
Soldering
Wettable flanks help improve side wetting after soldering which makes QFN packages easier to inspect with
automatic optical inspection (AOI). A wettable flank can be dimpled or step-cut to provide additional surface
area for solder adhesion which assists in reliably creating a side fillet as shown in Figure 8-2. Please see the
mechanical drawing for additional details.
8.4 Device Functional Modes
Table 8-1. Function Table (Each 2-Bit Section)
CONTROL INPUTS(1) (2)
PORT STATUS
OPERATION
OE DIR
A PORT
B PORT
Input (Hi-Z)
L
L
L
H
X
Output (Enabled)
Input (Hi-Z)
B data to A bus
A data to B bus
Isolation
Output (Enabled)
Input (Hi-Z)
H
Input (Hi-Z)
(1) Input circuits of the data I/Os are always active.
(2) Pins configured as inputs should not be left floating.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The AEC-Q100 qualified SN74AXC4T245-Q1 device can be used in level-translation applications for interfacing
devices or systems operating at different interface voltages with one another. The SN74AXC4T245-Q1 device is
ideal for use in applications where a push-pull driver is connected to the data I/Os. The maximum data rate can
be up to 380 Mbps when device translates a signal from 1.8 V to 3.3 V.
Figure 9-1 shows an example application where the SN74AXC4T245-Q1 device is used to translate a low
voltage UART signal from an SoC to a higher voltage signal which properly drives the inputs of the Bluetooth®
module, and vice versa.
9.2 Typical Application
Pullup Resistors keep device disabled
during power up. OE inputs may also
be tied to GND to keep device enabled
0.7 V
3.3 V
0.1 µF
0.1 µF
VCCA
VCCB
1DIR
2DIR
1OE
GPIO1
Bluetooth
Module
SN74AXC4T245-Q1
GPIO2
SoC
2OE
1A1
1A2
2A1
2A2
RX
TX
RTS
RX
1B1
CTS
TX
1B2
2B1
2B2
RTS
CTS
GND
Figure 9-1. UART Interface Application
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 9-1.
Table 9-1. Design Parameters
DESIGN PARAMETERS
Input voltage range
EXAMPLE VALUES
0.65 V to 3.6 V
0.65 V to 3.6 V
Output voltage range
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9.2.2 Detailed Design Procedure
To begin the design process, determine the following:
•
Input voltage range:
– Use the supply voltage of the device that is driving the SN74AXC4T245-Q1 device to determine the input
voltage range. For a valid logic-high, the value must exceed the high-level input voltage (VIH) of the input
port. For a valid logic low the value must be less than the low-level input voltage (VIL) of the input port.
Output voltage range:
•
– Use the supply voltage of the device that the SN74AXC4T245-Q1 device is driving to determine the output
voltage range.
9.2.3 Application Curve
Figure 9-2. Up Translation at 2.5 MHz (0.7 V to 3.3 V)
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10 Power Supply Recommendations
Always apply a ground reference to the GND pins first. This device is designed for glitch free power sequencing
without any supply sequencing requirements such as ramp order or ramp rate.
This device was designed with various power supply sequencing methods in mind to help prevent unintended
triggering of downstream devices. For more information regarding the power up glitch performance of the AXC
family of level translators, see Glitch Free Power Sequencing With AXC Level Translators.
11 Layout
11.1 Layout Guidelines
To ensure reliability of the device, following common printed-circuit board layout guidelines are recommended:
•
•
Use bypass capacitors on the power supply pins and place them as close to the device as possible.
Use short trace lengths to avoid excessive loading.
11.2 Layout Example
Legend
Via to VCCA
Via to VCCB
A
B
G
Via to GND
Copper Traces
SN74AXC4T245-Q1PW
0.1µF
0.1µF
A
G
B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCCA
VCCB
1DIR
2DIR
1A1
1OE
2OE
1B1
1B2
2B1
2B2
GND
RX to Module
TX from SoC
RTS from SoC
RX to SoC
G
G
CTS to Module
TX from Module
RTS from Module
1A2
2A1
CTS to SoC
2A2
GND
G
G
Figure 11-1. Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
•
•
•
•
•
•
Texas Instruments, Glitch Free Power Sequencing With AXC Level Translators application report
Texas Instruments, Implications of Slow or Floating CMOS Inputs application report
Texas Instruments, Low Voltage Translation For Standard Interfaces application report
Texas Instruments, Power Sequencing for AXC Family of Devices application report
Texas Instruments, SN74AXC4T245RSV EVM evaluation module user's guide
Texas Instruments, UART Interface Using SN74AXC4T245 video
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
Bluetooth® is a registered trademark of Bluetooth Special Interest Group (SIG).
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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18-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
CAXC4T245QBQBRQ1
CAXC4T245QRSVRQ1
CAXC4T245QWBQBRQ1
PCAXC4T245QWBQBRQ1
SN74AXC4T245QPWRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WQFN
UQFN
WQFN
WQFN
TSSOP
BQB
RSV
BQB
BQB
PW
16
16
16
16
16
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
4T245Q
NIPDAUAG
NIPDAU
Call TI
1ZDR
4T245Q
3000
TBD
2000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
4T245Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Dec-2021
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74AXC4T245-Q1 :
Catalog : SN74AXC4T245
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Dec-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CAXC4T245QBQBRQ1
CAXC4T245QRSVRQ1
WQFN
UQFN
BQB
RSV
BQB
PW
16
16
16
16
3000
3000
3000
2000
180.0
178.0
180.0
330.0
12.4
13.5
12.4
12.4
2.8
2.1
2.8
6.9
3.8
2.9
3.8
5.6
1.2
0.75
1.2
4.0
4.0
4.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
CAXC4T245QWBQBRQ1 WQFN
SN74AXC4T245QPWRQ1 TSSOP
1.6
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Dec-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CAXC4T245QBQBRQ1
CAXC4T245QRSVRQ1
CAXC4T245QWBQBRQ1
SN74AXC4T245QPWRQ1
WQFN
UQFN
BQB
RSV
BQB
PW
16
16
16
16
3000
3000
3000
2000
210.0
189.0
210.0
853.0
185.0
185.0
185.0
449.0
35.0
36.0
35.0
35.0
WQFN
TSSOP
Pack Materials-Page 2
PACKAGE OUTLINE
RSV0016A
UQFN - 0.55 mm max height
S
C
A
L
E
5
.
0
0
0
ULTRA THIN QUAD FLATPACK - NO LEAD
1.85
1.75
A
B
PIN 1 INDEX AREA
2.65
2.55
C
0.55
0.45
SEATING PLANE
0.05 C
0.05
0.00
2X 1.2
SYMM
℄
(0.13) TYP
5
8
0.45
0.35
15X
4
9
SYMM
℄
2X 1.2
12X 0.4
1
0.25
16X
12
0.15
0.07
0.05
C A B
13
16
0.55
0.45
PIN 1 ID
(45° X 0.1)
4220314/C 02/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RSV0016A
UQFN - 0.55 mm max height
ULTRA THIN QUAD FLATPACK - NO LEAD
SYMM
℄
(0.7)
16
SEE SOLDER MASK
DETAIL
13
12
16X (0.2)
1
SYMM
℄
12X (0.4)
(2.4)
(R0.05) TYP
9
4
15X (0.6)
5
8
(1.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 25X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4220314/C 02/2020
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RSV0016A
UQFN - 0.55 mm max height
ULTRA THIN QUAD FLATPACK - NO LEAD
(0.7)
16
13
16X (0.2)
1
12
SYMM
℄
12X (0.4)
(2.4)
(R0.05) TYP
4
9
15X (0.6)
5
8
SYMM
℄
(1.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 25X
4220314/C 02/2020
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
BQB 16
2.5 x 3.5, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226161/A
www.ti.com
PACKAGE OUTLINE
WQFN - 0.8 mm max height
PLASTIC QUAD FLAT PACK-NO LEAD
BQB0016A
A
2.6
2.4
B
3.6
3.4
PIN 1 INDEX AREA
C
0.8
0.7
SEATING PLANE
0.08 C
1.1
0.9
0.05
0.00
(0.2) TYP
2X 0.5
8
9
10X 0.5
7
10
SYMM
2X
2.5
2.1
1.9
15
2
0.30
0.18
16X
0.5
0.3
16
1
PIN 1 ID
(OPTIONAL)
SYMM
16X
0.1
C A B
0.05
C
4224640/A 11/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
WQFN - 0.8 mm max height
BQB0016A
PLASTIC QUAD FLAT PACK-NO LEAD
(2.3)
(1)
2X (0.5)
1
16
10X (0.5)
2
15
SYMM
2X
(2.5)
(2)
(3.3)
2X
(0.75)
10
7
16X (0.24)
16X (0.6)
(Ø0.2) VIA
TYP
9
8
SYMM
(R0.05) TYP
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
0.07 MIN
ALL AROUND
METAL
EXPOSED METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
EXPOSED METAL
NON-SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
4224640/A 11/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271)
.
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
WQFN - 0.8 mm max height
BQB0016A
PLASTIC QUAD FLAT PACK-NO LEAD
(2.3)
(0.95)
2X (0.5)
1
16
10X (0.5)
2
15
SYMM
2X
(2.5)
(1.79) (3.3)
10
7
16X (0.24)
16X (0.6)
EXPOSED METAL
9
8
SYMM
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
85% PRINTED COVERAGE BY AREA
SCALE: 20X
4224640/A 11/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
WQFN - 0.8 mm max height
INDSTNAME
BQB0016B
A
2.6
2.4
B
PIN 1 INDEX AREA
3.6
3.4
0.1 MIN
(0.13)
SECTION A-A
TYPICAL
C
0.8 MAX
SEATING PLANE
0.05
0.00
0.08 C
1.1
0.9
2X 0.5
(0.2) TYP
9
8
10X 0.5
7
10
(0.16)
SYMM
SYMM
2X
2.5
17
2.1
1.9
0.3
16X
0.2
0.1
0.05
C A B
C
15
2
PIN 1 ID
(OPTIONAL)
1
16
0.5
0.3
16X
SYMM
4226135/A 08/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
WQFN - 0.8 mm max height
INDSTNAME
BQB0016B
(2.3)
(1)
1
16
16X (0.6)
16X (0.25)
2
15
10X (0.5)
SYMM
17
(2)
(3.3)
2X (0.75)
10
7
(R0.05) TYP
(Ø 0.2) VIA
TYP
8
9
2X (0.5)
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
4226135/A 08/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271)
.
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
WQFN - 0.8 mm max height
INDSTNAME
BQB0016B
(2.3)
(0.95)
1
16
16X (0.6)
16X (0.25)
2
15
17
10X (0.5)
SYMM
(1.79)
(3.3)
2X (0.75)
10
7
(R0.05) TYP
METAL TYP
8
9
2X (0.5)
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
85% PRINTED COVERAGE BY AREA
SCALE: 20X
4226135/A 08/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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standards, and any other safety, security, regulatory or other requirements.
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Copyright © 2021, Texas Instruments Incorporated
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