SN74AXC1T45DCKR [TI]

单位双电源总线收发器 | DCK | 6 | -40 to 125;


型号：	SN74AXC1T45DCKR
厂家：	TEXAS INSTRUMENTS
描述：	单位双电源总线收发器 \| DCK \| 6 \| -40 to 125 总线收发器
文件：	总45页 (文件大小：2102K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN74AXC1T45

ZHCSHK6D –DECEMBER 2017 –REVISED OCTOBER 2021

具有可配置电压转换的SN74AXC1T45 单比特位双电源总线收发器

1 特性

3 说明

• 在0.65V 至3.6V 范围内进行上行和下行电平转换

SN74AXC1T45 是一款采用两个独立可配置电源轨的

单比特位同相总线收发器。V_CCA和 V_CCB电源电压低

至 0.65V 时，该器件可正常工作。A 端口用于跟踪

V_CCA，该端口可支持 0.65V 至 3.6V 范围内的任何电

源电压。B 端口用于跟踪 V_CCB，该端口也可支持

0.65V 至3.6V 范围内的任何电源电压。

• 工作温度：–40°C 至+125°C

• 设计采用毛刺信号抑制电路以提高电源定序性能

• 最大静态电流(I_CCA+ I_CCB) 为10µA（最高85°C）

和16µA（最高125°C）

• 从1.8V 转换到3.3V 时，支持高达500Mbps 的转

换速率

DIR 引脚决定信号传播的方向。DIR 引脚配置为高电平

时，信号转换由端口 A 流向端口 B。DIR 配置为低电

平时，则由端口B 流向端口A。DIR 引脚以V_CCA为基

准，这意味着它的逻辑高电平和逻辑低电平阈值跟踪

• V_CC隔离特性：

– 如果任何一个V_CC输入低于100mV，则所有

I/O 输出均禁用且处于高阻抗状态

• I_off支持局部断电模式运行

• 闩锁性能超过100mA，符合JESD 78 II 类规范

• ESD 保护性能超过JESD 22 规范要求

_CCA电压。

该器件完全符合使用 I_off电流的部分断电应用的规范要

求。当器件断电时，I_off保护电路可确保不从输入、输

出或偏置到特定电压的组合I/O 获取多余电流，也不向

其提供多余电流。

– 8000V 人体放电模型

– 1000V 充电器件模型

2 应用

V_CC隔离特性可确保当 V_CCA或 V_CCB低于 100mV

时，I/O 端口均禁用其输出并进入高阻态。

• 企业与通信

• 工业

• 个人电子产品

毛刺信号抑制电路使电源轨能以任何顺序打开或关断，

从而提供强大的电源定序性能。

器件信息

器件型号⁽¹⁾

封装尺寸（标称值）

2.90mm × 1.60mm

2.00mm × 1.25mm

1.60mm × 1.20mm

1.00mm x 1.00mm

1.00mm × 0.80mm

封装

SN74AXC1T45DBV

SN74AXC1T45DCK

SN74AXC1T45DRL

SN74AXC1T45DEA

SN74AXC1T45DTQ

SOT-23 (6)

SC70 (6)

SOT-5X3 (6)

X2SON (6)

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

0.7 V

3.3 V

Processor

V_CCA

DIR

V_CCB

Power Management

Unit

Control Block

SN74AXC1T45

简化版原理图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SCES882

SN74AXC1T45

ZHCSHK6D –DECEMBER 2017 –REVISED OCTOBER 2021

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Table of Contents

8.3 Feature Description...................................................20

8.4 Device Functional Modes..........................................20

9 Application and Implementation..................................21

9.1 Application Information............................................. 21

9.2 Typical Applications.................................................. 21

10 Power Supply Recommendations..............................25

10.1 Power-Up Considerations.......................................25

11 Layout...........................................................................25

11.1 Layout Guidelines................................................... 25

11.2 Layout Example...................................................... 25

12 Device and Documentation Support..........................26

12.1 Documentation Support.......................................... 26

12.2 接收文档更新通知................................................... 26

12.3 支持资源..................................................................26

12.4 Trademarks.............................................................26

12.5 Electrostatic Discharge Caution..............................26

12.6 术语表..................................................................... 26

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................6

6.6 Switching Characteristics ...........................................7

6.7 Operating Characteristics: T_A= 25°C....................... 14

6.8 Typical Characteristics..............................................15

7 Parameter Measurement Information..........................18

7.1 Load Circuit and Voltage Waveforms........................18

8 Detailed Description......................................................20

8.1 Overview...................................................................20

8.2 Functional Block Diagram.........................................20

Information.................................................................... 26

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision C (September 2020) to Revision D (October 2021)

Page

• Updated the Pin Configuration and Functions section to include DRL and DEA packages............................... 3

Changes from Revision B (June 2018) to Revision C (September 2020)

Page

• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1

• 将所有表更新为最新的3d 表格式.......................................................................................................................1

• Updated I_CCA, I_CCB, and I_CCA+ I_CCBto reflect updated performance of device..................................................6

Changes from Revision A (April 2018) to Revision B (June 2018)

Page

• 添加了DEA 和DTQ 作为可用封装选项..............................................................................................................1

• 将产品状态从“量产混合”更改为“量产数据”................................................................................................ 1

Changes from Revision * (December 2017) to Revision A (April 2018)

Page

• Added pinout drawing for DEA package ............................................................................................................3

• Added pinout drawing for DTQ package ............................................................................................................3

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5 Pin Configuration and Functions

V_CCA

GND

V_CCB

DIR

V_CCA

GND

V_CCB

DIR

图5-2. DCK Package

6-Pin SC70

图5-1. DBV Package

6-Pin SOT-23

Top View

V_CCA

GND

V_CCB

DIR

V_CCA

GND

V_CCB

DIR

图5-4. DEA Package

6-Pin X2SON

Transparent Top View

图5-3. DRL Package

6-Pin SOT-5X3

Top View

V_CCA

GND

V_CCB

DIR

图5-5. DTQ Package

6-Pin X2SON

Transparent Top View

表5-1. Pin Functions

TYPE

NO.

DESCRIPTION

NAME

Input or output A. This pin is referenced to V_CCA. When this pin is configured as an input, do

not leave it floating.

I/O

Input or output B. This pin is referenced to V_CCB. When this pin is configured as an input, do

not leave it floating.

Direction control signal. Set to Logic High for A-to-B level translation. Set to Logic Low for B-

to-A level translation.

DIR

GND

V_CCA

V_CCB

Ground.

—

A-port supply voltage. 0.65 V ≤V_CCA≤3.6 V.

B-port supply voltage. 0.65 V ≤V_CCB≤3.6 V.

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.5

–50

MAX UNIT

V_CCASupply voltage A

V_CCBSupply voltage B

4.2

I/O Ports (A Port)

I/O Ports (B Port)

Control Inputs

A Port

4.2

V_I

Input Voltage⁽²⁾

4.2

V_O

Voltage applied to any output in the high-impedance or power-off state⁽²⁾

Voltage applied to any output in the high or low state^{(2) (3)}

B Port

4.2

A Port

V_CCA+ 0.2

V_CCB+ 0.2

B Port

I_IK

I_OK

I_O

Input clamp current

V_I< 0

Output clamp current

V_O< 0

–50

Continuous output current

Continuous current through V_CCor GND

Junction Temperature

50 mA

100 mA

150 °C

–50

–100

T_J

T_STGStorage temperature

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

(3) The output positive-voltage rating may be exceeded up to 4.2 V maximum if the output current rating is observed.

6.2 ESD Ratings

VALUE

±8000

±1000

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)Electrostatic discharge

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)^{(1) (2) (3)}

MIN

0.65

MAX UNIT

V_CCA

V_CCB

Supply voltage A

Supply voltage B

3.6

0.65

V_CCI= 0.65 V - 0.75 V

V_CCI= 0.76 V - 1 V

V_CCI= 1.1 V - 1.95 V

V_CCI= 2.3 V - 2.7 V

V_CCI= 3 V - 3.6 V

V_CCIx 0.70

V_CCIx 0.65

1.6

Data Inputs

V_IH

High-level input voltage

V_CCA= 0.65 V - 0.75 V

V_CCA= 0.76 V - 1 V

V_CCA= 1.1 V - 1.95 V

V_CCA= 2.3 V - 2.7 V

V_CCA= 3 V - 3.6 V

V_CCI= 0.65 V - 0.75 V

V_CCI= 0.76 V - 1 V

V_CCI= 1.1 V - 1.95 V

V_CCI= 2.3 V - 2.7 V

V_CCI= 3 V - 3.6 V

V_CCAx 0.70

V_CCAx 0.65

1.6

Control Input (DIR)

Referenced to V_CCA

V_CCIx 0.30

V_CCIx 0.35

0.7

Data Inputs

0.8

V_IL

Low-level input voltage

V_CCA= 0.65 V - 0.75 V

V_CCA= 0.76 V - 1 V

V_CCA= 1.1 V - 1.95 V

V_CCA= 2.3 V - 2.7 V

V_CCA= 3 V - 3.6 V

V_CCAx 0.30

V_CCAx 0.35

0.7

Control Input (DIR)

Referenced to V_CCA

0.8

V_I

Input voltage ⁽³⁾

Output voltage

3.6

Active State

Tri-State

V_CCO

V_O

3.6

Input transition rate

100 ns/V

125 °C

Δt/Δv

T_A

Operating free-air temperature

–40

(1) VCCI is the VCC associated with the input port.

(2) VCCO is the VCC associated with the output port.

(3) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs.

6.4 Thermal Information

SN74AXC1T45

DBV

(SOT-23)

DCK

(SC70)

DRL

(SOT-5X3)

DEA

(X2SON)

DTQ

(X2SON)

THERMAL METRIC⁽¹⁾

UNIT

6 PINS

202.2

137.2

80.2

6 PINS

235.3

160.5

76.9

6 PINS

298.9

148.4

165.0

20.7

6 PINS

358.0

201.0

221.8

26.1

6 PINS

327.8

194.9

248.4

24.1

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)Junction-to-case (top) thermal resistance

R_θJB

ψ_JT

Junction-to-board thermal resistance

Junction-to-top characterization parameter

Junction-to-board characterization parameter

64.0

59.7

80.4

77.1

164.9

220.8

247.6

ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) ^{(1) (2)}

Operating free-air temperature (T_A)

UNI

PARAMETER

TEST CONDITIONS

V_CCA

V_CCB

–40°C to 85°C

–40°C to 125°C

MIN TYP⁽³⁾MAX

MIN

TYP MAX

V_CCO

–0.1

V_CCO

–0.1

I_OH= -100 µA

0.7 V - 3.6 V

I_OH= -50 µA

I_OH= -200 µA

I_OH= -500 µA

0.65 V

0.76 V

0.85 V

1.1 V

0.65 V

0.76 V

0.85 V

1.1 V

0.55

0.58

0.65

0.85

1.05

1.2

0.55

0.58

0.65

0.85

1.05

1.2

High-level

output voltage

V_OH

V_I= V_IH

I_OH= -3 mA

I_OH= -6 mA

I_OH= -8 mA

I_OH= -9 mA

I_OH= -12 mA

I_OL= 100 µA

I_OL= 50 µA

I_OL= 200 µA

I_OL= 500 µA

I_OL= 3 mA

I_OL= 6 mA

I_OL= 8 mA

I_OL= 9 mA

I_OL= 12 mA

1.4 V

1.65 V

2.3 V

1.65 V

2.3 V

1.75

2.3

1.75

2.3

3 V

0.7 V - 3.6 V

0.65 V

0.76 V

0.85 V

1.1 V

0.7 V - 3.6 V

0.65 V

0.76 V

0.85 V

1.1 V

0.1

0.18

0.2

0.18

0.2

Low-level

output voltage

V_OL

V_I= V_IL

0.25

0.35

0.45

0.55

0.7

0.25

0.35

0.45

0.55

0.7

1.4 V

1.65 V

2.3 V

1.65 V

2.3 V

3 V

Control input (DIR): V_I=

V_CCAor GND

0.65 V- 3.6 V 0.65 V- 3.6 V

1.5

–1

–4

–1.5

–8

Input leakage

current

I_I

µA

A or B Port: Vi = V_CCIor

GND

0 V

0 V - 3.6 V

0 V

7.5

–5

–7.5

Partial power A or B Port: Vi or Vo = 0 V -

down current 3.6 V

I_off

µA

0 V - 3.6 V

0.65 V- 3.6 V 0.65 V- 3.6 V

V_CCAsupply

current

V_I= V_CCI

or GND

I_CCA

I_O= 0

0 V

3.6 V

0 V

–2

–8

3.6 V

0.65 V- 3.6 V 0.65 V- 3.6 V

V_CCBsupply

current

V_I= V_CCI

or GND

0 V

3.6 V

0 V

I_CCB

I_O= 0

µA

3.6 V

–2

–8

I_CCA

I_CCB

Combined

supply current or GND

V_I= V_CCI

0.65 V- 3.6 V 0.65 V- 3.6 V

16 µA

Control input

capacitance

C_I

V_I= 3.3 V or GND

3.3 V

0 V

4.4

Data I/O

capacitance,

A Port

V_O= 1.65V DC +1 MHz -16

dBm sine wave

C_IO

Data I/O

capacitance,

B Port

V_O= 1.65V DC +1 MHz -16

dBm sine wave

C_IO

0 V

3.3 V

(1) VCCI is the VCC associated with the input port.

(2) VCCO is the VCC associated with the output port.

(3) All typical data is taken at 25°C.

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6.6 Switching Characteristics

表6-1. Switching Characteristics, V_CCA= 0.7 V

B–PORT SUPPLY VOLTAGE (V_CCB

1.2 ± 0.1 V 1.5 ± 0.1 V

MAX MAX

)

TEST

CONDITIONS

PARAMETER

FROM

UNIT

0.7 ± 0.05 V

MIN MAX

0.8 ± 0.04 V

MAX

0.9 ± 0.045 V

MAX

1.8 ± 0.15 V

MAX

2.5 ± 0.2 V

MAX

3.3 ± 0.3 V

MAX

MIN

0.5

MIN

0.5

MIN

0.5

MIN

0.5

MIN

0.5

MIN

0.5

MIN

0.5

173

143

163

389

406

369

395

117

154

143

123

331

333

313

339

143

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

t_pd

t_dis

t_en

Propagation delay

127

143

100

287

281

307

143

109

200

339

365

DIR

Disable time

Enable time

143

247

273

134

246

272

137

249

275

147

261

287

表6-2. Switching Characteristics, V_CCA= 0.8 V

B–PORT SUPPLY VOLTAGE (V_CCB

1.2 ± 0.1 V 1.5 ± 0.1 V

MAX MAX

)

TEST

CONDITIONS

PARAMETER

FROM

UNIT

0.7 ± 0.05 V

MIN MAX

0.8 ± 0.04 V

MAX

0.9 ± 0.045 V

MAX

1.8 ± 0.15 V

MAX

2.5 ± 0.2 V

MAX

3.3 ± 0.3 V

MAX

MIN

0.5

MIN

0.5

MIN

0.5

MIN

0.5

MIN

0.5

MIN

0.5

MIN

0.5

153

117

100

151

321

341

309

317

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

–40°C to 85°C

–40°C to 125°C

t_pd

t_dis

t_en

Propagation delay

100

111

261

266

251

259

100

DIR

Disable time

Enable time

226

229

220

228

189

197

183

191

182

190

183

191

192

200

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表6-3. Switching Characteristics, V_CCA= 0.9 V

B–PORT SUPPLY VOLTAGE (V_CCB

)

TEST

CONDITIONS

PARAMETER

FROM

UNIT

0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

0.5

126

0.5

–40°C to 85°C

–40°C to

125°C

Propagation

delay

t_pd

–40°C to 85°C

–40°C to

125°C

–40°C to 85°C

DIR

–40°C to

125°C

t_disDisable time

144

282

304

262

269

105

223

229

214

221

–40°C to 85°C

–40°C to

125°C

195

199

188

195

–40°C to 85°C

–40°C to

125°C

t_enEnable time

159

166

154

161

152

159

151

158

154

161

–40°C to 85°C

–40°C to

125°C

表6-4. Switching Characteristics, V_CCA= 1.2 V

B–PORT SUPPLY VOLTAGE (V_CCB

)

TEST

CONDITIONS

PARAMETER

FROM

UNIT

0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

0.5

–40°C to 85°C

–40°C to

125°C

Propagation

delay

t_pd

–40°C to 85°C

–40°C to

125°C

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PARAMETER

表6-4. Switching Characteristics, V_CCA= 1.2 V (continued)

B–PORT SUPPLY VOLTAGE (V_CCB

)

TEST

FROM

UNIT

0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

CONDITIONS

0.5

–40°C to 85°C

DIR

–40°C to

125°C

t_disDisable time

137

240

265

115

121

–40°C to 85°C

–40°C to

125°C

185

193

157

164

–40°C to 85°C

–40°C to

125°C

t_enEnable time

–40°C to 85°C

–40°C to

125°C

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表6-5. Switching Characteristics, V_CCA= 1.5 V

B–PORT SUPPLY VOLTAGE (V_CCB

)

TEST

CONDITIONS

PARAMETER

FROM

UNIT

0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

0.5

–40°C to 85°C

–40°C to

125°C

Propagation

delay

t_pd

–40°C to 85°C

–40°C to

125°C

–40°C to 85°C

DIR

–40°C to

125°C

t_disDisable time

136

238

263

104

109

–40°C to 85°C

–40°C to

125°C

178

186

151

157

–40°C to 85°C

–40°C to

125°C

t_enEnable time

–40°C to 85°C

–40°C to

125°C

表6-6. Switching Characteristics, V_CCA= 1.8 V

B–PORT SUPPLY VOLTAGE (V_CCB

)

TEST

CONDITIONS

PARAMETER

FROM

UNIT

0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

0.5

–40°C to 85°C

–40°C to

125°C

Propagation

delay

t_pd

–40°C to 85°C

–40°C to

125°C

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PARAMETER

表6-6. Switching Characteristics, V_CCA= 1.8 V (continued)

B–PORT SUPPLY VOLTAGE (V_CCB

)

TEST

FROM

UNIT

0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

CONDITIONS

0.5

–40°C to 85°C

DIR

–40°C to

125°C

t_disDisable time

136

241

266

101

105

–40°C to 85°C

–40°C to

125°C

176

184

148

155

–40°C to 85°C

–40°C to

125°C

t_enEnable time

–40°C to 85°C

–40°C to

125°C

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表6-7. Switching Characteristics, V_CCA= 2.5 V

B–PORT SUPPLY VOLTAGE (V_CCB

)

TEST

CONDITIONS

PARAMETER

FROM

UNIT

0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

0.5

–40°C to 85°C

–40°C to

125°C

Propagation

delay

t_pd

–40°C to 85°C

–40°C to

125°C

–40°C to 85°C

DIR

–40°C to

125°C

t_disDisable time

136

254

278

–40°C to 85°C

–40°C to

125°C

176

185

147

153

–40°C to 85°C

–40°C to

125°C

t_enEnable time

–40°C to 85°C

–40°C to

125°C

表6-8. Switching Characteristics, V_CCA= 3.3 V

B–PORT SUPPLY VOLTAGE (V_CCB

)

TEST

CONDITIONS

PARAMETER

FROM

UNIT

0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

0.5

–40°C to 85°C

–40°C to

125°C

Propagation

delay

t_pd

144

–40°C to 85°C

–40°C to

125°C

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PARAMETER

表6-8. Switching Characteristics, V_CCA= 3.3 V (continued)

B–PORT SUPPLY VOLTAGE (V_CCB

)

TEST

FROM

UNIT

0.7 ± 0.05 V 0.8 ± 0.04 V 0.9 ± 0.045 V 1.2 ± 0.1 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 ± 0.1 V

MIN MAX

1.8 ± 0.15 V

MIN MAX

2.5 ± 0.2 V

MIN MAX

3.3 ± 0.3 V

MIN MAX

CONDITIONS

0.5

–40°C to 85°C

DIR

–40°C to

125°C

t_disDisable time

136

331

356

–40°C to 85°C

–40°C to

125°C

185

149

156

–40°C to 85°C

–40°C to

125°C

t_enEnable time

–40°C to 85°C

–40°C to

125°C

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MAX UNIT

6.7 Operating Characteristics: T_A= 25°C

PARAMETER

TEST CONDITIONS

V_CCA

0.7 V

V_CCB

0.7 V

MIN

TYP

1.3

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

0.7 V

0.8 V

0.9 V

1.2 V

1.5 V

1.8 V

2.5 V

3.3 V

1.3

Power Dissipation Capacitance C_L= 0, R_L= Open f = 1

per transceiver (A to B)

MHz, t_r= t_f= 1 ns

1.3

1.4

1.7

2.1

C_pdA

9.2

9.4

9.8

Power Dissipation Capacitance C_L= 0, R_L= Open f = 1

per transceiver (B to A) MHz, t_r= t_f= 1 ns

10.1

11.0

14.4

18.6

9.2

9.3

9.4

9.7

Power Dissipation Capacitance C_L= 0, R_L= Open f = 1

per transceiver (A to B) MHz, t_r= t_f= 1 ns

10.1

11.0

14.4

18.3

1.3

C_pdB

1.3

Power Dissipation Capacitance C_L= 0, R_L= Open f = 1

per transceiver (B to A)

MHz, t_r= t_f= 1 ns

1.3

1.4

1.7

2.1

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6.8 Typical Characteristics

C_L= 45 pF

C_L= 62 pF

C_L= 79 pF

C_L= 105 pF

C_L= 123 pF

C_L= 45 pF

C_L= 62 pF

C_L= 79 pF

C_L= 105 pF

C_L= 123 pF

0.6

0.9

1.2

1.5

1.8 2.1

Supply B (V)

2.4

2.7

3.3

0.6

0.9

1.2

1.5

1.8 2.1

Supply B (V)

2.4

2.7

3.3

D016

D001

T_A= 25°C V_CCA= 0.7 V

T_A= 25°C V_CCA= 0.8 V

图6-1. Typical Propagation Delay of Low-to-High

图6-2. Typical Propagation Delay of Low-to-High

(A to B) vs Load Capacitance

C_L= 45 pF

C_L= 62 pF

C_L= 79 pF

C_L= 105 pF

C_L= 123 pF

C_L= 45 pF

C_L= 62 pF

C_L= 79 pF

C_L= 105 pF

C_L= 123 pF

0.6

0.9

1.2

1.5

1.8 2.1

Supply B (V)

2.4

2.7

3.3

0.6

0.9

1.2

1.5

1.8 2.1

Supply B (V)

2.4

2.7

3.3

D002

D003

T_A= 25°C V_CCA= 0.9 V

T_A= 25°C V_CCA= 1.2 V

图6-3. Typical Propagation Delay of Low-to-High

图6-4. Typical Propagation Delay of Low-to-High

(A to B) vs Load Capacitance

C_L= 45 pF

C_L= 62 pF

C_L= 79 pF

C_L= 105 pF

C_L= 123 pF

C_L= 62 pF

C_L= 79 pF

C_L= 105 pF

C_L= 123 pF

0.6

0.9

1.2

1.5

1.8 2.1

Supply B (V)

2.4

2.7

3.3

0.6

0.9

1.2

1.5

1.8 2.1

Supply B (V)

2.4

2.7

3.3

D004

D005

T_A= 25°C V_CCA= 1.5 V

T_A= 25°C V_CCA= 1.8 V

图6-5. Typical Propagation Delay of Low-to-High

图6-6. Typical Propagation Delay of Low-to-High

(A to B) vs Load Capacitance

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6.8 Typical Characteristics (continued)

C_L= 45 pF

C_L= 62 pF

C_L= 79 pF

C_L= 105 pF

C_L= 123 pF

C_L= 62 pF

C_L= 79 pF

C_L= 105 pF

C_L= 123 pF

0.6

0.9

1.2

1.5

1.8 2.1

Supply B (V)

2.4

2.7

3.3

0.6

0.9

1.2

1.5

1.8 2.1

Supply B (V)

2.4

2.7

3.3

D007

D006

T_A= 25°C V_CCA= 3.3 V

T_A= 25°C V_CCA= 2.5 V

图6-7. Typical Propagation Delay of Low-to-High

图6-8. Typical Propagation Delay of Low-to-High

(A to B) vs Load Capacitance

C_L= 45 pF

C_L= 62 pF

C_L= 79 pF

C_L= 105 pF

C_L= 123 pF

C_L= 45 pF

C_L= 62 pF

C_L= 79 pF

C_L= 105 pF

C_L= 123 pF

0.6

0.9

1.2

1.5

1.8 2.1

Supply A (V)

2.4

2.7

3.3

0.6

0.9

1.2

1.5

1.8 2.1

Supply A (V)

2.4

2.7

3.3

D008

D009

T_A= 25°C V_CCA= 0.7 V

T_A= 25°C V_CCA= 0.8 V

图6-9. Typical Propagation Delay of Low-to-High

图6-10. Typical Propagation Delay of Low-to-High

(B to A) vs Load Capacitance

27.5

C_L= 45 pF

C_L= 62 pF

C_L= 79 pF

C_L= 105 pF

C_L= 123 pF

C_L= 62 pF

C_L= 79 pF

C_L= 105 pF

C_L= 123 pF

22.5

17.5

12.5

7.5

0.6

0.9

1.2

1.5

1.8 2.1

Supply A (V)

2.4

2.7

3.3

0.6

0.9

1.2

1.5

1.8 2.1

Supply A (V)

2.4

2.7

3.3

D010

D011

T_A= 25°C V_CCA= 0.9 V

T_A= 25°C V_CCA= 1.2 V

图6-11. Typical Propagation Delay of Low-to-High

图6-12. Typical Propagation Delay of Low-to-High

(B to A) vs Load Capacitance

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6.8 Typical Characteristics (continued)

C_L= 45 pF

C_L= 62 pF

C_L= 79 pF

C_L= 105 pF

C_L= 123 pF

C_L= 62 pF

C_L= 79 pF

C_L= 105 pF

C_L= 123 pF

22.5

17.5

12.5

7.5

0.6

0.9

1.2

1.5

1.8 2.1

Supply A (V)

2.4

2.7

3.3

0.6

0.9

1.2

1.5

1.8 2.1

Supply A (V)

2.4

2.7

3.3

D012

D013

T_A= 25°C V_CCA= 1.5 V

T_A= 25°C

V_CCA= 1.8 V

图6-13. Typical Propagation Delay of Low-to-High

图6-14. Typical Propagation Delay of Low-to-High

(B to A) vs Load Capacitance

C_L= 45 pF

C_L= 62 pF

C_L= 79 pF

C_L= 105 pF

C_L= 123 pF

C_L= 45 pF

C_L= 62 pF

C_L= 79 pF

C_L= 105 pF

C_L= 123 pF

0.6

0.9

1.2

1.5

1.8 2.1

Supply A (V)

2.4

2.7

3.3

0.6

0.9

1.2

1.5

1.8 2.1

Supply A (V)

2.4

2.7

3.3

D014

D015

T_A= 25°C V_CCA= 2.5 V

T_A= 25°C V_CCA= 3.3 V

图6-15. Typical Propagation Delay of Low-to-High

图6-16. Typical Propagation Delay of Low-to-High

(B to A) vs Load Capacitance

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7 Parameter Measurement Information

7.1 Load Circuit and Voltage Waveforms

Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:

• f = 1 MHz

• Z_O= 50 Ω

• dv/dt ≤1 ns/V

Measurement Point

2 x V_CCO

Open

GND

R_L

Output Pin

Under Test

(1)

C_L

R_L

A. C_Lincludes probe and jig capacitance.

图7-1. Load Circuit

表7-1. Load Circuit Conditions

Parameter

V_CCO

R_L

C_L

S₁

V_TP

N/A

Δt/

Δv

Input transition rise or fall rate

15 pF

Open

0.65 V –3.6 V

1.1 V –3.6 V

1 MΩ

2 kΩ

20 kΩ

t_pd

Propagation (delay) time

0.65 V –0.95

15 pF

2 × V_CCO

0.3 V

0.15 V

0.1 V

3 V –3.6 V

1.65 V –2.7 V

1.1 V –1.6 V

2 kΩ

t_en, t_disEnable time, disable time

0.65 V –0.95

15 pF

2 × V_CCO

0.1 V

20 kΩ

15 pF

GND

0.3 V

0.15 V

0.1 V

3 V –3.6 V

1.65 V –2.7 V

1.1 V –1.6 V

2 kΩ

t_en, t_disEnable time, disable time

0.65 V –0.95

15 pF

GND

0.1 V

20 kΩ

(1)

V_CCI

(1)

V_CCI

Input A, B

100 kHz

V_CCI/ 2

Input A, B

500 ps/V œ 100 ns/V

0 V

V_OH

0 V

V_OH

(2)

t_pd

(2)

Output B, A

Ensure Monotonic

Rising and Falling Edge

(2)

V_OL

Output B, A

V_CCI/ 2

(2)

V_OL

1. V_CCIis the supply pin associated with the input port.

2. V_OHand V_OLare typical output voltage levels that occur

with specified R_L, C_L, and S₁

1. V_CCIis the supply pin associated with the input port.

2. V_OHand V_OLare typical output voltage levels that occur

with specified R_L, C_L, and S₁

图7-3. Input Transition Rise or Fall Rate

图7-2. Propagation Delay

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V_CCA

V_CCA/ 2

DIR

V_CCA/ 2

GND

(1)

t_en

(5)

V_CCO

Output A⁽²⁾

Output A⁽³⁾

V_CCO/ 2

V_OL+ V_TP

(6)

V_OL

t_dis

(6)

V_OH

V_OH- V_TP

V_CCO/ 2

GND

(1)

t_en

(5)

V_CCO

Output B⁽²⁾

Output B⁽³⁾

V_CCO/ 2

V_OL+ V_TP

(6)

V_OL

t_dis

(6)

V_OH

V_OH- V_TP

V_CCO/ 2

GND

1. Illustrative purposes only. Enable Time is a calculation as described in the data sheet.

2. Output waveform on the condition that input is driven to a valid Logic Low.

3. Output waveform on the condition that input is driven to a valid Logic High.

4. V_CCIis the supply pin associated with the input port

5. V_CCOis the supply pin associated with the output port.

6. V_OHand V_OLare typical output voltage levels that occur with specified R_L, C_L, and S₁

图7-4. Disable and Enable Time

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8 Detailed Description

8.1 Overview

The SN74AXC1T45 is single-bit, dual-supply, noninverting voltage level translation. Pin A and the direction

control pin are support by V_CCAand pin B is support by V_CCB. The A port can accept I/O voltages ranging from

0.65 V to 3.6 V, and the B port can accept I/O voltages from 0.65 V to 3.6 V. A high logic on the DIR pin allows

data transmission from A to B and a logic low on the DIR pin allows data transmission from B to A.

8.2 Functional Block Diagram

DIR

CCB

CCA

8.3 Feature Description

8.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 0.65-V to 3.6-V

Power-Supply Range

Both the V_CCAand V_CCBpins can be supplied at any voltage from 0.65 V to 3.6 V, making the device suitable for

translating between any of the voltage nodes (0.7 V, 0.8 V, 0.9 V, 1.2 V, 1.8 V, 2.5 V and 3.3 V).

8.3.2 Support High-Speed Translation

The SN74AXC1T45 device can support high data-rate applications. The translated signal data rate can be up to

500 Mbps when signal is translated from 1.8 V to 3.3 V.

8.3.3 I_offSupports Partial-Power-Down Mode Operation

The I_offcircuit prevents backflow current by disabling the I/O output circuits when the device is in partial-power-

down mode.

8.4 Device Functional Modes

表8-1 lists the device functions for the DIR input.

表8-1. Function Table

INPUT⁽¹⁾

OPERATION

DIR

B data to A bus

A data to B bus

(1) Input circuits of the data I/Os

always are active.

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

9.1 Application Information

The SN74AXC1T45 device can be used in level-translation applications for interfacing devices or systems with

one another when they are operating at different interface voltages. The maximum data rate can be up to 500

Mbps when the device translate signal is from 1.8 V to 3.3 V.

9.1.1 Enable Times

Calculate the enable times for the SN74AXC1T45 using the following formulas:

t_{A_en}(DIR to A) = t_dis(DIR to B) + t_pd(B to A)

t_{B_en}(DIR to B) = t_dis(DIR to A) + t_pd(A to B)

(1)

(2)

In a bidirectional application, these enable times provide the maximum delay time from the time the DIR bit is

switched until an output is expected. For example, if the SN74AXC1T45 initially is transmitting from A to B, then

the DIR bit is switched; the B port of the device must be disabled (t_dis)before presenting it with an input. After the

B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified

propagation delay (t_pd). To avoid bus contention care should be taken to not apply an input signal prior to the

output port being disabled (t_dismax).

9.2 Typical Applications

9.2.1 Unidirectional Logic Level-Shifting Application

图9-1 shows an example of the SN74AXC1T45 being used in a unidirectional logic level-shifting application.

CC1

CC2

SYSTEM-1

SYSTEM-2

图9-1. Unidirectional Logic Level-Shifting Application

表9-1. Unidirectional Level Shifting Function

NAME

V_CCA

GND

FUNCTION

V_CC1

GND

OUT

DESCRIPTION

SYSTEM-1 supply voltage (0.65 V to 3.6 V)

Device GND

Output level depends on V_CC1voltage.

Input threshold value depends on V_CC2voltage.

GND (low level) determines B-port to A-port direction.

SYSTEM-2 supply voltage (0.65 V to 3.6 V)

DIR

V_CCB

DIR

V_CC2

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9.2.1.1 Design Requirements

For this design example, use the parameters listed in 表9-2.

表9-2. Design Parameters

DESIGN PARAMETERS

Input voltage range

EXAMPLE VALUES

0.65 V to 3.6 V

Output voltage range

0.65 V to 3.6 V

9.2.1.2 Detailed Design Procedure

To begin the design process, determine the following:

• Input voltage range

– Use the supply voltage of the device that is driving the SN74AXC1T45 device to determine the input

voltage range. For a valid logic-high, the value must exceed the high-level input voltage (V_IH) of the input

port. For a valid logic low the value must be less than the low-level input voltage (V_IL) of the input port.

• Output voltage range

– Use the supply voltage of the device that the SN74AXC1T45 device is driving to determine the output

voltage range.

9.2.1.3 Application Curve

图9-2. Up Translation at 2.5 MHz (0.7 V to 3.3 V)

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9.2.2 Bidirectional Logic Level-Shifting Application

图 9-3 shows the SN74AXC1T45 being used in a bidirectional logic level-shifting application. Because the

SN74AXC1T45 does not have an output-enable (OE) pin, the system designer should take precautions to avoid

bus contention between SYSTEM-1 and SYSTEM-2 when changing directions.

CC1

CC2

Pullup/Pulldown

†

Pullup/Pulldown

†

I/O-1

I/O-2

or Bus Hold

DIR CTRL

SYSTEM-1

SYSTEM-2

图9-3. Bidirectional Logic Level-Shifting Application

表9-3 lists the data transmission from SYSTEM-1 to SYSTEM-2 and then from SYSTEM-2 to SYSTEM-1.

表9-3. Data Transmission: SYSTEM-1 and SYSTEM-2

STATE DIR CTRL

I/O-1

I/O-2

DESCRIPTION

Out

SYSTEM-1 data to SYSTEM-2.

SYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1 and I/O-2 are disabled. The bus-

line state depends on pullup or pulldown resistors.⁽¹⁾

Hi-Z

DIR bit is flipped. I/O-1 and I/O-2 still are disabled. The bus-line state depends on pullup or

pulldown resistors.⁽¹⁾

Hi-Z

Out

SYSTEM-2 data to SYSTEM-1.

(1) SYSTEM-1 and SYSTEM-2 must use the same conditions, essentially, both pullup or both pulldown.

9.2.2.1 Design Requirements

Refer to Design Requirements.

9.2.2.2 Detailed Design Procedure

Refer to Detailed Design Procedure.

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9.2.2.3 Application Curve

图9-4. Up Translation at 2.5 MHz (0.7 V to 3.3 V)

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10 Power Supply Recommendations

The SN74AXC1T45 device uses two separate configurable power-supply rails, V_CCAand V_CCB. The V_CCA

power-supply rail accepts any supply voltage from 0.65 V to 3.6 V and the V_CCBpower-supply rail accepts any

supply voltage from 0.65 V to 3.6 V. The A port and B port are designed to track the V_CCAand V_CCBsupplies

respectively allowing for low-voltage, bidirectional translation between any of the 0.7 V, 0.8 V, 0.9 V, 1.2 V, 1.5 V,

1.8 V, 2.5 V, and 3.3 V voltage nodes.

10.1 Power-Up Considerations

A proper power-up sequence must be followed to avoid excessive supply current, bus contention, oscillations, or

other anomalies. To guard against such power-up problems, take the following precautions:

1. Connect the ground before any supply voltage is applied.

2. Power up the V_CCAand V_CCBsupplies. The V_CCAand V_CCBsupplies can be ramped in any order.

11 Layout

11.1 Layout Guidelines

To ensure reliability of the device, following common printed-circuit board layout guidelines is recommended:

• Bypass capacitors should be used on power supplies.

• Short trace lengths should be used to avoid excessive loading.

• Placing pads on the signal paths for loading capacitors or pullup resistors to help adjust rise and fall times of

signals depending on the system requirements.

11.2 Layout Example

LEGEND

Polygonal Copper Pour

VIA to Power Plane

VIA to GND Plane (Inner Layer)

V_CCB

V_CCA

GND

V_CCB

DIR

V_CCA

From Controller

To System

图11-1. PCB Layout Example

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

• Texas Instruments, Evaluate SN74AXC1T45DRL Using a Generic EVM application report

• Texas Instruments, Implications of Slow or Floating CMOS Inputs application report

• Texas Instruments, Power Sequencing for the AXC Family of Devices application report

12.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

www.ti.com

24-Sep-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

SN74AXC1T45DBVR

SN74AXC1T45DCKR

SN74AXC1T45DEAR

SN74AXC1T45DRLR

SN74AXC1T45DTQR

ACTIVE

SOT-23

SC70

DBV

DCK

DEA

DRL

DTQ

3000 RoHS & Green

5000 RoHS & Green

4000 RoHS & Green

3000 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-40 to 125

1GRL

1A3

X2SON

SOT-5X3

X2SON

NIPDAU

NIPDAUAG

NIPDAU

1A1

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

24-Sep-2021

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74AXC1T45 :

Automotive : SN74AXC1T45-Q1

•

NOTE: Qualified Version Definitions:

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Jun-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

SN74AXC1T45DBVR

SN74AXC1T45DCKR

SN74AXC1T45DEAR

SOT-23

SC70

DBV

DCK

DEA

DRL

DTQ

3000

5000

4000

3000

180.0

178.0

180.0

8.4

9.0

9.5

8.4

9.5

3.2

2.4

3.2

2.5

1.4

1.2

4.0

2.0

8.0

X2SON

1.13

1.98

0.94

1.13

1.78

1.13

0.5

SN74AXC1T45DRLR SOT-5X3

SN74AXC1T45DTQR X2SON

0.69

0.5

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Jun-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

SN74AXC1T45DBVR

SN74AXC1T45DCKR

SN74AXC1T45DEAR

SN74AXC1T45DRLR

SN74AXC1T45DTQR

SOT-23

SC70

DBV

DCK

DEA

DRL

DTQ

3000

5000

4000

3000

210.0

180.0

189.0

183.0

189.0

185.0

180.0

185.0

183.0

185.0

35.0

18.0

36.0

20.0

36.0

X2SON

SOT-5X3

X2SON

Pack Materials-Page 2

PACKAGE OUTLINE

DBV0006A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

3.0

2.6

0.1 C

1.75

1.45

1.45 MAX

PIN 1

INDEX AREA

2X 0.95

1.9

3.05

2.75

0.50

0.25

C A B

0.15

0.00

0.2

(1.1)

TYP

0.25

GAGE PLANE

0.22

0.08

TYP

0.6

0.3

TYP

SEATING PLANE

4214840/C 06/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.

4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.

5. Refernce JEDEC MO-178.

www.ti.com

EXAMPLE BOARD LAYOUT

DBV0006A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

6X (1.1)

6X (0.6)

SYMM

2X (0.95)

(R0.05) TYP

(2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED METAL

0.07 MIN

ARROUND

0.07 MAX

ARROUND

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4214840/C 06/2021

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DBV0006A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

6X (1.1)

6X (0.6)

SYMM

2X(0.95)

(R0.05) TYP

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

4214840/C 06/2021

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

DEA0006A

X2SON - 0.4 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

1.05

0.95

PIN 1 INDEX AREA

1.05

0.95

0.4 MAX

SEATING PLANE

0.08 C

0.04

0.00

(0.102) TYP

0.55

SYMM

0.35

0.27

SYMM

0.7

0.35

0.20

0.12

PIN 1 ID

45 X 0.075

0.40

0.32

0.1

C B A

0.05

4223910/C 12/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

DEA0006A

X2SON - 0.4 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

5X (0.31)

(0.36)

6X (0.16)

4X (0.35)

(R0.05) TYP

SYMM

(0.55)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:40X

0.05 MIN

ALL AROUND

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4223910/C 12/2017

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

DEA0006A

X2SON - 0.4 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

5X (0.31)

(0.36)

6X (0.16)

4X (0.35)

(R0.05) TYP

SYMM

(0.55)

SOLDER PASTE EXAMPLE

BASED ON 0.075 mm THICK STENCIL

SCALE:40X

4223910/C 12/2017

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE OUTLINE

DRL0006A

SOT - 0.6 mm max height

PLASTIC SMALL OUTLINE

1.7

1.5

PIN 1

ID AREA

4X 0.5

1.7

1.5

2X 1

NOTE 3

1.3

1.1

0.3

0.05

TYP

0.00

0.1

0.6 MAX

SEATING PLANE

0.05 C

0.18

0.08

SYMM

0.27

0.15

0.1

0.05

C A B

0.4

0.2

4223266/C 12/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. Reference JEDEC registration MO-293 Variation UAAD

www.ti.com

EXAMPLE BOARD LAYOUT

DRL0006A

SOT - 0.6 mm max height

PLASTIC SMALL OUTLINE

6X (0.67)

SYMM

6X (0.3)

SYMM

4X (0.5)

(R0.05) TYP

(1.48)

LAND PATTERN EXAMPLE

SCALE:30X

0.05 MIN

AROUND

0.05 MAX

AROUND

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDERMASK DETAILS

4223266/C 12/2021

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

7. Land pattern design aligns to IPC-610, Bottom Termination Component (BTC) solder joint inspection criteria.

www.ti.com

EXAMPLE STENCIL DESIGN

DRL0006A

SOT - 0.6 mm max height

PLASTIC SMALL OUTLINE

6X (0.67)

SYMM

6X (0.3)

SYMM

4X (0.5)

(R0.05) TYP

(1.48)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SCALE:30X

4223266/C 12/2021

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

DTQ0006A

X2SON - 0.4 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

1.05

0.95

PIN 1 INDEX AREA

0.85

0.75

0.40 MAX

(0.1) TYP

SEATING PLANE

0.05 C

(0.1)

2X 0.6

0.4

0.05

0.00

(0.027) TYP

PKG

+0.05

-0.03

0.25

TYP

(0.08)

0.25

0.17

PIN 1 ID

(OPTIONAL)

NOTE 5

PKG

0.30

0.22

0.1

0.05

C A B

4224056/A 11/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pads must be soldered to the printed circuit board for optimal thermal and mechanical performance.

4. The size and shape of this feature may vary.

5. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes.

www.ti.com

EXAMPLE BOARD LAYOUT

DTQ0006A

X2SON - 0.4 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

0.05 MIN

ALL AROUND

TYP

SOLDER MASK OPEING

TYP

SYMM

4X (0.25)

(0.25)

TYP

4X (0.4)

SYMM

(0.8)

(0.2) TYP

EXPOSED METAL

CLEARANCE

METAL UNDER

SOLDER MASK

TYP

(0.2)

TYP

(0.027) TYP

(R0.05) TYP

(0.4)

(0.6)

LAND PATTERN EXAMPLE

SOLDER MASK DEFINED

SCALE:50X

4224056/A 11/2017

NOTES: (continued)

6. This package is designed to be soldered to a thermal pads on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

7. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.

www.ti.com

EXAMPLE STENCIL DESIGN

DTQ0006A

X2SON - 0.4 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

4X (0.25)

SYMM

(0.027) TYP

(0.279)

TYP

4X (0.4)

SYMM

(0.8)

(0.2) TYP

SOLDER MASK

EDGE, 2X

METAL UNDER

SOLDER MASK

TYP

(0.2)

TYP

(R0.05) TYP

(0.21)

(0.367)

4X (0.6)

SOLDER PASTE EXAMPLE

BASED ON 0.07 mm THICK STENCIL

PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:50X

4224056/A 11/2017

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

SN74AXC1T45DCKR [TI]

相关型号：

SN74AXC1T45DEAR

SN74AXC1T45DRLR

SN74AXC1T45DTQR

SN74AXC1T45QDCKRQ1

SN74AXC1T45QDRYRQ1

SN74AXC2T245

SN74AXC2T245-Q1

SN74AXC2T245RSWR

SN74AXC2T45

SN74AXC2T45-Q1

SN74AXC2T45-Q1_V01

SN74AXC2T45DCTR