SN74AVCBH164245KR [TI]
16 BIT DUAL SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3 STATE OUTPUTS; 可配置电压转换和3态输出16位双电源总线收发器型号: | SN74AVCBH164245KR |
厂家: | TEXAS INSTRUMENTS |
描述: | 16 BIT DUAL SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3 STATE OUTPUTS |
文件: | 总13页 (文件大小:292K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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SCES393A − JUNE 2002 − REVISED MAY 2004
D
D
Member of the Texas Instruments
Widebus Family
DOC Circuitry Dynamically Changes
Output Impedance, Resulting in Noise
D
D
I
Supports Partial-Power-Down Mode
off
Operation
Fully Configurable Dual-Rail Design Allows
Each Port to Operate Over the Full 1.4-V to
3.6-V Power-Supply Range
Reduction Without Speed Degradation
Dynamic Drive Capability Is Equivalent to
Standard Outputs With I and I of
D
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
OH
OL
24 mA at 2.5-V V
CC
D
D
D
Control Inputs V /V Levels are
D
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
IH IL
Referenced to V
Voltage
CCB
If Either V
Are in the High-Impedance State
Input Is at GND, Both Ports
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
CC
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
− 1000-V Charged-Device Model (C101)
description/ordering information
This 16-bit (dual-octal) noninverting bus transceiver uses two separate configurable power-supply rails. The
A-port is designed to track V . V accepts any supply voltage from 1.4 V to 3.6 V. The B-port is designed
CCA CCA
to track V
. V
accepts any supply voltage from 1.4 V to 3.6 V. This allows for universal low-voltage
CCB CCB
bidirectional translation between any of the 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.
The SN74AVCBH164245 is designed for asynchronous communication between data buses. The device
transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses are
effectively isolated.
The SN74AVCBH164245 is designed so that the control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by
V
.
CCB
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup
or pulldown resistors with the bus-hold circuitry is not recommended.
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CCB
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down. If either V
both ports are in the high-impedance state.
input is at GND,
CC
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
TSSOP − DGG Tape and reel SN74AVCBH164245GR
AVCBH164245
WBH4245
TVSOP − DGV
VFBGA − GQL
Tape and reel SN74AVCBH164245VR
Tape and reel SN74AVCBH164245KR
−40°C to 85°C
WBH4245
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DOC and Widebus are trademarks of Texas Instruments.
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Copyright 2004, Texas Instruments Incorporated
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1
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SCES393A − JUNE 2002 − REVISED MAY 2004
terminal assignments
DGG OR DGV PACKAGE
(TOP VIEW)
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1B1
1B2
GND
1B3
1B4
1OE
1A1
1A2
GND
1A3
1A4
2
3
4
5
6
7
V
V
CCB
1B5
CCA
8
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
9
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
V
V
CCB
2B5
CCA
2A5
2A6
GND
2A7
2A8
2OE
2B6
GND
2B7
2B8
2DIR
GQL PACKAGE
(TOP VIEW)
terminal assignments
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
1DIR
1B2
1B4
1B6
1B8
2B1
2B3
2B5
2B7
2DIR
NC
NC
GND
NC
NC
1OE
1A2
1A4
1A6
1A8
2A1
2A3
2A5
2A7
2OE
A
B
C
D
1B1
1B3
1B5
1B7
2B2
2B4
2B6
2B8
NC
GND
1A1
1A3
1A5
1A7
2A2
2A4
2A6
2A8
NC
V
CCB
GND
V
CCA
GND
E
F
G
H
J
GND
GND
G
H
J
V
CCB
GND
V
CCA
GND
K
NC
NC
K
NC − No internal connection
2
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ꢗ ꢎ ꢏꢈ ꢆꢘ ꢁꢙ ꢎ ꢚꢑ ꢕ ꢄꢇꢒ ꢖ ꢅꢘ ꢒꢏꢄꢚ ꢖ ꢏ ꢕꢄꢁꢀ ꢒꢄꢏ ꢎꢘ ꢁ ꢄꢁꢐ ꢛ ꢍꢀꢏꢄꢏ ꢖ ꢘ ꢑꢏ ꢓ ꢑꢏꢀ
SCES393A − JUNE 2002 − REVISED MAY 2004
FUNCTION TABLE
(each 8-bit section)
INPUTS
OPERATION
OE
DIR
L
L
L
B data to A bus
A data to B bus
Isolation
H
H
X
logic diagram (positive logic)
24
1
2DIR
1DIR
48
25
1OE
1B1
2OE
36
47
1A1
2A1
13
2
2B1
To Seven Other Channels
To Seven Other Channels
Pin numbers shown are for the DGG and DGV packages.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
and V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
CCA
CCB
Input voltage range, V (see Note 1): I/O ports (A port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
I
I/O ports (B port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1): (A port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
(B port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2): (A port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
(B port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
+ 0.5 V
CCA
CCB
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
O
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous current through V
O
, V
, or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CCA CCB
Package thermal impedance, θ (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
3
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SCES393A − JUNE 2002 − REVISED MAY 2004
recommended operating conditions (see Notes 4 through 6)
V
CCI
V
CCO
MIN
1.4
MAX
3.6
UNIT
V
V
V
Supply voltage
Supply voltage
CCA
1.4
3.6
V
CCB
1.4 V to 1.95 V
1.95 V to 2.7 V
2.7 V to 3.6 V
1.4 V to 1.95 V
1.95 V to 2.7 V
2.7 V to 3.6 V
1.4 V to 1.95 V
1.95 V to 2.7 V
2.7 V to 3.6 V
1.4 V to 1.95 V
1.95 V to 2.7 V
2.7 V to 3.6 V
V
× 0.65
1.7
CCI
High-level input
voltage
V
IH
V
IL
V
IH
V
IL
Data inputs
V
V
V
V
2
V
× 0.35
CCI
Low-level input
voltage
0.7
0.8
Data inputs
V
CCB
× 0.65
1.7
High-level input
voltage
Control inputs
(Referenced to V
)
)
CCB
2
V
CCB
× 0.35
0.7
Low-level input
voltage
Control inputs
(Referenced to V
CCB
0.8
V
V
Input voltage
0
0
0
3.6
V
V
I
Active state
3-state
V
CCO
Output voltage
O
3.6
−2
−4
−8
−12
2
1.4 V to 1.6 V
1.65 V to 1.95 V
2.3 V to 2.7 V
3 V to 3.6 V
I
High-level output current
Low-level output current
mA
mA
OH
OL
1.4 V to 1.6 V
1.65 V to 1.95 V
2.3 V to 2.7 V
3 V to 3.6 V
4
I
8
12
5
∆t/∆v Input transition rise or fall rate
Operating free-air temperature
NOTES: 4. V is the V associated with the data input port.
ns/V
T
A
−40
85
°C
CCI
CCO
CC
CC
5.
V
is the V
associated with the output port.
6. All unused data inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CCI
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢗ ꢎ ꢏꢈ ꢆꢘ ꢁꢙ ꢎ ꢚꢑ ꢕ ꢄꢇꢒ ꢖ ꢅꢘ ꢒꢏꢄꢚ ꢖ ꢏ ꢕꢄꢁꢀ ꢒꢄꢏ ꢎꢘ ꢁ ꢄꢁꢐ ꢛ ꢍꢀꢏꢄꢏ ꢖ ꢘ ꢑꢏ ꢓ ꢑꢏꢀ
SCES393A − JUNE 2002 − REVISED MAY 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Note 7)
†
TYP
PARAMETER
TEST CONDITIONS
MIN
−0.2 V
MAX
UNIT
V
V
CCB
CCA
I
I
I
I
I
I
I
I
I
I
= −100 µA
= −2 mA
= −4 mA
= −8 mA
= −12 mA
= 100 µA
= 2 mA
V = V
1.4 V to 3.6 V
1.4 V
1.4 V to 3.6 V
1.4 V
V
CCO
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
I
IH
IH
IH
IH
IH
IL
IL
IL
IL
IL
V = V
I
1.05
1.2
V = V
I
1.65 V
2.3 V
1.65 V
2.3 V
V
V
OH
V = V
I
1.75
2.3
V = V
I
3 V
3 V
V = V
I
1.4 V to 3.6 V
1.4 V
1.4 V to 3.6 V
1.4 V
0.2
0.35
0.45
0.55
0.7
V = V
I
= 4 mA
V = V
I
1.65 V
2.3 V
1.65 V
2.3 V
V
V
OL
= 8 mA
V = V
I
= 12 mA
V = V
I
3 V
3 V
I
Control inputs V = V
CCB
or GND
1.4 V to 3.6 V
1.4 V
3.6 V
2.5
µA
µA
I
I
V = 0.49 V
I
1.4 V
11
V = 0.57 V
1.65 V
2.3 V
1.65 V
2.3 V
25
45
75
I
‡
I
BHL
V = 0.7 V
I
V = 0.8 V
I
3 V
3 V
V = 0.91 V
I
1.4 V
1.4 V
−11
V = 1.07 V
1.65 V
2.3 V
1.65 V
2.3 V
−25
−45
I
§
I
I
I
µA
µA
BHH
V = 1.7 V
I
V = 2 V
I
3 V
3 V
−75
1.6 V
1.6 V
100
1.95 V
2.7 V
1.95 V
2.7 V
200
¶
V = 0 to V
I CC
BHLO
300
3.6 V
3.6 V
525
1.6 V
1.6 V
−100
−200
−300
−525
1.95 V
2.7 V
1.95 V
2.7 V
#
V = 0 to V
I CC
µA
µA
BHHO
3.6 V
3.6 V
A port
B port
0 V
0 to 3.6 V
0 V
10
10
I
V or V = 0 to 3.6 V
I O
off
0 to 3.6 V
†
‡
All typical values are at T = 25°C.
The bus-hold circuit can sink at least the minimum low sustaining current at V max. I
then raising it to V max.
IL
The bus-hold circuit can source at least the minimum high sustaining current at V min. I
A
should be measured after lowering V to GND and
IN
IL BHL
§
should be measured after raising V to V and
IN CC
IH
BHH
then lowering it to V min.
IH
¶
#
An external driver must source at least I
to switch this node from low to high.
BHLO
to switch this node from high to low.
An external driver must sink at least I
BHHO
associated with the output port.
NOTE 7:
V
CCO
is the V
CC
5
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ꢗꢎ ꢏ ꢈ ꢆ ꢘꢁ ꢙꢎ ꢚꢑ ꢕ ꢄꢇꢒ ꢖ ꢅ ꢘꢒꢏꢄꢚ ꢖ ꢏꢕ ꢄꢁ ꢀꢒ ꢄꢏ ꢎꢘ ꢁ ꢄꢁꢐ ꢛ ꢍꢀꢏꢄꢏ ꢖ ꢘ ꢑꢏ ꢓꢑꢏ ꢀ
SCES393A − JUNE 2002 − REVISED MAY 2004
electrical characteristics over recommended operating free-air temperature range (continued)
(unless otherwise noted) (see Notes 8 and 9)
†
PARAMETER
A or B ports
TEST CONDITIONS
MIN TYP
MAX
12.5
12.5
UNIT
V
V
CCB
CCA
OE = V
3.6 V
0 V
3.6 V
3.6 V
IH
V
= V
or GND,
CCO
or GND
O
‡
B port
A port
µA
I
OZ
V = V
I
CCI
OE = don’t care
3.6 V
1.6 V
1.95 V
2.7 V
0 V
0 V
1.6 V
1.95 V
2.7 V
3.6 V
0 V
12.5
20
20
30
I
V = V
I
or GND,
I
O
= 0
µA
µA
CCA
CCI
−40
40
3.6 V
3.6 V
1.6 V
1.95 V
2.7 V
0 V
3.6 V
1.6 V
1.95 V
2.7 V
3.6 V
0 V
40
20
20
30
I
V = V
I
or GND,
I
O
= 0
CCB
CCI
40
3.6 V
3.6 V
3.3 V
3.3 V
−40
40
3.6 V
3.3 V
3.3 V
C
C
Control inputs V = 3.3 V or GND
4
5
pF
pF
i
I
A or B ports
V
O
= 3.3 V or GND
io
†
‡
All typical values are at T = 25°C.
A
For I/O ports, the parameter I
includes the input leakage current.
associated with the output port.
associated with the input port.
OZ
NOTES: 8. V
is the V
CC
CCO
is the V
9.
V
CCI
CC
switching characteristics over recommended operating free-air temperature range,
V
= 1.5 V 0.1 V (see Figure 2)
CCA
V
= 1.5 V
0.1 V
V
= 1.8 V
0.15 V
V
= 2.5 V
0.2 V
V
= 3.3 V
0.3 V
CCB
CCB
CCB
CCB
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1.7
1.8
2.5
MAX
6.7
MIN
1.9
2.2
2.4
MAX
6.3
MIN
1.8
2.1
2.1
MAX
5.5
MIN
1.7
2.1
1.9
MAX
5.8
A
B
B
A
A
t
t
ns
ns
pd
6.8
7.4
7.6
7.3
8.4
7.4
5.2
4.2
OE
en
B
A
B
2.1
2.2
2.1
9
6.9
7.1
2.9
2.3
2.3
9.8
6.1
6.4
3.2
1.3
1.7
10
3.6
5.1
3
1.3
1.6
9.8
3
OE
OE
OE
t
ns
dis
4.8
6
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ꢉ ꢊ ꢍꢇꢎ ꢏ ꢐꢑꢄ ꢒꢍꢀ ꢑꢓꢓꢒꢔ ꢇꢑꢀ ꢏ ꢕꢄꢁꢀ ꢆꢖ ꢎ ꢅꢖ ꢕ
ꢗ ꢎ ꢏꢈ ꢆꢘ ꢁꢙ ꢎ ꢚꢑ ꢕ ꢄꢇꢒ ꢖ ꢅꢘ ꢒꢏꢄꢚ ꢖ ꢏ ꢕꢄꢁꢀ ꢒꢄꢏ ꢎꢘ ꢁ ꢄꢁꢐ ꢛ ꢍꢀꢏꢄꢏ ꢖ ꢘ ꢑꢏ ꢓ ꢑꢏꢀ
SCES393A − JUNE 2002 − REVISED MAY 2004
switching characteristics over recommended operating free-air temperature range,
V
= 1.8 V 0.15 V (see Figure 2)
CCA
V
= 1.5 V
0.1 V
V
= 1.8 V
0.15 V
V
= 2.5 V
0.2 V
V
= 3.3 V
0.3 V
CCB
CCB
CCB
CCB
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1.7
1.4
2.6
MAX
6.4
MIN
1.8
1.8
2.5
MAX
6
MIN
1.7
1.8
2.2
MAX
4.7
MIN
1.6
1.8
1.9
MAX
4.3
A
B
B
A
A
t
t
ns
ns
pd
5.5
6
5.8
5.5
8.5
7.5
5.3
4.2
OE
OE
OE
OE
en
B
A
B
1.8
2.3
1.8
7.6
7
2.6
2.3
2.5
7.7
6.1
6.3
2.6
1.3
1.8
7.6
3.6
4.7
2.6
1.3
1.7
7.4
3
t
ns
dis
7
4.4
switching characteristics over recommended operating free-air temperature range,
V
= 2.5 V 0.2 V (see Figure 2)
CCA
V
= 1.5 V
0.1 V
V
= 1.8 V
0.15 V
V
= 2.5 V
0.2 V
V
= 3.3 V
0.3 V
CCB
CCB
CCB
CCB
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1.6
1.3
3.1
MAX
6
MIN
1.8
1.7
2.5
MAX
5.6
MIN
1.5
1.5
2.2
MAX
4
MIN
1.4
1.4
1.9
MAX
3.4
A
B
B
A
A
t
t
ns
ns
pd
4.6
8.5
4.4
4
3.7
7.5
5.3
4.2
OE
en
B
A
B
1.7
2.4
1.2
5.7
7
2.2
3
5.5
6.1
5
2.2
1.4
1.4
5.3
3.6
3.6
2.2
1.2
1.3
5.1
3
OE
OE
OE
t
ns
dis
5.8
1.9
3.3
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V 0.3 V (see Figure 2)
CCA
V
= 1.5 V
0.1 V
V
= 1.8 V
0.15 V
V
= 2.5 V
0.2 V
V
= 3.3 V
0.3 V
CCB
CCB
CCB
CCB
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1.5
1.3
2.6
MAX
5.9
MIN
1.7
1.6
2.5
MAX
5.4
MIN
1.5
1.5
2.2
MAX
3.7
MIN
1.4
1.4
1.9
MAX
3.1
A
B
B
A
A
t
t
ns
ns
pd
4.5
3.8
3.3
3.1
8.3
7.4
5.2
4.1
OE
OE
OE
OE
en
B
A
B
1.6
2.3
1.3
4.9
7
2
3
4.5
6
2
1.3
1.6
4.3
3.5
3.8
1.9
1.2
1.5
4.1
3.5
3.5
t
ns
dis
6.9
2.1
5.5
7
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ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈꢉ ꢊ ꢃ ꢋ ꢃ ꢌ
ꢉꢊ ꢍꢇꢎ ꢏ ꢐ ꢑ ꢄꢒ ꢍꢀꢑ ꢓꢓ ꢒꢔ ꢇꢑ ꢀ ꢏꢕ ꢄꢁ ꢀꢆ ꢖꢎ ꢅ ꢖꢕ
ꢗꢎ ꢏ ꢈ ꢆ ꢘꢁ ꢙꢎ ꢚꢑ ꢕ ꢄꢇꢒ ꢖ ꢅ ꢘꢒꢏꢄꢚ ꢖ ꢏꢕ ꢄꢁ ꢀꢒ ꢄꢏ ꢎꢘ ꢁ ꢄꢁꢐ ꢛ ꢍꢀꢏꢄꢏ ꢖ ꢘ ꢑꢏ ꢓꢑꢏ ꢀ
SCES393A − JUNE 2002 − REVISED MAY 2004
operating characteristics, V
and V
= 3.3 V, T = 25°C
CCA
CCB
A
PARAMETER
TEST CONDITIONS
TYP
14
7
UNIT
Outputs enabled
Outputs disabled
Outputs enabled
Outputs disabled
Outputs enabled
Outputs disabled
Outputs enabled
Outputs disabled
Power dissipation capacitance per transceiver,
A port input, B port output
C
(V
pdA
CCA
C
C
= 0,
= 0,
f = 10 MHz
f = 10 MHz
pF
L
L
)
20
7
Power dissipation capacitance per transceiver,
B port input, A port output
20
7
Power dissipation capacitance per transceiver,
A port input, B port output
C
pdB
pF
(V
CCB
)
14
7
Power dissipation capacitance per transceiver,
B port input, A port output
output description
The DOC circuitry is implemented, which, during the transition, initially lowers the output impedance to
effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical V
OL
vs I
and V
vs I
curves to illustrate the output impedance and drive capability of the circuit. At the
OL
OH
OH
beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a
high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family
Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC) Circuitry
Technology and Applications, literature number SCEA009.
3.2
T
= 25°C
T
= 25°C
A
A
Process = Nominal
Process = Nominal
2.8
2.4
2.0
2.8
2.4
2.0
V
= 3.3 V
CC
1.6
1.2
0.8
0.4
1.6
1.2
0.8
0.4
V
= 2.5 V
CC
V
= 1.8 V
CC
V
= 3.3 V
V
= 2.5 V
CC
CC
V
= 1.8 V
CC
−160 −144 −128 −112 −96 −80 −64 −48 −32 −16
− Output Current − mA
0
17
34
51
68
85 102 119 136 153 170
0
I
− Output Current − mA
I
OH
OL
Figure 1. Typical Output Voltage vs Output Current
8
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ꢗ
ꢎ
ꢏ
ꢈ
ꢆ
ꢘ
ꢁ
ꢙ
ꢎ
ꢚꢑ
ꢕ
ꢄ
ꢇ
ꢒ
ꢖ
ꢅ
ꢘ
ꢒ
ꢏ
ꢄ
ꢚ
ꢖ
ꢏ
ꢕ
ꢄ
ꢁ
ꢀ
ꢒꢄꢏ
ꢎ
ꢘ
ꢁ
ꢄ
ꢁ
ꢐ
ꢛ
ꢍ
ꢀ
ꢏ
ꢄ
ꢏ
ꢖ
ꢘ
ꢑ
ꢏ
ꢓ
ꢑ
ꢏ
ꢀ
SCES393A − JUNE 2002 − REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION
2 × V
CCO
TEST
S1
S1
R
Open
GND
t
Open
L
pd
/t
From Output
Under Test
t
2 × V
CCO
GND
PLZ PZL
/t
PHZ PZH
t
C
L
R
L
(see Note A)
t
LOAD CIRCUIT
w
V
CCI
V /2
CCI
V /2
CCI
Input
V
TP
C
R
V
CCO
L
L
0 V
1.5 V 0.1 V
1.8 V 0.15 V
2.5 V 0.2 V
3.3 V 0.3 V
2 kΩ
1 kΩ
500 Ω
500 Ω
0.1 V
0.15 V
0.15 V
0.3 V
15 pF
30 pF
30 pF
30 pF
VOLTAGE WAVEFORMS
PULSE DURATION
V
CCB
Output
Control
(low-level
enabling)
V
CCB
/2
V
CCB
/2
0 V
t
t
PLZ
PZL
V
V
CCO
Output
Waveform 1
V
CCI
V
CCO
/2
/2
Input
t
V /2
CCI
V /2
CCI
V
+ V
OL
TP
S1 at 2 × V
CCO
OL
0 V
(see Note B)
t
PZH
t
t
PHZ
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
OH
V
OH
− V
TP
V
CCO
Output
V
CCO
/2
V
/2
CCO
(see Note B)
0 V
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, Z = 50 Ω, dv/dt ≥ 1 V/ns,
O
dv/dt ≥1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
H.
I.
t
t
t
V
V
and t
and t
are the same as t
.
.
PLZ
PZL
PLH
PHZ
PZH
dis
are the same as t
are the same as t .
en
and t
PHL
is the V
pd
associated with the input port.
associated with the output port.
CC
CCI
CC
is the V
CCO
Figure 2. Load Circuit and Voltage Waveforms
9
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MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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