SN74AUP1T34-Q1 [TI]
1 位单向电压电平转换器，SN74AUP1T34-Q1;
| 型号： | SN74AUP1T34-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1 位单向电压电平转换器，SN74AUP1T34-Q1 转换器 电平转换器 |
| 文件： | 总19页 (文件大小：687K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SN74AUP1T34-Q1
ZHCSEZ0A –DECEMBER 2013–REVISED APRIL 2016
SN74AUP1T34-Q1 1 位单向电压电平转换器
1 特性
2 应用范围
1
•
适用于汽车电子 应用
•
•
•
•
•
汽车
企业
–
–
符合 AEC-Q100 标准
工业
器件温度等级 1：-40°C 至 125°C 的环境运行
温度范围
个人电子产品
电信
–
器件人体放电模式 (HBM) 静电放电 (ESD) 分类
等级 3A
3 说明
–
带电器件模型 (CDM) ESD 分类等级 C5
•
•
0.9V 至 3.6V 的宽运行 VCC 范围
SN74AUP1T34-Q1 器件是一款 1 位非反向转换器，使
用两条独立的可配置电源轨。该单向转换器在 A 和 B
两端口间转换。A 端口设计用于跟踪 VCCA。VCCA可接
受从 0.9V 到 3.6V 范围内的电源电压。B 端口设计用
于跟踪 VCCB。VCCB可接受从 0.9V 至 3.6V 间的电源电
压值。这可实现 1V，1.2V，1.5V，1.8V，2.5V 和
3.3V 电压节点间的低压转换。此外，SN74AUP1T34-
Q1 完全 适用于 使用 Ioff 的局部掉电应用。Ioff 电路会
禁用输出，从而在器件掉电时防止电流回流损坏器件。
均衡的传播延迟：tPLH = tPHL
（1.8V 至 3.3V 转换时的典型值）
•
•
•
•
低静态功耗：ICC 最高为 5µA
±6mA 输出驱动（电压为 3V 时）
Ioff 支持部分掉电模式运行
VCC 隔离特性 – 如果 VCCA 输入接地，则 B 端口
处于高阻态
•
输入滞后可实现输入转换和输入上更好的开关噪声
抗扰度
VCC 隔离特性确保了在 VCCA输入在 GND 上时，B 端
口处于高阻抗状态。如果 VCCB输入在 GND 上，到 A
侧的任一输入都不会导致泄漏电流，即使在悬空状态时
也是如此。
•
•
•
静电放电 (ESD) 保护性能超过 JESD 22 规范要求
5000V 人体模型 (AEC-Q100-002-E)
锁存性能满足
100mA，符合 Q100-004-D 规范
器件信息(1)
器件型号
封装
SC70 (5)
封装尺寸（标称值）
SN74AUP1T34-Q1
2.00mm × 1.25mm
(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。
示例应用图
Camera Module 1
Camera Module 2
Camera Module 3
ADAS Host
Processor
SN74AUP1T34-Q1
Control Output
To Multiple Loads
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SCES852
SN74AUP1T34-Q1
ZHCSEZ0A –DECEMBER 2013–REVISED APRIL 2016
www.ti.com.cn
目录
8.3 Feature Description................................................... 7
8.4 Device Functional Modes.......................................... 7
Application and Implementation .......................... 8
9.1 Application Information.............................................. 8
9.2 Typical Application ................................................... 8
1
2
3
4
5
6
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 3
6.1 Absolute Maximum Ratings ...................................... 3
6.2 ESD Ratings.............................................................. 3
6.3 Recommended Operating Conditions ...................... 4
6.4 Thermal Information.................................................. 4
6.5 AC Electrical Characteristics..................................... 5
6.6 Typical Characteristics.............................................. 6
Parameter Measurement Information .................. 6
Detailed Description .............................................. 7
8.1 Overview ................................................................... 7
8.2 Functional Block Diagram ......................................... 7
9
10 Power Supply Recommendations ....................... 9
11 Layout................................................................... 10
11.1 Layout Guidelines ................................................. 10
11.2 Layout Example .................................................... 10
12 器件和文档支持 ..................................................... 11
12.1 社区资源................................................................ 11
12.2 商标....................................................................... 11
12.3 静电放电警告......................................................... 11
12.4 Glossary................................................................ 11
13 机械、封装和可订购信息....................................... 11
7
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (December 2013) to Revision A
Page
•
•
已添加 ESD 额定值表，特性 描述部分，器件功能模式，应用和实施部分，电源相关建议部分，布局部分，器件和文
档支持部分以及机械、封装和可订购信息部分。 .................................................................................................................... 1
已删除订购信息表................................................................................................................................................................... 1
2
Copyright © 2013–2016, Texas Instruments Incorporated
SN74AUP1T34-Q1
www.ti.com.cn
ZHCSEZ0A –DECEMBER 2013–REVISED APRIL 2016
5 Pin Configuration and Functions
DCK Package
5-Pin SC70
Top View
V
ꢀ
1
2
3
5
4
V
B
CCA
A
CCB
GND
Pin Functions
PIN
I/O
DESCRIPTION
NAME
A
NO.
2
I
Input Port. Referenced to VCCA
.
B
4
O
Output Port. Referenced to VCCB.
Ground.
GND
VCCA
VCCB
3
—
—
—
1
Input Port DC Power Supply.
Output Port DC Power Supply.
5
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
V
VCCA
VCCB
,
Supply voltage
–0.3
4
VI
Input voltage
–0.5
–0.5
–0.5
4.6
4.6
V
Voltage applied to any output in the high-impedance or power-off state
Voltage applied to any output in the high or low state
VO
V
4.6
IIK
IOK
IO
Input clamp current
VI < 0
–50
–50
±50
±100
150
mA
mA
mA
mA
°C
Output clamp current
Continuous output current
VO < 0
Continuous current through VCCA or GND
Storage temperature
Tstg
–65
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1), Classification 3A
5000
Electrostatic
V(ESD)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Classification C5
,
V
discharge
750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2013–2016, Texas Instruments Incorporated
3
SN74AUP1T34-Q1
ZHCSEZ0A –DECEMBER 2013–REVISED APRIL 2016
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCCA
VCCB
MIN
MAX
UNIT
VCCA
VCCB
,
Supply voltage
0.9
3.6
V
0.9 V to 1.95 V 0.9 V to 1.95 V
0.65 × VCCA
VIH
High-level input voltage
Low-level input voltage
2.3 V to 2.7 V
3 V to 3.6 V
0.9 V
0.9 V to 3.6 V
0.9 V to 3.6 V
0.9 V to 1.95 V
0.9 V to 1.95 V
0.9 V to 3.6 V
0.9 V to 3.6 V
1.6
2
V
V
0.3 × VCCA
0.35 × VCCA
0.7
1 V to 1.95 V
2.3 V to 2.7 V
3 V to 3.6 V
VIL
0.9
Input transition rise or fall
rate
Δt/Δv
3 V to 3.6 V
0.9 V to 3.6 V
200
125
ns/V
°C
Operating free-air
temperature
TA
–40
IOH = –100 µA
0.9 V to 3.6 V
0.9 V to 1 V
1.2 V
0.9 V to 3.6 V
0.9 V to 1 V
1.2 V
VCCB – 0.2
IOH = –0.25 mA
IOH = –1.5 mA
IOH = –2 mA
IOH = –3 mA
IOH = –6 mA
IOL = 100 µA
IOL = 0.25 mA
IOL = 1.5 mA
IOL = 2 mA
0.75 × VCCB
1
1.32
1.9
VOH
VI = VIH
V
1.65 V
1.65 V
2.3 V
2.3 V
3 V
3 V
2.72
0.9 V to 3.6 V
0.9 V to 1 V
1.2 V
0.9 V to 3.6 V
0.9 V 1 V
1.2 V
0.1
0.1
0.3 × VCCB
VOL
VI = VIL
V
1.65 V
1.65 V
0.31
0.31
0.31
±1
±5
±5
2.7
2
IOL = 3 mA
2.3 V
2.3 V
IOL = 6 mA
3 V
3 V
II
Control inputs
A or B port
VI = VCCA or GND
0.9 V to 3.6 V
0 V
0.9 V to 3.6 V
0 V to 3.6 V
0 V
µA
µA
Ioff
VI or VO = 0 to 3.6 V
0 V to 3.6 V
0.9 V to 3.6 V
0.9 V to 3.6 V
0 V
0.9 V to 3.6 V
VCCA
ICCA
VI = VCCI or GND, IO = 0 mA
µA
µA
0 V to 3.6 V
0 V
1
0 V to 3.6 V
0.9 V to 3.6 V
0.9 V to 3.6 V
0 V
1
0.9 V to 3.6 V
VCCA
2.7
2
ICCB
VI = VCCI or GND, IO = 0 mA
VI = VCCI or GND, IO = 0 mA
0 V to 3.6 V
0 V
1
0 V to 3.6 V
0.9 V to 3.6 V
3.3 V
1
ICCA + ICCB
Cio
0.9 V to 3.6 V
3.3 V
5.4
4
µA
pF
A or B port
6.4 Thermal Information
SN74AUP1T34-Q1
THERMAL METRIC(1)
DCK (SC70)
5 PINS
301.9
113
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
79.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
3.9
ψJB
78.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
Copyright © 2013–2016, Texas Instruments Incorporated
SN74AUP1T34-Q1
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ZHCSEZ0A –DECEMBER 2013–REVISED APRIL 2016
6.5 AC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
VCCB = 0.9 V
VCCB = 1.2 V
VCCB = 1.65 V
VCCB = 2.3 V
VCCB = 3 V
PARAMETER
CL
VCCA
UNIT
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
5 pF
0.9 V
1.2 V
1.65 V
2.3 V
3 V
25
18
16.2
16.3
16.8
5 pF
42.5
40
24.9
10.7
8.02
7.61
23.2
8.84
5.73
4.5
22.6
8.08
4.92
3.65
22.5
7.88
4.2
tPLH/tPHL
5 pF
ns
5 pF
41.3
42.5
5 pF
3.39
10 pF
10 pF
10 pF
10 pF
10 pF
15 pF
15 pF
15 pF
15 pF
15 pF
30 pF
30 pF
30 pF
30 pF
30 pF
0.9 V
1.2 V
1.65 V
2.3 V
3 V
28.9
30.6
32.1
19.8
21.6
21.3
17.9
19.6
18.7
18
19.7
18
18.5
20.3
18.3
43.22
40.44
41.56
42.81
12.33
9.21
8.3
9.57
6.57
5.54
4.8
8.81
5.6
8.61
4.73
4.07
3.36
tPLH/tPHL
tPLH/tPHL
tPLH/tPHL
ns
ns
ns
4.42
3.8
7.87
0.9 V
1.2 V
1.65 V
2.3 V
3 V
43.87
40.78
41.79
43.09
16.2
14.7
14.9
16.2
11.8
8.8
11
7.1
11
6.4
7.6
5.88
5.4
5.27
4.7
6.98
0.9 V
1.2 V
1.65 V
2.3 V
3 V
45.65
41.72
42.44
43.69
15.1
12.18
12.35
11.6
12.37
8.15
7.25
6.92
11.61
6.94
5.55
4.95
11.41
6.1
4.97
4.35
VIH
Vm
tPLH
Vm
Input (An)
0 V
tPLH
Vm
VOH
Vm
Output(Bn)
VOL
VMI =VIH/2; VMO= VCCB/2
tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
Figure 1. Waveform 1 - Propagation Delays
Copyright © 2013–2016, Texas Instruments Incorporated
5
SN74AUP1T34-Q1
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6.6 Typical Characteristics
0.600
0.500
0.400
0.300
0.200
0.100
0.000
VCCB = 1.0V
VCCB = 1.2V
VCCB = 1.5V
VCCB = 1.8V
VCCB = 2.5V
VCCB = 3.3V
0.00
5.00
10.00
15.00
20.00
25.00
30.00
Low Level Output Current [mA] with VIL = 0V
C001
Figure 2. Low Level Output Voltage vs Low Level Output Current
7 Parameter Measurement Information
VCC
Pulse
DUT
Generator
CL
RL
TEST
tPLH, tPHL
CL = 5 pF, 10 pF, 15 pF, 30 pF or equivalent (includes probe and jig capacitance)
RL = 1 MΩ or equivalent
ZOUT of pulse generator = 50 Ω
Figure 3. AC (Propagation Delay) Test Circuit
6
Copyright © 2013–2016, Texas Instruments Incorporated
SN74AUP1T34-Q1
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ZHCSEZ0A –DECEMBER 2013–REVISED APRIL 2016
8 Detailed Description
8.1 Overview
The SN74AUP1T34-Q1 is a unidirectional, single-bit, dual-supply, noninverting voltage-level translator. Pin A,
which is referenced to VCCA, receives the signal that is to be level translated. Pin B, which is referenced to VCCB
,
transmits the level translated signal. Both supply pins VCCA and VCCB support a voltage range from 0.9 V to
3.6 V.
8.2 Functional Block Diagram
VCCA
VCCB
2
4
A
B
Copyright © 2016, Texas Instruments Incorporated
8.3 Feature Description
8.3.1 Fully Configurable Dual-Rail Design
Both VCCA and VCCB can be supplied at any voltage from 0.9 V to 3.6 V, making the device suitable for translating
between any of the voltage nodes (1 V, 1.2 V, 1.8 V, 2.5 V, and 3.3 V).
8.3.2 Partial-Power-Down Mode Operation
Ioff circuitry disables the outputs, preventing damaging current backflow through the SN74AUP1T34-Q1 when it is
powered down. This can occur in applications where subsections of a system are powered down (partial-power-
down) to reduce power consumption.
8.3.3 VCC Isolation
The VCC isolation feature ensures that if either VCCA or VCCB are at GND (or < 0.4 V), both ports A and B are set
to a high-impedance state, preventing false logic levels from being presented to either bus.
8.3.4 Input Hysteresis
Input hysteresis allows the input to support slew rates as slow as 200 ns/V, improving switching noise immunity.
8.4 Device Functional Modes
Table 1 lists the functional modes of the SN74AUP1T34-Q1.
Table 1. Function Table
INPUT
OUTPUT
A PORT
B PORT
L
L
H
H
Copyright © 2013–2016, Texas Instruments Incorporated
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SN74AUP1T34-Q1
ZHCSEZ0A –DECEMBER 2013–REVISED APRIL 2016
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74AUP1T34-Q1 can be used in level-translation applications for interfacing devices or systems operating
at different interface voltages with one another.
9.2 Typical Application
1.0V
3.3V
1.0 µF
0.1 µF
0.1 µF
1.0 µF
VCCA
VCCB
VDD (1.0V)
VDD (3.3V)
1.0V Controller
SN74AUP1T34-Q1
3.3V System
Signal
A
B
Signal
GND
GND
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 4. Typical Application Example
9.2.1 Design Requirements
Table 2 lists the design requirements of the SN74AUP1T34-Q1.
Table 2. Design Parameters
DESIGN PARAMETER
Input Voltage Range
Output Voltage Range
EXAMPLE VALUE
0.9 V to 3.6 V
0.9 V to 3.6 V
9.2.2 Detailed Design Procedure
To begin the design process, determine the following:
•
Input voltage range
–
Use the supply voltage of the device that is driving the SN74AUP1T34-Q1 device to determine the input
voltage range. For a valid logic-high, the value must exceed the VIH of the input port. For a valid logic low
the value must be less than the VIL of the input port.
•
Output voltage range
–
Use the supply voltage of the device that the SN74AUP1T34-Q1 device is driving to determine the output
voltage range.
8
Copyright © 2013–2016, Texas Instruments Incorporated
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ZHCSEZ0A –DECEMBER 2013–REVISED APRIL 2016
9.2.3 Application Curve
Figure 5. 10 MHz Up Translation (0.9 V to 3.6 V)
10 Power Supply Recommendations
Connect ground before applying either VCCA or VCCB. There is no specific power sequence requirement for the
SN74AUP1T34. VCCA or VCCB may be powered up first, and VCCA or VCCB may be powered down first.
Copyright © 2013–2016, Texas Instruments Incorporated
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SN74AUP1T34-Q1
ZHCSEZ0A –DECEMBER 2013–REVISED APRIL 2016
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
To ensure reliability of the device, TI recommends following common printed-circuit board layout guidelines.
•
•
•
Bypass capacitors must be used on power supplies.
Short trace lengths must be used to avoid excessive loading.
Placing pads on the signal paths for loading capacitors or pullup resistors helps adjust rise and fall times of
signals depending on the system requirements.
11.2 Layout Example
LEGEND
Polygonal Copper Pour
VIA to Power Plane (Inner Layer)
VIA to GND Plane (Inner Layer)
Bypass Capacitor
Bypass Capacitor
VCCA
VCCB
1
2
3
5
4
A
From Source
GND
B
To Destination
SN74AUP1T34-Q1DCK
(Top View)
Figure 6. Example Layout
10
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SN74AUP1T34-Q1
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ZHCSEZ0A –DECEMBER 2013–REVISED APRIL 2016
12 器件和文档支持
12.1 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.2 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
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11
PACKAGE OPTION ADDENDUM
www.ti.com
22-Aug-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN74AUP1T34QDCKRQ1
ACTIVE
SC70
DCK
5
3000 RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(U4E, U4J)
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74AUP1T34-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
22-Aug-2022
Catalog : SN74AUP1T34
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74AUP1T34QDCKRQ1 SC70
SN74AUP1T34QDCKRQ1 SC70
DCK
DCK
5
5
3000
3000
178.0
178.0
9.0
9.0
2.4
2.4
2.5
2.5
1.2
1.2
4.0
4.0
8.0
8.0
Q3
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74AUP1T34QDCKRQ1
SN74AUP1T34QDCKRQ1
SC70
SC70
DCK
DCK
5
5
3000
3000
190.0
180.0
190.0
180.0
30.0
18.0
Pack Materials-Page 2
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
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