SN74AHC16540DGG [TI]
16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS; 16位缓冲器/驱动器，具有三态输出
| 型号： | SN74AHC16540DGG |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS |
| 文件： | 总7页 (文件大小：118K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54AHC16540, SN74AHC16540
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS331F – MARCH 1996 – REVISED JANUARY 2000
SN54AHC16540 . . . WD PACKAGE
SN74AHC16540 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
EPIC (Enhanced-Performance Implanted
CMOS) Process
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE1
1Y1
1OE2
1A1
Operating Range 2-V to 5.5-V V
CC
2
3
1Y2
1A2
Distributed V
High-Speed Switching Noise
and GND Pins Minimize
CC
4
GND
1Y3
GND
1A3
5
Flow-Through Architecture Optimizes PCB
Layout
6
1Y4
1A4
7
V
V
CC
CC
Latch-Up Performance Exceeds 250 mA Per
JESD 17
8
1Y5
1Y6
GND
1Y7
1Y8
2Y1
2Y2
GND
2Y3
2Y4
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
9
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
V
V
CC
CC
description
2Y5
2Y6
GND
2Y7
2Y8
2A5
2A6
GND
2A7
2A8
These 16-bit buffers and bus drivers provide a
high-performance bus interface for wide data
paths.
The 3-state control gate is a 2-input AND gate with
active-low inputs so that if either output-enable
(OE1 or OE2) input is high, all corresponding
outputs are in the high-impedance state.
2OE1
2OE2
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54AHC16540 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74AHC16540 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 8-bit buffer/driver)
INPUTS
OUTPUT
Y
A
L
OE1
L
OE2
L
H
L
L
L
H
X
X
H
X
Z
Z
X
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 2000, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHC16540, SN74AHC16540
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS331F – MARCH 1996 – REVISED JANUARY 2000
†
logic symbol
1
1OE1
&
&
48
EN1
EN2
1OE2
24
2OE1
25
2OE2
47
1A1
46
2
3
1Y1
1Y2
1Y3
1Y4
1Y5
1Y6
1Y7
1Y8
2Y1
2Y2
2Y3
2Y4
2Y5
2Y6
2Y7
2Y8
1
1
1A2
44
5
1A3
43
6
1A4
41
8
1A5
40
9
1A6
38
11
12
13
14
16
17
19
20
22
23
1A7
37
1A8
36
2A1
35
1
2
2A2
33
2A3
32
2A4
30
2A5
29
2A6
27
2A7
26
2A8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
24
25
1
1OE1
2OE1
2OE2
48
1OE2
36
13
47
2
2Y1
1A1
1Y1
2A1
To Seven Other Channels
To Seven Other Channels
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHC16540, SN74AHC16540
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS331F – MARCH 1996 – REVISED JANUARY 2000
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
IK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through each V
Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
O
O
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±75 mA
CC
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
SN54AHC16540 SN74AHC16540
UNIT
MIN
2
MAX
MIN
2
MAX
V
V
Supply voltage
5.5
5.5
V
CC
V
V
V
V
V
V
= 2 V
1.5
2.1
3.85
1.5
2.1
3.85
CC
CC
CC
CC
CC
CC
High-level input voltage
= 3 V
V
V
IH
= 5.5 V
= 2 V
0.5
0.9
0.5
0.9
V
IL
Low-level input voltage
= 3 V
= 5.5 V
1.65
5.5
1.65
5.5
V
V
Input voltage
0
0
0
0
V
V
A
I
Output voltage
V
V
CC
O
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
–50
–4
–8
50
4
–50
–4
–8
50
4
I
High-level output current
Low-level output current
= 3.3 V ± 0.3 V
= 5 V ± 0.5 V
= 2 V
OH
OL
mA
A
I
= 3.3 V ± 0.3 V
= 5 V ± 0.5 V
= 3.3 V ± 0.3 V
= 5 V ± 0.5 V
mA
8
8
100
20
125
100
20
85
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
T
A
–55
–40
°C
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHC16540, SN74AHC16540
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS331F – MARCH 1996 – REVISED JANUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
TYP
2
SN54AHC16540 SN74AHC16540
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
1.9
MAX
MIN
1.9
MAX
MIN
1.9
MAX
2 V
3 V
I
= –50
A
2.9
3
2.9
2.9
OH
V
V
4.5 V
3 V
4.4
4.5
4.4
4.4
V
OH
OL
I
I
= –4 mA
= –8 mA
2.58
3.94
2.48
3.8
2.48
3.8
OH
4.5 V
2 V
OH
0.1
0.1
0.1
0.1
0.1
0.5
0.5
±1*
0.1
0.1
I
= 50
A
3 V
OL
4.5 V
3 V
0.1
0.1
V
I
I
= 4 mA
= 8 mA
0.36
0.36
±0.1
0.44
0.44
±1
OL
4.5 V
0 V to 5.5 V
OL
I
I
V = V
or GND
A
A
I
CC
= V
V
or GND,
O
I
CC
V (OE) = V or V
IH
5.5 V
±0.25
±2.5
±2.5
I
OZ
CC
IL
I
V = V
or GND,
or GND
I = 0
O
5.5 V
5 V
4
40
40
10
A
pF
pF
I
CC
CC
C
C
V = V
2
3
10
i
I
V
= V or GND
CC
5 V
o
O
* On products compliant to MIL-PRF-38535, this parameter is not production tested at V
CC
= 0 V.
switching characteristics over recommended operating free-air temperature range,
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
SN54AHC16540 SN74AHC16540
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
ns
MIN
MAX
8.4**
8.4**
MIN
1**
MAX
10**
10**
MIN
1
MAX
10
t
t
t
t
t
t
t
t
t
t
t
t
t
4.8**
4.8**
PLH
PHL
PZH
PZL
PHZ
PLZ
PLH
PHL
PZH
PZL
PHZ
PLZ
sk(o)
A
Y
Y
Y
Y
Y
Y
C
C
C
C
C
= 15 pF
= 15 pF
= 15 pF
= 50 pF
= 50 pF
L
L
L
L
L
1**
1
10
6.8** 10.6**
6.8** 10.6**
6.8** 11.5**
6.8** 11.5**
1** 12.5**
1** 12.5**
1** 12.5**
1** 12.5**
1
12.5
12.5
12.5
12.5
12.5
12.5
16
ns
OE
OE
A
1
1
ns
1
7.7
7.3
9.7
7.1
9.4
9.7
11
11
1
1
1
1
1
1
12.5
12.5
16
1
ns
1
14.1
14.1
14
1
ns
OE
OE
16
1
16
16
1
16
C
C
= 50 pF
= 50 pF
ns
ns
L
L
14
16
1
16
1.5***
1.5
** On products compliant to MIL-PRF-38535, this parameter is not production tested.
*** On products compliant to MIL-PRF-38535, this parameter does not apply.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHC16540, SN74AHC16540
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS331F – MARCH 1996 – REVISED JANUARY 2000
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
3.7*
3.7*
4.7*
4.7*
4.5*
4.5*
5.2
SN54AHC16540 SN74AHC16540
UNIT
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
MIN
MAX
6*
MIN
1*
1*
1*
1*
1*
1*
1
MAX
MIN
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
7*
1
7
PLH
PHL
PZH
PZL
PHZ
PLZ
PLH
PHL
PZH
PZL
PHZ
PLZ
sk(o)
A
Y
Y
Y
Y
Y
Y
C
C
C
C
C
= 15 pF
= 15 pF
= 15 pF
= 50 pF
= 50 pF
ns
ns
ns
ns
ns
L
L
L
L
L
6*
7*
1
7
7.3*
7.3*
7.2*
7.2*
8
8.5*
8.5*
8.5*
8.5*
9
1
8.5
8.5
8.5
8.5
8.5
8.5
10.5
10.5
10.5
10.5
1
OE
OE
A
1
1
1
1
5.2
8
1
9
1
6.2
9.3
9.3
9.2
9.2
1
10.5
10.5
10.5
10.5
1
OE
OE
6.2
1
1
6
1
1
C
C
= 50 pF
= 50 pF
ns
ns
L
L
6
1
1
**
1
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
** On products compliant to MIL-PRF-38535, this parameter does not apply.
noise characteristics, V
= 5 V, C = 50 pF, T = 25°C (see Note 4)
CC
L
A
SN74AHC16540
PARAMETER
UNIT
MIN
TYP
0.6
MAX
V
V
V
V
V
Quiet output, maximum dynamic V
V
V
V
V
V
OL(P)
OL(V)
OH(V)
IH(D)
IL(D)
OL
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
–0.3
4.7
OL
OH
3.5
1.5
NOTE 4: Characteristics are for surface-mount packages only.
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
No load, f = 1 MHz
TYP
UNIT
C
Power dissipation capacitance
13
pF
pd
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHC16540, SN74AHC16540
16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS331F – MARCH 1996 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
GND
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
t
t
/t
Open
PLH PHL
/t
C
C
L
t
V
CC
L
PLZ PZL
/t
(see Note A)
(see Note A)
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
CC
Timing Input
0 V
t
w
t
h
t
su
V
CC
V
CC
50% V
50% V
CC
Input
CC
50% V
50% V
CC
Data Input
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
50% V
50% V
50% V
50% V
t
Input
CC
CC
CC
CC
0 V
0 V
t
PZL
t
t
t
PLZ
PLH
PHL
Output
Waveform 1
V
OH
≈V
CC
In-Phase
Output
50% V
50% V
CC
50% V
CC
CC
V
S1 at V
(see Note B)
V
OL
+ 0.3 V
CC
V
OL
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
V
OH
OH
Out-of-Phase
Output
V
OH
– 0.3 V
50% V
50% V
50% V
CC
CC
CC
V
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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Copyright 2000, Texas Instruments Incorporated
相关型号：
SN74AHC16540DLR
AHC/VHC/H/U/V SERIES, DUAL 8-BIT DRIVER, INVERTED OUTPUT, PDSO48, GREEN, PLASTIC, SSOP-48
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