SN74AC00PWR [TI]
QUADRUPLE 2-INPUT POSITIVE-NAND GATES; 四路2输入正与非门型号: | SN74AC00PWR |
厂家: | TEXAS INSTRUMENTS |
描述: | QUADRUPLE 2-INPUT POSITIVE-NAND GATES |
文件: | 总14页 (文件大小:517K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢆꢇ ꢀꢁ ꢈꢃ ꢄꢅ ꢆꢆ
ꢉ ꢊꢄꢋꢌ ꢊꢍꢎ ꢏ ꢐ ꢑꢒꢁ ꢍꢊꢓ ꢍꢔ ꢀꢒ ꢓ ꢒꢕꢏ ꢑꢁꢄꢁ ꢋ ꢖ ꢄꢓꢏ ꢀ
SCAS524E − AUGUST 1995 − REVISED OCTOBER 2003
D
D
D
2-V to 6-V V
Operation
CC
Inputs Accept Voltages to 6 V
Max t of 7 ns at 5 V
pd
SN54AC00 . . . FK PACKAGE
(TOP VIEW)
SN54AC00 . . . J OR W PACKAGE
SN74AC00 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
1A
1B
1Y
2A
2B
V
CC
3
2
1
20 19
18
4B
4A
4Y
3B
3A
3Y
1Y
NC
2A
4A
4
5
6
7
8
NC
17
16 4Y
15
14
NC
2B
NC
3B
2Y
GND
9 10 11 12 13
8
NC − No internal connection
description/ordering information
The ‘AC00 devices contain four independent 2-input NAND gates. Each gate performs the Boolean function
of Y = A S B or Y = A + B in positive logic.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
SOIC − D
Tube
SN74AC00N
SN74AC00N
Tube
SN74AC00D
AC00
Tape and reel
Tape and reel
Tape and reel
Tube
SN74AC00DR
SN74AC00NSR
SN74AC00DBR
SN74AC00PW
SN74AC00PWR
SNJ54AC00J
SNJ54AC00W
SNJ54AC00FK
SOP − NS
AC00
AC00
−40°C to 85°C
SSOP − DB
TSSOP − PW
AC00
Tape and reel
Tube
CDIP − J
CFP − W
LCCC − FK
SNJ54AC00J
SNJ54AC00W
SNJ54AC00FK
Tube
−55°C to 125°C
Tube
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
Y
A
B
H
X
L
H
L
L
H
H
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
ꢔ ꢘ ꢣ ꢛ ꢚꢦ ꢡꢠ ꢞꢟ ꢠꢚ ꢜꢣ ꢥꢗ ꢝꢘ ꢞ ꢞꢚ ꢭꢒ ꢎꢑ ꢍꢌ ꢮ ꢑꢯꢰꢂ ꢯꢂꢇ ꢝꢥꢥ ꢣꢝ ꢛ ꢝ ꢜꢢ ꢞꢢꢛ ꢟ ꢝ ꢛ ꢢ ꢞꢢ ꢟꢞꢢ ꢦ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢆ ꢇ ꢀꢁ ꢈ ꢃ ꢄꢅꢆ ꢆ
ꢉꢊ ꢄ ꢋꢌ ꢊ ꢍꢎ ꢏ ꢐ ꢑꢒ ꢁꢍ ꢊꢓ ꢍ ꢔꢀ ꢒ ꢓꢒ ꢕ ꢏꢑ ꢁꢄꢁ ꢋ ꢖ ꢄꢓ ꢏꢀ
SCAS524E − AUGUST 1995 − REVISED OCTOBER 2003
logic diagram (positive logic)
A
B
Y
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54AC00
SN74AC00
UNIT
MIN
2
MAX
MIN
2
MAX
V
V
Supply voltage
6
6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
2.1
2.1
= 4.5 V
= 5.5 V
= 3 V
3.15
3.85
3.15
3.85
High-level input voltage
V
V
IH
0.9
1.35
1.65
0.9
1.35
1.65
= 4.5 V
= 5.5 V
V
IL
Low-level input voltage
V
V
Input voltage
0
0
V
0
0
V
V
V
V
I
CC
CC
Output voltage
V
CC
O
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
−12
−24
−24
12
−12
−24
−24
12
= 4.5 V
= 5.5 V
= 3 V
I
High-level output current
Low-level output current
mA
mA
OH
= 4.5 V
= 5.5 V
24
24
I
OL
24
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
8
8
ns/V
T
A
−55
125
−40
85
°C
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅ ꢆ ꢆꢇ ꢀꢁ ꢈꢃ ꢄꢅ ꢆꢆ
ꢉ ꢊꢄꢋꢌ ꢊꢍꢎ ꢏ ꢐ ꢑꢒꢁ ꢍꢊꢓ ꢍꢔ ꢀꢒ ꢓ ꢒꢕꢏ ꢑꢁꢄꢁ ꢋ ꢖ ꢄꢓꢏ ꢀ
SCAS524E − AUGUST 1995 − REVISED OCTOBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
SN54AC00
SN74AC00
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
2.9
TYP
MAX
MIN
2.9
4.4
5.4
2.4
3.7
4.7
3.85
MAX
MIN
2.9
MAX
3 V
4.5 V
5.5 V
3 V
4.4
4.4
I
= −50 µA
OH
5.4
5.4
I
I
= −12 mA
= −24 mA
2.56
3.86
4.86
2.46
3.76
4.76
OH
V
OH
V
4.5 V
5.5 V
5.5 V
5.5 V
3 V
OH
†
†
I
I
= −50 mA
OH
= −75 mA
3.85
OH
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
4.5 V
5.5 V
3 V
I
= 50 µA
OL
0.1
0.1
0.1
I
I
=12 mA
= 24 mA
0.36
0.36
0.36
0.5
0.44
0.44
0.44
OL
V
OL
V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
0.5
OL
0.5
†
†
I
I
= 50 mA
1.65
OL
= 75 mA
1.65
1
OL
I
I
V = V
or GND
or GND,
or GND
0.1
2
1
µA
µA
pF
I
I
CC
CC
CC
V = V
I = 0
O
40
20
CC
I
C
V = V
5 V
2.6
i
I
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.
switching characteristics over recommended operating free-air temperature range,
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
7
SN54AC00
SN74AC00
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
2
MAX
9.5
8
MIN
1
MAX
MIN
2
MAX
10
t
t
11
9
PLH
A or B
Y
ns
1.5
5.5
1
1
8.5
PHL
switching characteristics over recommended operating free-air temperature range,
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T
A
= 25°C
TYP
6
SN54AC00
SN74AC00
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1.5
MAX
8
MIN
1
MAX
MIN
1.5
1
MAX
8.5
7
t
t
8.5
7
PLH
A or B
Y
ns
1.5
4.5
6.5
1
PHL
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
Power dissipation capacitance
TEST CONDITIONS
= 50 pF, f = 1 MHz
L
TYP
UNIT
C
C
40
pF
pd
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆꢆ ꢇ ꢀꢁ ꢈ ꢃ ꢄꢅꢆ ꢆ
ꢉꢊ ꢄ ꢋꢌ ꢊ ꢍꢎ ꢏ ꢐ ꢑꢒ ꢁꢍ ꢊꢓ ꢍ ꢔꢀ ꢒ ꢓꢒ ꢕ ꢏꢑ ꢁꢄꢁ ꢋ ꢖ ꢄꢓ ꢏꢀ
SCAS524E − AUGUST 1995 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
TEST
/t
S1
Input
(see Note B)
50% V
CC
50% V
CC
t
Open
PLH PHL
0 V
t
t
t
PHL
PLH
PHL
2 × V
CC
V
OH
In-Phase
Output
S1
50% V
CC
50% V
CC
500 Ω
Open
From Output
Under Test
V
OL
t
PLH
C
= 50 pF
L
500 Ω
V
OH
(see Note A)
Out-of-Phase
Output
50% V
50% V
CC
CC
V
OL
LOAD CIRCUIT
C includes probe and jig capacitance.
L
VOLTAGE WAVEFORMS
NOTES: A.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
4-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
5962-87549012A
5962-8754901CA
5962-8754901DA
SN74AC00D
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
J
20
14
14
14
1
1
None
None
None
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
W
D
1
SOIC
50
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74AC00DBLE
SN74AC00DBR
OBSOLETE
ACTIVE
SSOP
SSOP
DB
DB
14
14
None
Call TI
Call TI
2000
2500
25
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74AC00DR
SN74AC00N
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
PDIP
SO
D
N
14
14
14
14
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
SN74AC00NSR
SN74AC00PW
NS
PW
2000
90
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
TSSOP
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
SN74AC00PWLE
SN74AC00PWR
OBSOLETE TSSOP
PW
PW
14
14
None
Call TI
Call TI
ACTIVE
TSSOP
2000
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
SNJ54AC00FK
SNJ54AC00J
SNJ54AC00W
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
14
14
1
1
1
None
None
None
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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