SN74ABT853PWLE [TI]
8-Bit To 9-Bit Parity Bus Transceivers 24-TSSOP -40 to 85;
| 型号： | SN74ABT853PWLE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-Bit To 9-Bit Parity Bus Transceivers 24-TSSOP -40 to 85 信息通信管理 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总20页 (文件大小：591K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ABT853, SN74ABT853
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997
SN54ABT853 . . . JT OR W PACKAGE
SN74ABT853 . . . DB, DW, NT, OR PW PACKAGE
(TOP VIEW)
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
OEA
A1
A2
A3
A4
A5
A6
A7
A8
V
CC
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
B1
B2
B3
B4
B5
B6
B7
B8
Latch-Up Performance Exceeds 500 mA Per
JESD 17
Typical V
< 1 V at V
(Output Ground Bounce)
OLP
CC
= 5 V, T = 25°C
A
High-Drive Outputs (–32-mA I , 64-mA I
OH
)
OL
High-Impedance State During Power Up
and Power Down
ERR 10
15 PARITY
Parity-Error Flag With Parity
Generator/Checker
CLR
GND
OEB
LE
11
12
14
13
Latch for Storage of Parity-Error Flag
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Package, and Plastic (NT)
and Ceramic (JT) DIPs
SN54ABT853 . . . FK PACKAGE
(TOP VIEW)
4
3
2
1
28 27 26
25
5
A3
A4
A5
NC
A6
A7
A8
B3
B4
B5
NC
B6
B7
B8
6
description
24
23
22
21
20
19
7
The ’ABT853 8-bit to 9-bit parity transceivers are
designedforcommunicationbetweendatabuses.
When data is transmitted from the A bus to the
B bus, a parity bit is generated. When data is
transmitted from the B bus to the A bus with its
corresponding parity bit, the open-collector
parity-error (ERR) output indicates whether or not
an error in the B data has occurred. The
output-enable (OEA and OEB) inputs can be used
to disable the device so that the buses are
effectively isolated. The ’ABT853 transceivers
provide true data at their outputs.
8
9
10
11
12 13 14 15 16 17 18
NC – No internal connection
A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports
with the ERR flag. The parity-error output can be passed, sampled, stored, or cleared from the latch using the
latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is transferred from
the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the
designer more system diagnostic capability.
When V
is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 2.1 V, OE should be tied to V
the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup resistor;
CC
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT853, SN74ABT853
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997
description (continued)
The SN54ABT853 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ABT853 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
LE
OUTPUTS AND I/Os
†
Bi
Σ OF H
FUNCTION
Ai
Σ OF H
‡
A
B
PARITY
OEB
OEA
CLR
ERR
Odd
L
A data to B bus and
generate parity
L
H
X
X
L
NA
NA
A
NA
Even
H
Odd
Even
X
H
L
B data to A bus and
check parity
H
L
X
NA
B
NA
NA
H
X
L
H
L
H
H
H
H
L
NA
X
X
X
NA
NA
NA
NA
NC
H
Store error flag
X
X
Clear error flag register
H
L
X
NC
H
X
§
Isolation
H
L
H
L
X
Z
Z
A
Z
(parity check)
X
X
L Odd
H Even
Odd
Even
H
L
L
H
L
A data to B bus and
generate inverted parity
X
X
NA
NA
NA
NA = not applicable, NC = no change, X = don’t care
†
‡
§
Summation of high-level inputs includes PARITY along with Bi inputs.
Output states shown assume ERR was previously high.
In this mode, ERR (when clocked) shows inverted parity of the A bus.
¶
logic symbol
13
11
Φ
LE
LE
10
15
ERR
ERR
CLR
CLR
1
OEA
OEB
OEA
OEB
14
PARITY
1
PARITY
2
3
4
5
6
7
8
9
23
22
21
20
19
18
17
16
A1
A2
A3
A4
A5
A6
A7
A8
1
B1
B2
B3
B4
B5
B6
B7
B8
A Bus
B Bus
8
8
¶
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT853, SN74ABT853
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997
logic diagram (positive logic)
2–9
8
8x
EN
A1–A8
23–16
8
B1–B8
8x
8
EN
14
OEB
15
1
PARITY
OEA
8
8
MUX
1
1
1
2k
9
P
1
G1
10
13
ERR
LE
11
CLR
Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages.
ERROR-FLAG FUNCTION TABLE
INTERNAL
TO DEVICE
OUTPUT
PRESTATE
INPUTS
OUTPUT
ERR
FUNCTION
†
CLR
LE
POINT P
ERR
N–1
L
H
L
L
H
L
L
L
X
Pass
X
L
H
L
X
H
X
L
Sample
H
X
L
H
H
L
L
H
H
Clear
Store
H
X
H
H
†
The state of ERR before changes at CLR, LE, or point P
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT853, SN74ABT853
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997
error-flag waveforms
H
L
OEB
H
L
OEA
Even
Odd
Bi + PARITY
H
L
LE
H
L
CLR
H
L
ERR
Pass
Store
Sample
Clear
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V : Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high or power-off state, V
. . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
O
Current into any output in the low state, I : SN54ABT853 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74ABT853 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT853, SN74ABT853
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997
recommended operating conditions (see Note 3)
SN54ABT853 SN74ABT853
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
0.8
0.8
V
0
V
CC
5.5
0
V
CC
5.5
V
I
High-level output voltage
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
ERR
V
OH
I
Except ERR
–24
48
–32
64
mA
mA
ns/V
µs/V
°C
OH
OL
I
∆t/∆v
∆t/∆V
Outputs enabled
10
10
200
–55
200
–40
CC
T
A
Operating free-air temperature
125
85
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT853, SN74ABT853
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54ABT853 SN74ABT853
A
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
MIN
MAX
MIN
MAX
V
V
V
V
V
= 4.5 V,
I = –18 mA
–1.2
–1.2
–1.2
V
IK
CC
CC
CC
I
= 4.5 V,
= 5 V,
I
I
I
I
I
I
= –3 mA
= –3 mA
= –24 mA
= –32 mA
= 24 mA
= 64 mA
2.5
3
2.5
3
2.5
3
OH
OH
OH
OH
OL
OL
All outputs
except ERR
V
V
OH
2
2
V
= 4.5 V
= 4.5 V
CC
CC
2*
2
0.55
0.55
V
V
V
OL
0.55*
0.55
100
mV
hys
I
ERR
V
V
= 4.5 V,
V
= 5.5 V
50
±1
50
±1
50
±1
µA
OH
CC
CC
CC
OH
Control inputs
A or B ports
I
I
= 5.5 V,
V = V
I
or GND
CC
µA
±100
±100
±100
V
V
= 0 to 2.1 V,
= 0.5 V to 2.7 V, OE = X
‡
‡
±50
±50
±50
±50
±50
±50
µA
µA
I
I
OZPU
O
V
V
= 2.1 V to 0,
= 0.5 V to 2.7 V, OE = X
CC
O
OZPD
§
I
I
I
V
V
V
= 5.5 V,
= 5.5 V,
= 0,
V
V
= 2.7 V
= 0.5 V
10
–10
10
10
–10
µA
µA
µA
OZH
CC
CC
CC
CC
O
§
–10
OZL
O
V or V ≤ 4.5 V
I
±100
±100
off
O
V
V
= 5.5 V,
= 5.5 V
I
Outputs high
= 2.5 V
50
50
50
µA
CEX
O
¶
#
#
#
–50 –200
I
O
V
CC
= 5.5 V,
V
O
–50 –100 –200
–50 –200
mA
µA
Outputs high
Outputs low
1
24
250
38
450
38
250
38
V
I
= 5.5 V,
= 0,
CC
O
I
A or B ports
mA
µA
CC
V = V
I
or GND
CC
Outputs disabled
0.5
250
450
250
V
= 5.5 V,
CC
Outputs enabled
Outputs disabled
1.5
50
1.5
50
1.5
50
mA
µA
One input at 3.4 V,
Other inputs at
Data inputs
||
∆I
CC
V
CC
or GND
V
= 5.5 V, One input at 3.4 V,
or GND
CC
1.5
1.5
1.5
mA
Control inputs
Other inputs at V
CC
C
C
Control inputs V = 2.5 V or 0.5 V
4.5
pF
pF
i
I
A or B ports
V
O
= 2.5 V or 0.5 V
10.5
io
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
‡
§
¶
#
||
All typical values are at V
= 5 V.
CC
This parameter is characterized, but not production tested.
The parameters I and I include the input leakage current.
OZH
OZL
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This data sheet limit can vary among suppliers.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT853, SN74ABT853
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
V
T
= 5 V,
= 25°C
CC
A
SN54ABT853 SN74ABT853
UNIT
MIN
3.5
4
MAX
MIN
3.5
4
MAX
MIN
3.5
4
MAX
LE high or low
t
w
t
su
t
h
Pulse duration
Setup time
Hold time
ns
ns
ns
CLR low
†
9.4
†
9.4
B or PARITY before LE↓
CLR before LE↓
B or PARITY after LE↓
CLR after LE↓
10.2
2
2
0
3
2
0
3
0
3
†
This data sheet limit can vary among suppliers.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
V
T
= 5 V,
= 25°C
CC
A
SN54ABT853 SN74ABT853
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1.2
1
TYP
MAX
MIN
1.2
1
MAX
6.4
MIN
1.2
1
MAX
t
t
t
t
t
t
t
t
t
t
t
4.8
5.3
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PLH
PHL
PLH
PHL
A or B
A
B or A
ns
ns
†
4.8
†
5.3
5.4
2.1
2.5
1.8
2.3
1
9.5
9.7
2.1
2.5
1.8
2.3
1
13.3
11
2.1
2.5
1.8
2.3
1
11.2
11
PARITY
8.5
13.6
11.7
6.3
10.5
10
PARITY
ERR
ns
ns
ns
OE
CLR
LE
8.6
5.5
6.2
6
1.8
5.1
1.8
6.1
1.8
1
ERR
†
†
1
1
5.8
6.7
6.6
11.7
12.8
2
†
10.1
11.5
2
†
11.8
12.9
2
B or PARITY
ns
ns
ns
ERR
†
2.2
2.2
2.2
†
†
6.7
t
t
t
t
1
†
5.8
1
†
8.8
9.8
9.5
8.2
1
†
PZH
PZL
PHZ
PLZ
A or B or PARITY
A or B or PARITY
OE
OE
1.5
1.8
2.1
5.8
7.3
7.2
1.5
1.8
2.1
1.5
1.8
2.1
6.7
7.9
8.1
†
†
†
†
†
†
†
This data sheet limit can vary among suppliers.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT853, SN74ABT853
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997
PARAMETER MEASUREMENT INFORMATION
7 V
Open
S1
500 Ω
TEST
S1
From Output
Under Test
t
/t
Open
7 V
GND
PLH PHL
t
/t
PLZ PZL
C
= 50 pF
L
500 Ω
t
/t
Open
(see Note A)
PHZ PZH
LOAD CIRCUIT
3 V
0 V
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
3 V
0 V
3 V
0 V
1.5 V
1.5 V
Input
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
PZL
t
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
S1 at 7 V
V
V
3.5 V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
– 0.3 V
OL
V
OL
OL
(see Note B)
t
PHZ
t
PLH
t
PHL
PZH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
OH
1.5 V
1.5 V
Output
≈ 0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
11-Nov-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CFP
Drawing
5962-9674601Q3A
5962-9674601QKA
5962-9674601QLA
SN74ABT853DBLE
SN74ABT853DW
ACTIVE
ACTIVE
FK
28
24
24
24
24
1
1
1
TBD
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
W
A42
A42
N / A for Pkg Type
N / A for Pkg Type
Call TI
ACTIVE
CDIP
SSOP
SOIC
JT
OBSOLETE
ACTIVE
DB
Call TI
DW
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ABT853DWE4
SN74ABT853DWG4
SN74ABT853DWR
SN74ABT853DWRE4
SN74ABT853DWRG4
SN74ABT853NT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
DW
DW
DW
DW
DW
NT
24
24
24
24
24
24
24
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
15
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74ABT853NTE4
NT
15
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74ABT853PWLE
SNJ54ABT853FK
SNJ54ABT853JT
SNJ54ABT853W
OBSOLETE TSSOP
PW
FK
JT
24
28
24
24
TBD
TBD
TBD
TBD
Call TI
Call TI
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
1
1
1
POST-PLATE N / A for Pkg Type
A42
A42
N / A for Pkg Type
N / A for Pkg Type
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Nov-2009
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74ABT853DWR
SOIC
DW
24
2000
330.0
24.4
10.75 15.7
2.7
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DW 24
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 41.0
SN74ABT853DWR
2000
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MCFP007 – OCTOBER 1994
W (R-GDFP-F24)
CERAMIC DUAL FLATPACK
0.375 (9,53)
0.340 (8,64)
Base and Seating Plane
0.006 (0,15)
0.004 (0,10)
0.045 (1,14)
0.026 (0,66)
0.090 (2,29)
0.045 (1,14)
0.395 (10,03)
0.360 (9,14)
0.360 (9,14)
0.240 (6,10)
0.360 (9,14)
0.240 (6,10)
0.019 (0,48)
0.015 (0,38)
1
24
0.050 (1,27)
0.640 (16,26)
0.490 (12,45)
0.030 (0,76)
0.015 (0,38)
12
13
30° TYP
1.115 (28,32)
0.840 (21,34)
4040180-5/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD
E. Index point is provided on cap for terminal identification only.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MCER004A – JANUARY 1995 – REVISED JANUARY 1997
JT (R-GDIP-T**)
CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
PINS **
A
24
28
DIM
13
24
1.280
(32,51) (37,08)
1.460
A MAX
1.240
(31,50) (36,58)
1.440
B
A MIN
B MAX
B MIN
0.300
(7,62)
0.291
(7,39)
1
12
0.070 (1,78)
0.030 (0,76)
0.245
(6,22)
0.285
(7,24)
0.320 (8,13)
0.290 (7,37)
0.015 (0,38) MIN
0.100 (2,54) MAX
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.014 (0,36)
0.008 (0,20)
0.100 (2,54)
4040110/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
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