SN65LVPE504RUAR [TI]

四通道（半 x4 单路）PCI Express Gen II 转接驱动器 | RUA | 42 | -40 to 85;


型号：	SN65LVPE504RUAR
厂家：	TEXAS INSTRUMENTS
描述：	四通道（半 x4 单路）PCI Express Gen II 转接驱动器 \| RUA \| 42 \| -40 to 85 PC 驱动接口集成电路线路驱动器或接收器驱动程序和接口
文件：	总16页 (文件大小：3001K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN65LVPE504

www.ti.com

SLLSE46 –SEPTEMBER 2010

Quad Channel (Half X4 Lane) PCIe Redriver/Equalizer

Check for Samples: SN65LVPE504

FEATURES

DESCRIPTION

•

4 Identical Channel PCIe Equalizer/Redriver

•

Support for Both PCIe Gen I (2.5Gbps) and

Gen II (5.0 Gbps) Speed

The SN65LVPE504 is a quad channel, half four lane

PCIe redriver and signal conditioner supporting data

rates of up to 5.0Gbps. The device complies with

PCIe spec revision 2.1, supporting electrical idle and

power management modes.

•

Selectable Equalization, De-emphasis, and

Output Swing

•

Per Channel Receive Detect (Lane Detection)

Programmable EQ, De-Emphasis and Amplitude

Swing

Selectable Receiver Electrical Idle Threshold

Control

The SN65LVPE504 is designed to minimize the

signal degradation effects such as crosstalk and

inter-symbol interference (ISI) that limits interconnect

distance between two devices. The input stage of

each channel offers selectable equalization settings

that can be programmed to match loss in the

channel. The differential outputs provide selectable

de-emphasis to compensate for the anticipated

distortion PCIe signal will experience. Both

•

Low Operating Power Modes

–

Supports Three Low-Power Modes to

Enable up to 80% Lower Operating Power

•

Excellent Jitter and Loss Compensation

Capability to 50" of 4-mil SL on FR4

Small Foot Print – 42 Pin 9 × 3.5 TQFN

Package

High Protection Against ESD Transient

equalization and de-emphasis levels for all

channels are controlled by the setting of signal

control pins EQ, DE and OS.

–

HBM: 6,000 V

CDM: 1,000 V

MM: 200 V

See Table 1 for EQ, DE and OS setting details.

spacer

APPLICATIONS

•

PC MB, Docking Station, Server,

Communication Platform, Backplane and

Cabled Application

PS1 PS2

RST# EN_RXD

Low Power

Controller

Detect

1-4+

Receiver/

Equalizer

Receiver/

Equalizer

CHANNEL

1-4

Driver

1-4-

Loss of Signal

Detector

VBB_TX

SQ_TH

Figure 1. Data Flow Block Diagram

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

SN65LVPE504

SLLSE46 –SEPTEMBER 2010

DEVICE OPERATION

Device PowerOn

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Device initiates internal power-on reset after Vcc has stabilized. External reset can also be applied at anytime by

toggling RST pin. External reset is recommended after every device power-up. After 50µs (MAX) from the

application of RST, device samples the state of EN_RXD, if it is set H device will enter Rx.Detect state where

each of the four channels will perform Rx.Detect function (as described in PCIe spec). If EN_RXD is set L,

automatic RX detect function is disabled and all channels are enabled with their termination set to Z_{RX_DC}

Receiver Detection

While EN_RXD pin is H and device is not in reset state (RST is H), LVPE504 performs RX.Detect on all its 4

channels indefinitely until remote termination is detected on at least one channel. When termination is detected

on ≥ 1 CH, RX.Detect cycle is limited to 5 more tries on the other channels. At the end of 5^thtry those channels

which failed to detect remote termination will be turned off to save power and their Rx termination is set to

Z_RX-HIGH. In the event device detects only three channels, all four channels are enabled.

Automatic Rx detection feature on all four channels can be forced off by driving EN_RXD low. In this state all

four channels input termination are set to Z_{RX_DC}

Standby Mode

This is low power state triggered by RST = L. In standby mode receiver termination resistor for each of the four

channels is switched to Z_RX-HIGHof >50 kΩ and transmitters are pulled to Hi-Z state. Device power is reduced to

<10mW (TYP). To get device out of standby mode RST is toggled L-H.

Electrical Idle Support

A link is in an electrical idle state when the TX± voltage is held at a steady constant value like the common mode

voltage. LVPE504 detects an electrical idle state when RX± input voltage of the associated channel falls below

V_{EID_TH}min and stays in this state for at least 20ns. After detection of an electrical idle state in a given channel

the device asserts electrical idle state in its corresponding TX. When RX± voltage exceeds V_{EID_TH}max, normal

operation is restored and output start passing input signal. Electrical idle exit and entry time is specified at < 8 ns

(MAX).

Electrical idle support is independent for each channel, however to lower active power it is possible to slave

electrical idle function from channel 1 to CH2-CH4. This mode is selected by driving PS2 to H.

Power Save Features

Device supports three power save modes as below:

1. Standby Mode

This mode can be enabled from any state (Rx detect or active) by driving RST L. In this state all 4 channels

have their termination set to Z_RX-HIGHand outputs are at Hi-Z. Device power is 10mW (MAX).

2. Auto Low Power Mode

This mode is enabled when PS1 pin is tied H and device has been in active mode, i.e., past Rx detect state

for >250ms (TYP). In this mode anytime Vin_{diff_p-p}falls below selected V_{EID_TH}for a given channel and stays

below V_{EID_TH}for >1µs, the associated CH enters auto low power (ALP) mode where power/CH is reduced

by >80% of normal operating power/CH. A CH will exit ALP mode whenever Vin_{diff_p-p}exceeds max V_{EID_TH}

for that channel. Exit latency from ALP state is 30ns max. To use this mode link latency will need to account

for the ALP exit time for N_FTS. ALP mode is handled by each channel independently based on its input

differential signal level, unless slave mode is activated (PS2=H) when CH1 controls SQ detect of other

channels based on its signal level.

3. Slave Power Mode

This mode is activated by driving PS2 high. Under normal operation squelch detection is handled by each

channel independently. In slave mode SQ detection for CH2, CH3 and CH4 are turned off and squelch

function is slaved to that of CH1. By turning off squelch detection circuitry for three of the four channels

device saves power. To use this feature user must ensure all channels operate simultaneously

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SN65LVPE504

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SLLSE46 –SEPTEMBER 2010

Squelch Control

Controls electrical idle detect threshold level. Three levels are supported as shown in Table 1.

Beacon Support

With its broadband design, the SN65LVPE504 supports low frequency Beacon signal (as defined by PCIe 2.1

spec) used to indicate wake-up event to the system by a downstream device when in L2 power state. All

requirements for a beacon signal as specified in PCI Express specification 2.1 must be met for device to pass

beacon signals.

PCIe

compliant

cable

Instrumentation Chassis/

I/O expansion box/

Docking Station

Server/PC/Notebook

Cabled

Midplane

I/O Module

Mainboard

I/O Hub

SN75LVPE504

Backplane

Figure 2. LVPE504 Typical Applications

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SLLSE46 –SEPTEMBER 2010

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DEVICE INFORMATION

RUA Package

(Top View)

VCC

RX1+

RX1–

GND

RX2+

RX2–

GND

VCC

GND

RX3+

RX3–

GND

RX4+

RX4–

TX1+

TX1–

GND

TX2+

TX2–

GND

VCC

GND

TX3+

TX3–

GND

TX4+

TX4–

VCC

Figure 3. Flow-Through Pin-Out

PIN FUNCTIONS

I/O TYPE

DESCRIPTION

NO.

NAME

HIGH SPEED DIFFERENTIAL I/O PINS

RX1+

RX1–

RX2+

RX2–

RX3+

RX3–

RX4+

RX4–

TX1+

TX1–

TX2+

TX2–

Non-inverting and inverting CML differential input for CH 1 and CH 4. These pins are tied to an internal voltage

bias by dual termination resistor circuit

I, CML

Non-inverting and inverting CML differential output for CH 1 and CH 4. These pins are internally tied to voltage

bias by termination resistors

O, CML

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SLLSE46 –SEPTEMBER 2010

PIN FUNCTIONS (continued)

I/O TYPE

DESCRIPTION

NO.

NAME

HIGH SPEED DIFFERENTIAL I/O PINS (continued)

TX3+

TX3–

TX4+

TX4–

Non-inverting and inverting CML differential output for CH 1 and CH 4. These pins are internally tied to voltage

bias by termination resistors

O, CML

DEVICE CONTROL PIN

EN_RXD

I, LVCMOS Sets device operation modes per Table 1. Internally pulled to VCC

PS2

PS1

I, LVCMOS Tying pin to VCC slaves CH2-4 electrical idle and Rx.Detect function to CH1. Internally pulled to GND

I, LVCMOS Select auto-low power save mode per Table 1. Internally pulled to GND

SQ_TH⁽¹⁾I, LVCMOS Squelch threshold level select pin for electrical idle detect per Table 1 Internally pulled to VCC/2

RST I, LVCMOS Reset device, input active Low. Internally pulled to VCC

SIGNAL CONDITIONING PINS⁽¹⁾

I, LVCMOS Selects de-emphasis settings for CH 1-CH 4 per Table 1. Internally pulled to Vcc/2

I, LVCMOS Selects equalization settings for CH 1-CH 4 per Table 1. Internally pulled to Vcc/2

I, LVCMOS Selects output amplitude for CH 1-CH 4 per Table 1. Internally pulled to Vcc/2

POWER PINS

1,9,17,22,30,38

VCC

GND

Power

Positive supply should be 3.3V ± 10%

Supply ground

5,8,10,13,

26,29,31,34û

(1) Internally biased to Vcc/2 with >200kΩ pull-up/pull-down. When 3-state pins are left as NC, board leakage at the pin pad must be < 1 µA

otherwise drive to Vcc/2 to assert mid-level state.

Table 1. Control Pin Settings

OUTPUT SWING (CH1-CH4) at 5Gbps

SQUELCH THRESHOLD (CH1-CH4)

TRANSITION BIT AMPLITUDE

MIN DIFFERENTIAL INPUT

SQ_TH

(TYP mVpp)

(CH1-CH4)

47 mVpp

61 mVpp

83 mVpp

800

NC (default)

929

NC (default)

1047

OUTPUT DE-EMPHASIS (CH1-CH4) at 5Gbps

INPUT EQUALIZATION (CH1-CH4)

OS = NC

–3.4dB

OS = 0

–2.1dB

–4.9dB

–9.2dB

OS = 1

–4.6dB

–7.2dB

–11dB

Equalization dB (at 5Gbps)

NC (default)

7 (default)

–6.2dB

–10.3dB

EN_RXD

DEVICE FUNCTION

Set input termination to Rx_DC

Perform Rx detect after power up

RST

DEVICE FUNCTION

Device in standby state, inputs set to Hi-Z

Device in active mode

PS1

DEVICE FUNCTION

Auto-low power mode disabled (default)

Auto-low power mode enabled

PS2

DEVICE FUNCTION

Electrical Idle and Rx Detect independent for CH1-CH4 (default)

CH2-CH4 Electrical Idle and Rx Detect slaved to CH1

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SN65LVPE504

SLLSE46 –SEPTEMBER 2010

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ORDERING INFORMATION⁽¹⁾

PART MARKING

PART NUMBER

SN65LVPE504RUAR

PACKAGE

LVPE504

42-pin RUA Reel (large)

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

VALUE

–0.5 to 4

–0.5 to VCC + 0.5

±6000

UNIT

Supply voltage range⁽²⁾

Voltage range

V_CC

Differential I/O

Control I/O

Human body model⁽³⁾

Charged-device model⁽⁴⁾

Machine model⁽⁵⁾

Electrostatic discharge

±1000

±200

Continuous power dissipation

See Thermal Table

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions

is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential voltages, are with respect to network ground terminal.

(3) Tested in accordance with JEDEC Standard 22, Test Method A114-B

(4) Tested in accordance with JEDEC Standard 22, Test Method C101-A

(5) Tested in accordance with JEDEC Standard 22, Test Method A115-A

THERMAL INFORMATION

SN65LVPE504

THERMAL METRIC

UNITS

TQFN (42 PINS)

q_JA

Junction-to-ambient thermal resistance

0.5

q_JCtop

q_JB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

y_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

y_JB

q_JCbot

4.7

RECOMMENDED OPERATING CONDITIONS

MIN

TYP

MAX

3.6

UNITS

V_CC

Supply voltage

3.3

C_COUPLING

AC Coupling capacitor

Operating free-air temperature

200

°C

–40

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SLLSE46 –SEPTEMBER 2010

ELECTRICAL CHARACTERISTICS

under recommended operating conditions

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

DEVICE PARAMETERS

RST, DEx, EQx, OS = NC, EN_RXD = NC, K28.5

pattern at 5 Gbps, VID = 1000mVp-p

I_CC

174

161

190

175

PS2 = Vcc; RST, DEx, EQx, OS = NC,

EN_RXD = NC, K28.5 pattern at 5 Gbps,

V_ID= 1000mV_p-p

ICC_Slave

Supply current

ICC_ALP

When auto-low power conditions are met,

PS1 = V_CC

ICC_{ALP _Slave}

ICC_{NO_CONNECT}

ICC_stdby

PS1, PS2 = VCC and link in EID state

EN_RXD = 1 No termination detected on any CH

RST = GND

2.5

0.1

Maximum data rate

Gbps

µs

AutoLP_ENTRY

AutoLP_EXIT

t_ENB

Auto low power entry time

Auto low power exit time

Device enable time

Electrical idle at input, Refer to Figure 7

After first signal activity, Refer to Figure 7

RST 0 → 1

µs

t_DIS

Device disable time

RST 1 → 0

0.1

µs

EN_RXD = 1, Time to start Rx Detect after power

T_RX.Detect

Rx.Detect start event

µs

CONTROL LOGIC

V_IH

High level Input Voltage

Low Level Input Voltage

Input Hysteresis

1.4

Vcc

0.5

V_IL

–0.3

V_HYS

150

OS, EQ, DE, SQ_TH, PS1, PS2 = V_CC

EN_RXD, RST = V_CC

I_IH

High Level Input Current

Low Level Input Current

µA

PS1, PS2 = GND

–1

I_IL

OS, EQ, DE, SQ_TH, EN_RXD, RST = GND

–30

RECEIVER AC/DC

Vin_{diff_p-p}

RX1-RX4 Input voltage swing

Max Rx total timing error

AC coupled differential signal (5Gbps)

At device pin (5Gbps)

100

1200 mVp-p

T_{RX_TJ}

0.4

Max Rx deterministic timing

error

T_{RX_DJ}

At device pin (5Gbps)

0.3

RX1-RX4 Common mode

voltage

V_{CM_RX}

3.6

RX1-RX4 AC peak common

mode voltage

Vin_{COM_P}

Z_{RX_DC}

150

mVP

Ω

DC single ended impedance

DC Differential input

impedance

Z_{RX_Diff}

120

Ω

Device in standby mode. Rx termination not

powered measured with respect to GND over 200

mV max

Z_{RX_High}

DC Input high impedance

kΩ

Measured at receiver pin: SQ_TH = NC

V_{EID_TH}

Electrical idle detect threshold SQ_TH = 1

SQ_TH = 0

107

mVpp

50 MHz – 1.25 GHz

RL_RX-DIFF

RL_RX-CM

Differential return loss

1.25 GHz – 2.5 GHz

50 MHz – 2.5 GHz

Common mode return loss

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SLLSE46 –SEPTEMBER 2010

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ELECTRICAL CHARACTERISTICS (continued)

under recommended operating conditions

PARAMETER

CONDITIONS

MIN

TYP

MAX UNITS

TRANSMITTER AC/DC

RL = 100Ω ±1%, OS = NC, transition Bit

RL = 100Ω ±1%, OS = GND transition Bit

RL = 100Ω ±1% OS = VCC transition Bit

866

929

800

1031

1047

Differential peak-to-peak

output voltage

V_{TXDIFF_P-P}

RL = 100Ω ±1%, DE=NC, OS = 0,1,NC

on-transition bit

620

RL = 100Ω ±1%, DE=OS = 0,1,NC on-transition bit

456

288

–3.0

–5.5

–3.4

–6.2

–4.0

OS = NC (Figure 9) for OS = 1 and NC see

Table 1)

De-emphasis level

–6.5

–9.0 –10.3 –10.6

0.9

T_DE

De-emphasis width

At 5 Gbps

Z_{TX_diff}

DC Differential impedance

Defined during signaling

f = 50 MHz – 1.25 GHz

f = 1.25 GHz – 2.5 GHz

f = 50 MHz – 2.5 GHz

TX± shorted to GND

100

120

Ω

RL_{diff_TX}

Differential return loss

RL_{CM_TX}

I_{TX_SC}

Common mode return loss

TX short circuit current

Transmitter DC common-mode Allowed DC CM voltage at TX pins

voltage

V_{TX_CM_DC}

V_{TX_CM_AC2}

V_{TX_CM_AC1}

1.8

2.2

TX AC common mode voltage Max(V_d++ V_d–) /2 – Min(V_d++ V_d–)/2

at Gen II speed

100

mVpp

TX AC common mode voltage RMS(V_d++ V_d–)/2 – DC_AVG(V_d++ V_d–)/2

at Gen I speed

V_{TX_CM_DeltaL0-}

L0s

Absolute Delta DC CM voltage |V_{TX_CM_DC [L0]}– VTX_CM_DC [L0_s] |

during active and idle states

100

V_{TX_CM-DC-Line-}

Delta

Absolute delta of DC CM

|V_{TX_CM_DC–D+ [L0]}– V_{TX_CM_DC–D– [L0]}|

voltage between D+ and D–

Electrical idle differential peak |V_TX-Idle-D+– V_TX-Idle-D–|, LP filtered to remove any

V_{TX_idle_diff-AC-p}

V_{TX_idle_diff-DC}

V_detect

mVpp

output voltage

DC component

DC electrical idle differential

output voltage

|V_{TX_idle-D+}– V_{TX_idle-D–}|, LP filtered to remove any

AC component

1.9

Voltage change to allow

receiver detect

Positive voltage to sense receiver

600

De-Emphasis = 0 dB,

t_R,t_F

Output rise/fall time

OS = NC (CH 0 and CH 1)

20%-80% of differential voltage at the output

De-Emphasis = 0dB,

t_{RF_MM}

Output rise/fall time mismatch OS = NC (CH 0 and CH 1)

20%-80% of differential voltage at the output

De-Emphasis = 0dB (CH 0 and CH 1). Propagation

delay between 50% level at input and output

T_{diff_LH}, T_{diff_HL}

Differential propagation delay

280

350

T_{INTRA_SKEW}

T_{INTER_SKEW}

t_idleEntry, t_idleExit

T_{tx_EID_min}

Output skew (same lane)

Lane to lane skew

5 Gbps

–25

Idle entry and exit times

Minimum time in EID

See Figure 5

Tx EQUALIZATION AT GEN II SPEED

(1)

TX_DJ

At point A1 in Figure 8, EQ/DE=NC, OS=HIGH

At point A2 in Figure 8, EQ/DE=NC, OS=LOW

At point B in Figure 8, EQ/DE=NC, OS=HIGH

D24.3 pattern at point A1/A2/B in Figure 8

Residual deterministic jitter

ps p-p

psrms

TX_RJ

Residual random jitter

0.1

(1) Refer to Figure 8 with ±K28.5 pattern, –3.5dB DE from source AWG

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SLLSE46 –SEPTEMBER 2010

diff_HL

diff_LH

OUT

Figure 4. Propagation Delay

IN+

Vcm

IN-

EID_TH

idleExit

idleEntry

OUT+

Vcm

OUT-

Figure 5. Idle Mode Exit and Entry Delay

80 %

20 %

Figure 6. Output Rise and Fall Times

RX_1-4+

RX_1-4-

TX_1-4+

TX_1-4-

VCM

idleEntry

AutoLP

EXIT

VCM

AutoLP

Power Saving

Mode

ENTRY

Figure 7. Auto Low Power Mode Timing (when enabled)

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SLLSE46 –SEPTEMBER 2010

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X = 40", 4mil SL on

FR4

Jitter Measurement

AWG*

Y = 8", 5mil SL on

FR4

5 Gbps Signal Gen.

K28.5 pattern, 800mVpp

X = 25", 4mil SL on

FR4

Jitter Measurement

AWG*

Y = 23", 5mil SL on

FR4

5 Gbps Signal Gen.

K28.5 pattern, 800mVpp

Figure 8. Jitter Measurement Setup

1-bit

1 to N bits

1-bit

t_DE

DEx/OSx = NC

-3.4dB

-6.2dB

DEx = 0;

OSx = NC

-10.3dB

DEx = 1;

OSx = NC

Vcm

Diff_VppTX

Diff_{VppTX_DE}

t_DE

Figure 9. Output De-Emphasis Levels

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SLLSE46 –SEPTEMBER 2010

TYPICAL CHARACTERISTICS

TYPICAL EYE DIAGRAM AND PERFORMANCE CURVES

•

Input Signal Characteristics – VID = 1000mVpp, DE = –3.5 dB, Pattern = K28.5

Device Operating Conditions: VCC = 3.3 V, Temp = 25°C

All trace are 4 mils

PCIe Gen I and Gen II compliance mask shown

AT GEN II SPEED

Input Trace = 4", Output Trace = 8"

Input Trace = 4", Output Trace = 16"

EQ = 0 dB, OS = 833 mVpp, DE = -1.9 dB

EQ = 0 dB, OS = 1166 mVpp, DE = -4.9 dB

Figure 10.

Figure 11.

Input Trace = 4", Output Trace = 28"

Input Trace = 16", Output Trace = 4"

EQ = 0 dB, OS = 1166 mVpp, DE = -7.4 dB

EQ = 0 dB, OS = 833 mVpp, DE = -1.9 dB

Figure 12.

Figure 13.

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TYPICAL CHARACTERISTICS (continued)

Input Trace = 28", Output Trace = 4"

Input Trace = 36", Output Trace = 4"

EQ = 7 dB, OS = 833 mVpp, DE = -1.9 dB

Figure 14.

Figure 15.

Input Trace = 48", Output Trace = 4"

EQ = 15 dB, OS = 833 mVpp, DE = -1.9 dB

Figure 16.

AT GEN I SPEED

Input Trace = 4", Output Trace = 8"

Input Trace = 4", Output Trace = 16"

EQ = 7 dB, OS = 833 mVpp, DE = -1.9 dB

EQ = 7 dB, OS = 1166 mVpp, DE = -4.9 dB

Figure 17.

Figure 18.

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TYPICAL CHARACTERISTICS (continued)

Input Trace = 4", Output Trace = 28"

Input Trace = 16", Output Trace = 4"

EQ = 7 dB, OS = 1166 mVpp, DE = -7.4 dB

EQ = 7 dB, OS = 833 mVpp, DE = -1.9 dB

Figure 19.

Figure 20.

Input Trace = 28", Output Trace = 4"

Input Trace = 36", Output Trace = 4"

EQ = 15 dB, OS = 833 mVpp, DE = -1.9 dB

Figure 21.

Figure 22.

Input Trace = 48", Output Trace = 4"

EQ = 15 dB, OS = 833 mVpp, DE = -1.9 dB

Figure 23.

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PACKAGE OPTION ADDENDUM

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4-Oct-2010

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

SN65LVPE504RUAR

ACTIVE

WQFN

RUA

3000

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

Request Free Samples

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

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TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

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SN65LVPE504RUAR [TI]

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