SN65LVPE501RGER [TI]

Dual Channel x1 PCIe Redriver/Equalizer; 双通道的PCIe X1转接驱动器/均衡器


型号：	SN65LVPE501RGER
厂家：	TEXAS INSTRUMENTS
描述：	Dual Channel x1 PCIe Redriver/Equalizer 双通道的PCIe X1转接驱动器/均衡器驱动器 PC
文件：	总24页 (文件大小：1268K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN65LVPE501

www.ti.com

SLLSE30A –MAY 2010–REVISED MAY 2012

Dual Channel x1 PCIe Redriver/Equalizer

Check for Samples: SN65LVPE501

FEATURES

•

Excellent Jitter and Loss Compensation

Capability:

•

Single Lane PCIe Equalizer/Redriver

–

30" of 6 mil Stripline on FR4

Support for Both PCIe Gen I (2.5Gbps) and

Gen II (5.0 Gbps) Speed

•

Small Foot Print – 24 Pin 4 × 4 QFN Package

High Protection Against ESD Transient

•

Selectable Equalization, De-emphasis and

Output Swing Control

–

HBM: 3,000 V

CDM: 1,500 V

MM: 200 V

•

Integrated Termination

Hot-Plug Capable

Receiver Detect

Low Power:

APPLICATIONS

•

PC MB, Docking Stations, Backplane and

Cabled Application

–

330mW(TYP), V_CC= 3.3V

•

Auto Low Power Modes:

–

5mW (TYP) When no Connection Detected

70mW (TYP) When in Auto-Low Power

Mode

DESCRIPTION

The SN65LVPE501 is a dual channel, single lane PCIe redriver and signal conditioner supporting data rates of

up to 5.0Gbps. The device complies with PCIe spec revision 2.1.

Programmable EQ, De-Emphasis and Amplitude Swing

The SN65LVPE501 is designed to minimize the signal degradation effects such as crosstalk and inter-symbol

interference (ISI) that limits the interconnect distance between two devices. The input stage of each channel

offers selectable equalization settings that can be programmed to match loss in the channel. The differential

outputs provide selectable de-emphasis to compensate for the anticipated distortion PCIe signal will experience.

Level of de-emphasis will depend on the length of interconnect and its characteristics. Both equalization and de-

emphasis levels are controlled by the setting of signal control pins EQ1, EQ2 and DE1, DE2.

To provide additional control of signal integrity in extended backplane applications LVPE501 provides

independent output amplitude control for each channel. See Table 2 for setting details.

Device PowerOn

Device initiates internal power-on reset after V_CChas stabilized. External reset can also be applied at anytime by

toggling RST pin. External reset is recommended after every device power-up. When RST is driven high, the

device samples the state of EN_RXD, if it is set H device enters Rx.Detect state where each channel will perform

Rx.Detect function (as described in PCIe spec). If EN_RXD is set L, automatic RX detect function is disabled and

both channels are enabled with their termination set to Z_{DC_RX}

Receiver Detection

While EN_RXD pin is H and device is not in sleep mode (RST is H), SN65LVPE501 performs RX.Detect on both

channels indefinitely until remote termination is detected on both channels. Automatic Rx detection feature can

be forced off by driving EN_RXD low. In this state both channels input termination are set to Z_{DC_RX}

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

SN65LVPE501

SLLSE30A –MAY 2010–REVISED MAY 2012

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION CONTINUED

Sleep (Shut_Down) Mode

This is low power state triggered by RST = L. In sleep mode receiver termination resistor for each of the two

channels is switched to Z_{RX-HIGH_IMP}of >50 KΩ and transmitters are pulled to Hi-Z state. Device power is reduced

to <1mW (TYP). To get device out of sleep mode RST is toggled L-H.

Electrical Idle Support

A link is in an electrical idle state when the TX± voltage is held at a steady constant value like the common mode

voltage. SN65LVPE501 detects an electrical idle state when RX± input voltage of the associated channel falls

below V_{EID_TH}min. After detection of an electrical idle state in a given channel the device asserts electrical idle

state in its corresponding TX. When RX± voltage exceeds V_{EID_TH}max, normal device operation is restored and

output starts passing input signal. Electrical idle exit and entry time is specified at ≤6ns.

Electrical idle support is independent for each channel.

Power Save Features

The device supports three power save modes as described below.

1. Sleep (Shut_Down) Mode

This mode can be enabled from any state (Rx detect or active) by driving RST L. In this state both channels

have their termination set to Z_{RX-HIGH_IMP+}and outputs are at Hi-Z. Device power is 1mW (MAX)

2. Auto Low Power Mode

This mode is enabled when PS pin is tied H and device is in active mode. In this mode anytime Vin_{diff_pp}falls

below selected V_{EID_TH}for a given channel and stays below V_{EID_TH}for >1µs (TYP), the associated CH will

enter auto low power (ALP) mode where power/CH will be reduced to <1/3^rdof normal operating power/CH

or about 70mW under typical voltage of 3.3V when ALP conditions are met for both channels. A CH will exit

ALP mode whenever Vin_{diff_pp}exceeds max V_{EID_TH}for that channel. Exit latency is 30ns max. To use this

mode link latency will need to account for the ALP exit time for N_FTS. ALP mode is handled by each

channel independently based on its input differential signal level. This mode can be disabled by leaving PS

as NC or tying PS to GND via 4.7kΩ.

3. Cable Disconnect Mode

This mode is activated when RST is H, EN_RXD = H, and no termination is detected by either channel.

Device is in the Rx.Detect state whereby it is continuously performing Rx.Detect on both channels. In this

state total power consumed by device is typically <3% of normal active power. Or <10mW (MAX).

Beacon Support

With its broadband design, the SN65LVPE501 supports low frequency Beacon signal (as defined by PCIe 2.1

spec) used to indicate wake-up event to the system by a downstream device when in L2 power state. All

requirements for a beacon signal as specified in PCI Express specification 2.1 must be met for device to pass

beacon signals.

Devic Power

The SN65LVPE501 is designed to operate from a single 3.3V supply. Always practice proper supply sequencing

procedure. Apply V_CCfirst before any input control pin signals are applied to the device. Power-down sequence

is in reverse order.

SN65LVPE501

www.ti.com

SLLSE30A –MAY 2010–REVISED MAY 2012

PCIe

Instrumentation Chassis

/I/O expansion box/

Docking Station

compliant

cable

Server/PC/Notebook

Midplane

I/O Module

I/O Hub

SN75LVPE501

Figure 1. SN65LVPE501 Typical Applications

SN65LVPE501

SLLSE30A –MAY 2010–REVISED MAY 2012

www.ti.com

RST

Detect

RX1+

TX1+

TX1-

Receiver/

Equalizer

CHANNEL 1

Driver

RX1-

EQ1

CNTRL

EQ2

VBB_TX

DE1

DE2

DEMP

CNTRL

TX2+

RX2+

RX2-

Receiver/

Equalizer

CHANNEL 2

Driver

TX2-

VBB_TX

Cntrl.

Detect

RST

OS1

OS2

Figure 2. Data Flow Block Diagram

Split System

Upstream Board

Downstream Board

PCIe

PCIe Cable

EN_RXD

CPRSNT#

Enclosed System

System Board

PCIe

EN_RXD

Mezzanine

Card

Figure 3. Typical Implementation

SN65LVPE501

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NUMBER

SLLSE30A –MAY 2010–REVISED MAY 2012

Table 1. Pin Description

NAME

I/O TYPE

DESCRIPTION

HIGH SPEED DIFFERENTIAL I/O PINS

RX1+

RX1–

RX2+

RX2–

TX1+

TX1–

TX2+

TX2–

I, CML

O, CML

Non-inverting and inverting CML differential input for CH 1 and CH 2. These pins are tied to an

internal voltage bias by dual termination resistor circuit.

Non-inverting and inverting CML differential output for CH 1 and CH 2. These pins are

internally tied to voltage bias by termination resistors.

DEVICE CONTROL PIN⁽¹⁾

EN_RXD

I, LVCMOS Sets device operation modes per Table 2. Internally pulled to VCC

I, LVCMOS Select auto-low power save mode per Table 2. Internally pulled to GND

I, LVCMOS Reset device, input active Low. Internally pulled to VCC

I, LVCMOS Reserved for factory test. Must be connected to GND

RST

RSVD

SIGNAL CONTROL PINS⁽²⁾

3,16

2,17

DE1, DE2

EQ1, EQ2

OS1, OS2

I, LVCMOS Selects de-emphasis settings for CH 1 and CH 2 per Table 2. Internally tied to V_CC/2

I, LVCMOS Selects equalization settings for CH 1 and CH 2 per Table 2. Internally tied to V_CC/2

I, LVCMOS Selects output amplitude for CH 1 and CH 2 per Table 2. Internally tied to V_CC/2

4, 15

POWER PINS

1,13

VCC

GND

Power

Positive supply should be 3.3V ± 10%

Supply ground

6,10,18,21

(1) When not used can be left as NC or connected to V_CC/GND via 4.7kΩ resistor.

(2) Internally biased to V_CC/2 with >200kΩ pullup/pulldown. When 3-state pins are left as NC board leakage at the pin pad must be <1 µA

otherwise drive to V_CC/2 to assert mid-level state.

SN65LVPE501

SLLSE30A –MAY 2010–REVISED MAY 2012

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Table 2. Signal Control Pin Setting

TRANSITION BIT AMPLITUDE

OSx

(TYP mVpp)

1000

875

1100

DEx⁽¹⁾

OSx⁽¹⁾= NC

–3.7 dB

OSx⁽¹⁾= 0

OSx⁽¹⁾= 1

–4.6 dB

–6.6 dB

–8.7 dB

–2.5 dB

–5.5 dB

–9.5 dB

–6.4 dB

–9.4 dB

EQUALIZATION dB

(At GenII Speed)

EQx⁽¹⁾

EN_RXD

DEVICE FUNCTION

Set input termination to Z_{DC_RX}

and disable Rx. Detect

Perform Rx.Detect (default,

internally pulled to Vcc)

RST

DEVICE FUNCTION

Device in quiescent state and

inputs set to Hi-Z

Device not in shut_down mode

(default, internally pulled to Vcc)

DEVICE FUNCTION

Auto-low power mode disabled

(default, internally pulled to GND)

Auto-low power mode enabled

(1) Applies to Channel 1 and Channel 2 at 2.5 GHz.

SN65LVPE501

www.ti.com

SLLSE30A –MAY 2010–REVISED MAY 2012

3.3 V

TOP VIEW

OS1 DE1

GND

EN_RXD

EQ1

VCC

SN65LVPE501

RST

RSVD

0.1 µF

TX1+

TX1–

RX1+

RX1–

CH1

0.1 µF

Thermal Pad

(must be soldered to

GND plane)

GND

0.1 µF

TX2+

TX2–

0.1 µF

RX2+

RX2–

CH2

0.1 µF

VCC

OS2

DE2

EQ1

GND

3.3 V

(1) This is a reference example and it is not intended to represent the best configuration; every designer should select

the EQ and DE settings that better fits the system needs. All DEx, EQx and OSx pins default to NC.

(2) The recommended value for all the resistors shown in the Figure is 4.9K Ω.

(3) For terminals OSx, DEx, and EQx, populate only pull-up or only pull-down according to the desired setting.

Figure 4. Reference Device Implementation

SN65LVPE501

SLLSE30A –MAY 2010–REVISED MAY 2012

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BOTTOM VIEW

EQ1 DE1

EN_RXD

OS1

VCC

GND

SN65LVPE501

RSVD

RST

TX1+

TX1-

GND

RX2+

RX2-

RX1+

RX1-

CH1

Thermal Pad

(must be soldered to

GND plane)

GND

TX2+

TX2-

CH2

GND EQ2

DE2 OS2

PS VCC

TOP VIEW

GND EN_RXD OS1

DE1 EQ1

VCC

SN65LVPE501

RSVD

TX1+

TX1-

RST

RX1+

RX1-

CH1

Thermal Pad

(must be soldered to

GND plane)

GND

RX2+

RX2-

TX2+

TX2-

CH2

OS2 DE2 EQ2

VCC PS

GND

Figure 5. Flow-Through Pin-Out

ORDERING INFORMATION⁽¹⁾

PART MARKING

LVPE501

PART NUMBER

PCAKAGE

SN65LVPE501RGER

SN65LVPE501RGET

24-pin RGE Reel (large)

24-pin RGE Reel (small)

LVPE501

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

SN65LVPE501

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SLLSE30A –MAY 2010–REVISED MAY 2012

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

UNIT / VALUES

–0.5 V to 4 V

Supply Voltage Range⁽²⁾

Voltage Range

V_CC

Differential I/O

–0.5V to 4 V

Control I/O

–0.5 V to V_CC+ 0.5

±3000 V

(Human Body Model) QSS 009-105 (JESD22-A114B)

(Charged Device Model) QSS 009-147 (JESD22-C101-A)

(Machine Model) JESD22-A115-A

Electrostatic Discharge

±1500 V

±200 V

Continuous power dissipation

See Thermal Information Table

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions

is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential voltages, are with respect to network ground terminal.

THERMAL INFORMATION

SN65LVPE501

THERMAL METRIC⁽¹⁾

RGE

UNITS

24 PINS

θ_JA

Junction-to-ambient thermal resistance⁽²⁾

0.5

(3)

θ_JC(TOP)

θ_JB

Junction-to-case(top) thermal resistance

(4)

Junction-to-board thermal resistance

°C/W

(5)

ψ_JT

Junction-to-top characterization parameter

(6)

ψ_JB

Junction-to-board characterization parameter

(7)

θ_JC(BOTTOM)

Junction-to-case(bottom) thermal resistance

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

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SLLSE30A –MAY 2010–REVISED MAY 2012

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RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN TYP MAX UNIT

V_CC

Supply Voltage

3.3

3.6

C_COUPLING

AC Coupling Capacitor

Operating free-air temperature

200 nF

85 °C

–40

ELECTRICAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

DEVICE PARAMETERS (under recommended operating conditions, unless otherwise noted)

RST, DEx, EQx, OSx = NC, EN_RXD = NC, K28.5 pattern at 5 Gbps,

V_ID= 1000mV_p-p

I_CC

101

120

ICC_idle

PS=1; When auto-low power conditions are met

RST = GND

0.2

Supply Current

ICC_shut-down

ICC_RX.Detect

RST, EN_RXD = NC

Maximum Data Rate

Gbps

µs

AutoLP_ENTRY

AutoLP_EXIT

Auto Low Power Entry Time

Auto Low Power Exit Time

Electrical Idle at Input, Refer to Figure 9

After first signal activity, Refer to Figure 9

1.0

1.3

Rx Detect Start Event, Vcc = Stable

RST, EN_RXD = H

t_PU

Power Up Time

µs

Sleep (shut-down) Mode Entry

Time

t_DIS

RST H→L; EN_RXD=X

µs

T_ENB

Sleep (shut-down) Mode Exit Time RST L→H; EN_RXD=H, Start of Ex detect event

CONTROL LOGIC (under recommended operating conditions, unless otherwise noted)

V_IH

High level Input Voltage

Low Level Input Voltage

Input Hysteresis

1.4

V_CC

0.5

V_IL

–0.3

V_HYS

150

OSx, EQx, DEx = V_CC

EN_RXD, RST = V_CC

OSx, EQx, DEx = GND

PS = GND

I_IH

High Level Input Current

µA

–30

–1

I_IL

Low Level Input Current

EN_RXD, RST = GND

–20

RECEIVER AC/DC (under recommended operating conditions, unless otherwise noted)

Vin_{diff_pp}

V_{CM_RX}

RX1, RX2 Input Voltage Swing

AC coupled differential signal

100

1200 mVp-p

3.6

RX1, RX2 Common Mode Voltage

RX1, RX2 AC Peak common

mode voltage

Vin_{COM_P}

150 mVP

Z_{DC_RX}

Z_{diff_RX}

DC single ended impedance

DC Differential Input impedance

100

120

Device in sleep mode Rx termination not powered; Measured with

respect to GND over 200mV max

Z_{RX_High_IMP+}

V_{EID_TH}

DC Input High Impedance

kΩ

Electrical Idle Detect Threshold

Measured at receiver pin (see Figure 7)

50 MHz – 1.25 GHz

175 mVpp

RL_RX-DIFF

Differential Return Loss

Operating temperature 0°C to 85°C

1.25 GHz – 2.5 GHz

Operating temperature –40°C to 85°C

RL_RX-CM

Common Mode Return Loss

50 MHz – 2.5 GHz

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ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

TRANSMITTER AC/DC (under recommended operating conditions, unless otherwise noted)

R_L=100Ω ±1%, DEx, OS = NC, Transition Bit

800 1000 1200

V_{TXDIFF_PP}

R_L=100Ω ±1%, DEx = NC, OSx = GND Transition Bit

R_L=100Ω ±1%, DEx = NC, OSx = VCC Transition Bit

875

1100

R_L=100Ω ±1%, DEx=NC, OSx = 0,1,NC

Non-Transition Bit

Differential peak-to-peak Output

Voltage

655

495

350

R_L=100Ω ±1%, DEx=0,OSx = 0,1,NC

Non-Transition Bit

V_{TXDIFF_NTB_PP}

R_L=100Ω ±1%, DEx=1, OSx = 0,1,

NC Non-Transition Bit

DEx, OSx = NC, See

Figure 11 ;

(for OS1,2 = 1 and 0 see

Table 2)

Operating temperature 0°C to 85°C

–3.0

–3.7

–4.0

–4.2

Operating temperature –40°C to 85°C

De-Emphasis Level

DEx = 0, OSx = NC

DEx = 1, OSx = NC

At 5Gbps

–6.4

–9.4

0.8

T_DE

De-Emphasis Width

Z_{diff_TX}

DC Differential Impedance

Defined during signaling

9.5

100

120

Ω

Operating temperature 0°C to 85°C

Operating temperature –40°C to 85°C

Operating temperature 0°C to 85°C

Operating temperature –40°C to 85°C

f = 50 MHz – 1.25 GHz.

f = 1.25 GHz – 2.5 GHz,

RL_{diff_TX}

Differential Return Loss

5.5

RL_{CM_TX}

I_{TX_SC}

Common Mode Return Loss

TX short circuit current

f = 50 MHz – 2.5 GHz

TX± shorted to GND

Transmitter DC common-mode

voltage

V_{TX_CM_DC}

Allowed DC CM voltage at TX pins

Max(V_d++ V_d–)/2 – Min(V_d++ V_d–)/2

|V_{TX_CM_DC [L0]}– V_{TX_CM_DC [L0s]}|, PS=L

2.1

2.65

3.1

TX AC common mode voltage at

GEN II speed

V_{TX_CM_AC2}

100 mVpp

TX AC common mode voltage at

GEN I speed

V_{TX_CM_AC1}

100

Absolute Delta DC CM voltage

during active and idle states

V_{TX_CM_DeltaL0-L0s}

V_{TX_CM-DC-Line-}

Absolute Delta of DC CM voltage

between D+ and D–

|V_{TX_CM_DC-D+ [L0]}– V_{TX_CM_DC-D- [L0]}

Delta

Electrical idle differential peak

output voltage

V_{TX_idle_diff-AC-p}

V_{TX_idle_diff-DC}

V_detect

|V_TX-Idle-D+– V_TX-Idle-D–| HP filtered to remove any DC component

|V_{TX_idle-D+}– V_{TX_idle-D–}| LP filtered to remove any AC component

Positive voltage to sense receiver

10 mVpp

DC Electrical idle differential

output voltage

3.5

Voltage change to allow receiver

detect

600

DEx = NC, OS = NC (CH 0 and CH 1) 20%-80% of differential voltage

at the output; VID > 1000mVpp

t_R,t_F

Output Rise/Fall time

DEx = NC, OS = NC (CH 0 and CH 1) 20%-80% of differential voltage

at the output

t_{RF_MM}

Output Rise/Fall time mismatch

DEx = NC (CH 0 and CH 1). Propagation delay between 50% level at

input and output. See Figure 6

T_{diff_LH}, T_{diff_HL}

t_idleEntryt_idleExit

Differential Propagation Delay

Idle entry and exit times

280

330

See Figure 7

Tx EQUALIZATION at GEN II Speed (under recommenced operating conditions)

At point A in Figure 10⁽²⁾

At point B in Figure 10⁽²⁾

At point A in Figure 10⁽²⁾

(1)

T_TX-TJ

Total Jitter

ps pp

T_TX-DJ

Deterministic Jitter

(2)

At point B in Figure 10

(1) Includes RJ at 10^-12

(2) Refer to Figure 10 with ± K28.5 pattern at 5Gbps, –3.5dB DE from source AWG .

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diff_HL

diff_LH

OUT

Figure 6. Propagation Delay

vertical spacer

IN+

EID_TH

IN-

idleExit

idleEntry

OUT+

OUT-

Figure 7. Idle Mode Exit and Entry Delay

vertical spacer

80%

20%

Figure 8. Output Rise and Fall Times

vertical spacer

RX_1,2+

RX_1,2-

VCM

idleEntry

AutoLP

EXIT

TX_1,2+

TX_1,2-

VCM

AutoLP

Power Saving

Mode

ENTRY

Figure 9. Auto Low Power Mode Timing (when enabled)

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Jitter

Measurement

25" 6mil

Stripline

5" 6mil Stripline

AWG*

A = Device pin + 2"

B = End of trace on test board

Jitter

Measurement

Figure 10. Jitter Measurement Setup

vertical spacer

1-bit

1 to N bits

1-bit

t_DE

DEx = NC

-3.7dB

-6.4 dB

DEx = 0

-9.4 dB

DEx = 1

V_{TXDIFF_NTB_P-P}

V_{TXDIFF_TB_P-P}

t_DE

Figure 11. Output De-Emphasis Levels OSx = NC

Typical Eye Diagram and Performance Curves at Output

Input Signal Characteristics: Data Rate = 5 Gbps, V_ID= 1000 mVpp, DE = -3.5 dB, Pattern = K28.5

Device Operating Conditions: VCC = 3.3 V, Temp = 25°C

Device EQ settings (EQ/DE/OS) adjusted for best eye performance

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Output Trace Length Held Constant and Input Trace Length Varied

Figure 12. Input Trace = 4 Inches, 6 mil, and Measured at Output Trace = 4 Inches

vertical spacer

Figure 13. Input Trace = 20 Inches, 6 mil, and Measured at Output Trace = 4 Inches

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Figure 14. Input Trace = 32 Inches, 6 mil, and Measured at Output Trace = 4 Inches

vertical spacer

Figure 15. Input Trace = 44 Inches, 6 mil, and Measured at Output Trace = 4 Inches

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Variable Trace Lengths at Input and Output

Figure 16. Input Trace = 28 Inches, 6 mil, and Measured at Output Trace = 24 Inches

vertical spacer

Figure 17. Input Trace = 44 Inches, 6 mil, and Measured at Output Trace = 24 Inches

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Product Folder Link(s): SN65LVPE501

SN65LVPE501

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SLLSE30A –MAY 2010–REVISED MAY 2012

REVISION HISTORY

Changes from Original (May 2010) to Revision A

Page

•

Added Figure 4 ..................................................................................................................................................................... 7

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Product Folder Link(s): SN65LVPE501

PACKAGE OPTION ADDENDUM

www.ti.com

11-May-2012

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

SN65LVPE501RGER

SN65LVPE501RGET

ACTIVE

VQFN

RGE

3000

250

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

SN65LVPE501RGER

SN65LVPE501RGET

VQFN

RGE

3000

250

330.0

180.0

12.4

4.25

1.15

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

SN65LVPE501RGER

SN65LVPE501RGET

VQFN

RGE

3000

250

367.0

210.0

367.0

185.0

35.0

Pack Materials-Page 2

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SN65LVPE501RGER [TI]

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