SN65LVDS311YFFT [TI]
可编程 27 位显示屏串行接口变送器 | YFF | 49 | -40 to 85;型号: | SN65LVDS311YFFT |
厂家: | TEXAS INSTRUMENTS |
描述: | 可编程 27 位显示屏串行接口变送器 | YFF | 49 | -40 to 85 驱动 接口集成电路 驱动器 |
文件: | 总33页 (文件大小:1774K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SN65LVDS311
www.ti.com
SLLSE31B –MAY 2010–REVISED MARCH 2013
PROGRAMMABLE 27-BIT DISPLAY SERIAL INTERFACE TRANSMITTER
Check for Samples: SN65LVDS311
When transmitting, the PLL locks to the incoming
1
FEATURES
pixel clock PCLK and generates an internal high-
speed clock at the line rate of the data lines. The
parallel data is latched on the rising edge of PCLK.
The serialized data is presented on the serial outputs
D0, D1, D2 with a recreation of the Pixel clock PCLK
generated from the internal high-speed clock and
output on the CLK output. If the input clock PCLK
stops, the device enters a standby mode to conserve
power.
•
•
•
2.8 × 2.8mm package size
1.8V input signal swing
24-Bit RGB Data, 3 Control Bits, 1 Parity Bit
and 2 Reserved Bits Transmitted over 1, 2 or 3
Differential Lines
•
•
SubLVDS Differential Voltage Levels
Three Operating Modes to Conserve Power
–
–
–
–
Active-Mode QVGA 17.4mW (typ)
Active-Mode VGA 28.8mW (typ)
Shutdown Mode ≈ 0.5μA (typ)
Standby Mode ≈ 0.5μA (typ)
Two Link-Select lines LS0 and LS1 control whether 1,
2 or 3 serial links are used. The TXEN input may be
used to put the SN65LVDS311 in a shutdown mode.
The SN65LVDS311 enters an active Standby mode if
the input clock PCLK stops. This minimizes power
consumption without the need for controlling an
external pin. The SN65LVDS311 is characterized for
operation over ambient air temperatures of -40°C to
85°C. All CMOS inputs offer failsafe to protect the
input from damage during power-up and to avoid
current flow into the device inputs during power-up.
•
•
•
•
ESD Rating > 3kV (HBM)
Pixel Clock Range of 4MHz–65MHz
Failsafe on all CMOS Inputs
Typical Application: Cameras, Embedded
Computers
DESCRIPTION
The SN65LVDS311 serializer transmits 27 parallel
input data over 1, 2, or 3 serial output links. The
device pinout is optimized to interface with the
OMAP3630 application processor. The device loads a
shift register with the 24 pixel bits and 3 control bits
from the parallel CMOS input interface. The data are
latched into the device by the pixel clock, PCLK. In
addition to the 27 bits, the device adds a parity bit
and two reserved bits for a total number of 30 serial
bits. The parity bit allows a receiver to detect single-
bit errors. Odd parity is implemented.
The serial shift register is uploaded through 1, 2, or 3
serial outputs at 30, 15, or 10 times the pixel clock
data rate. A copy of the pixel clock is output on an
additional differential output. The serial data and
clock are transmitted via Sub Low-Voltage Differential
Signaling (SubLVDS) lines. The SN65LVDS311
supports three power modes (Shutdown, Standby
and Active) to conserve power.
LCD
VDS314
L
or
VDS302
L
Application
Processor
with CMOS
Video Interface
LVDS301
or
LVDS311
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2010–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN65LVDS311
SLLSE31B –MAY 2010–REVISED MARCH 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Functional Block Diagram
Parity
Calculation
D0+
SubLVDS
Bit 29
D0-
Bit 28 = 0
8
R[0:7]
Bit 27 = 0
D1+
SubLVDS
8
G[0:7]
D1-
[0..26]
8
B[0:7]
D2+
SubLVDS
D2-
HS
VS
CLK+
SubLVDS
DE
CLK-
iPCLK
PCLK
x10, x15, x30
x1
PLL
Multiplier
LS0
LS1
Control /
Standby Monitor
Glitch
Suppression
TXEN
PINOUT
SN65LVDS311 Top view
SN65LVDS311 Bottom view
1
2
3
G1
R0
G3
R7
B2
B3
D0N
4
5
6
7
PCLK
HS
7
PCLK
HS
6
DE
5
4
3
G1
R0
G3
R7
B2
B3
D0N
2
1
A
B
C
D
E
F
A
B
C
D
E
F
R3
R5
B0
B1
B4
G5
G4
R2
R1
G6
R6
G2
B5
G7
B7
R4
DE
R4
B7
R2
R1
G6
R6
G2
B5
G7
R3
R5
B0
B1
B4
G5
G4
G0
B6
VS
VS
B6
G0
GND
VDD
GND
GND
D0P
LS1
LS0
D2P
D2P
LS0
LS1
GND
VDD
GND
GND
D0P
VDDPLLD
TXEN
GND
CLKN
GND
GND
VDDPLLA
CLKP
D2N
D2N
GND
GND
VDDPLLA
CLKP
VDDPLLD
TXEN
GND
CLKN
D1P
D1P
D1N
D1N
G
G
VDDLVDS
VDDLVDS
2
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SLLSE31B –MAY 2010–REVISED MARCH 2013
Table 1. SIGNAL LIST
SIGNAL
R0
PIN
SIGNAL
PIN
SIGNAL
B0
PIN
SIGNAL
PCLK
HS
PIN
A7
B7
B6
A6
E5
C6
C5
B3
B2
A2
A1
A5
B1
D2
D3
G4
G3
D4
G0
G1
G2
G3
G4
G5
G6
G7
B4
A3
E2
C3
G1
F1
C2
G2
E7
F7
D5
C1
D1
E3
F3
E1
F2
B5
A4
C7
D7
F6
R1
B1
R2
B2
VS
R3
B3
DE
R4
B4
TXEN
LS0
R5
B5
R6
B6
LS1
R7
B7
D0P
D0N
VDD
GND
D1P
D2P
D2N
VDDPLLA
CLKP
CLKN
G6
G5
G7
D1N
VDDPLLD
VDDLVDS
C4, D6, E6, E4, F4, F5
Table 2. TERMINAL FUNCTIONS
NAME
I/O
DESCRIPTION
D0+, D0–
SubLVDS Data Link (active during normal operation)
SubLVDS Data Link (active during normal operation when LS0 = high and LS1 = low, or
LS0 = low and LS1=high; high impedance if LS0 = LS1 = low)
D1+, D1–
SubLVDS Out
SubLVDS Data Link (active during normal operation when LS0 = low and LS1 = high,
high-impedance when LS1 = low)
D2+, D2–
CLK+, CLK–
R0–R7
G0–G7
B0–B7
HS
SubLVDS output Clock; clock polarity is fixed
Red Pixel Data (8); pin assignment depends on SWAP pin setting
Green Pixel Data (8); pin assignment depends on SWAP pin setting
Blue Pixel Data (8); pin assignment depends on SWAP pin setting
Horizontal Sync
VS
Vertical Sync
DE
Data Enable
PCLK
LS0, LS1
Input Pixel Clock; data are latched on rising input clock edge
Link Select (Determines active SubLVDS Data Links and PLL Range) See Table 3
Disables the CMOS Drivers and Turns Off the PLL, putting device in shutdown mode
CMOS IN
1 – Transmitter enabled
0 – Transmitter disabled
(Shutdown)
TXEN
Note: The TXEN input incorporates glitch-suppression logic to avoid device malfunction
on short input spikes. It is necessary to pull TXEN high for longer than 10 μs to enable
the transmitter. It is necessary to pull the TXEN input low for longer than 10 μs to disable
the transmitter. At power up, the transmitter is enabled immediately if TXEN = 1 and
disabled if TXEN = 0
VDD
Supply Voltage
GND
Supply Ground
VDDLVDS
GNDLVDS
VDDPLLA
GNDPLLA
VDDPLLD
GNDPLLD
SubLVDS I/O supply Voltage
SubLVDS Ground
Power Supply(1)
PLL analog supply Voltage
PLL analog GND
PLL digital supply Voltage
PLL digital GND
(1) For a multilayer pcb, it is recommended to keep one common GND layer underneath the device and connect all ground terminals
directly to this plane.
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SLLSE31B –MAY 2010–REVISED MARCH 2013
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FUNCTIONAL DESCRIPTION
Serialization Modes
The SN65LVDS311 transmitter has three modes of operation controlled by link-select pins LS0 and LS1. Table 3
shows the serializer modes of operation.
Table 3. Logic Table: Link Select Operating Modes
LS1
LS0
Mode of Operation
Data Links Status
0
0
1ChM
2ChM
3ChM
1-channel mode (30-bit serialization rate)
D0 active;
D1, D2 high-impedance
0
1
2-channel mode (15-bit serialization rate)
D0, D1 active;
D2 high-impedance
1
1
0
1
3-channel mode (10-bit serialization rate)
Reserved
D0, D1, D2 active
Reserved
1-Channel Mode
While LS0 and LS1 are held low, the SN65LVDS311 transmits payload data over a single SubLVDS data pair,
D0. The PLL locks to PCLK and internally multiplies the clock by a factor of 30. The internal high-speed clock is
used to serialize (shift out) the data payload on D0. Two reserved bits and the parity bit are added to the data
frame. Figure 1 illustrates the timing and the mapping of the data payload into the 30-bit frame. The internal high-
speed clock is divided by a factor of 30 to recreate the pixel clock, and presented on the SubLVDS CLK output.
While in this mode, the PLL can lock to a clock that is in the range of 4MHz through 15MHz. This mode is
intended for smaller video display formats (e.g. QVGA to HVGA) that do not require the full bandwidth
capabilities of the SN65LVDS311.
CLK–
CLK+
D0 +/– CHANNEL
0
0
CP R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 VS HS DE
0
0
CP R7 R6
Figure 1. Data and Clock Output in 1-Channel Mode (LS0 and LS1 = low).
2-Channel Mode
While LS0 is held high and LS1 is held low, the SN65LVDS311 transmits payload data over two SubLVDS data
pairs, D0 and D1. The PLL locks to PCLK and internally multiplies it by a factor of 15. The internal high-speed
clock is used to serialize the data payload on D0, and D1. Two reserved bits and the parity bit are added to the
data frame. Figure 2 illustrates the timing and the mapping of the data payload into the 30-bit frame and how the
frame becomes split into the two output channels. The internal high-speed clock is divided by 15 to recreate the
pixel clock, and presented on SubLVDS CLK. The PLL can lock to a clock that is in the range of 8MHz through
30MHz in this mode. Typical applications for using the 2-channel mode are HVGA and VGA displays.
CLK–
CLK +
D0 +/– Channel CP R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 VS
0
CP R7 R6
D1 +/– Channel
G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0 HS DE G3 G2
0 0
Figure 2. Data and Clock Output in 2-Channel Mode (LS0 = high; LS1 = low).
4
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SLLSE31B –MAY 2010–REVISED MARCH 2013
3-Channel Mode
While LS0 is held low and LS1 is held high, the SN65LVDS311 transmits payload data over three SubLVDS data
pairs D0, D1, and D2. The PLL locks to PCLK, and internally multiplies it by 10. The internal high-speed clock is
used to serialize the data payload on D0, D1, and D2. Two reserved bits and the parity bit are added to the data
frame. Figure 3 illustrates the timing and the mapping of the data payload into the 30-bit frame and how the
frame becomes split over the three output channels. The internal high speed clock is divided back down by a
factor of 10 to recreate the pixel clock and presented on SubLVDS CLK output. While in this mode, the PLL can
lock to a clock in the range of 20MHz through 65MHz. The 3-channel mode supports applications with very large
display resolutions such as VGA or XGA.
CLK -
CLK +
D0 +/- CHANNEL CP R7 R6 R5 R4 R3 R2 R1 R0 VS CP R7 R6
D1 +/- CHANNEL
D2 +/- CHANNEL
0
0
G7 G6 G5 G4 G3 G2 G1 G0 HS
B7 B6 B5 B4 B3 B2 B1 B0 DE
0
0
G7 G6
B7 B6
Figure 3. Data and Clock Output in 3-Channel Mode (LS0 = low; LS1 = high).
Powerdown Modes
The SN65LVDS311 Transmitter has two powerdown modes to facilitate efficient power management.
Shutdown Mode
The SN65LVDS311 enters Shutdown mode when the TXEN pin is asserted low. This turns off all transmitter
circuitry, including the CMOS input, PLL, serializer, and SubLVDS transmitter output stage. All outputs are high-
impedance. Current consumption in Shutdown mode is nearly zero.
Standby Mode
The SN65LVDS311 enters the Standby mode if TXEN is high and the PCLK input frequency is less than 500kHz.
All circuitry except the PCLK input monitor is shut down, and all outputs enter high-impedance mode. The current
consumption in Standby mode is very low. When the PCLK input signal is completely stopped, the IDD current
consumption is less than 10 μA. The PCLK input must not be left floating.
NOTE
A floating (left open) CMOS input allows leakage currents to flow from VDD to GND. To
prevent large leakage current, a CMOS gate must be kept at a valid logic level, either VIH
or VIL. This can be achieved by applying an external voltage of VIH or VIL to all
SN65LVDS311 inputs.
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Active Modes
When TXEN is high and the PCLK input clock signal is faster than 3MHz, the SN65LVDS311 enters Active
mode. Current consumption in Active mode depends on operating frequency and the number of data transitions
in the data payload.
Acquire Mode (PLL approaches lock)
The PLL is enabled and attempts to lock to the input Clock. All outputs remain in high-impedance mode. When
the PLL monitor detects stable PLL operation, the device switches from Acquire to Transmit mode. For proper
device operation, the pixel clock frequency must fall within the valid fPCLK range specified under recommended
operating conditions. If the pixel clock frequency is larger than 3MHz but smaller than fPCLK(min), the
SN65LVDS311 PLL is enabled. Under such conditions, it is possible for the PLL to lock temporarily to the pixel
clock, causing the PLL monitor to release the device into transmit mode. If this happens, the PLL may or may not
be properly locked to the pixel clock input, potentially causing data errors, frequency oscillation, and PLL
deadlock (loss of VCO oscillation).
Transmit Mode
After the PLL achieves lock, the device enters the normal transmit mode. The CLK pin outputs a copy of PCLK.
Based on the selected mode of operation, the D0, D1, and D2 outputs carry the serialized data. In 1-channel
mode, outputs D1 and D2 remain high-impedance. In the 2-channel mode, output D2 remains high-impedance.
Parity Bit Generation
The SN65LVDS311 transmitter calculates the parity of the transmit data word and sets the parity bit accordingly.
The parity bit covers the 27 bit data payload consisting of 24 bits of pixel data plus VS, HS and DE. The two
reserved bits are not included in the parity generation. ODD Parity bit signaling is used. The transmitter sets the
Parity bit if the sum of the 27 data bits result in an even number of ones. The Parity bit is cleared otherwise. This
allows the receiver to verify Parity and detect single bit errors.
Status Detect and Operating Modes Flow diagram
The SN65LVDS311 switches between the power saving and active modes in the following way:
Power Up
TXEN = 1
CLK Inactive
Power Up
TXEN = 0
TXEN Low
> 10 ms
TXEN High > 10 ms
Shutdown
Mode
Standby
Mode
PCLK
Stops or Lost
PCLK
Active
TXEN Low
> 10 ms
PCLK
Stops or Lost
Power Up
TXEN = 1
CLK Active
TXEN Low
> 10 ms
PLL Achieved Lock
Transmit
Mode
Acquire
Mode
Figure 4. Status Detect and Operating Modes Flow Diagram
6
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SLLSE31B –MAY 2010–REVISED MARCH 2013
Table 4. Status Detect and Operating Modes Descriptions
Mode
Characteristics
Conditions
Shutdown Mode
Least amount of power consumption(1) (most circuitry turned TXEN is low(1) (2)
off); All outputs are high-impedance
Standby Mode
Low power consumption (only clock activity circuit active; PLL TXEN is high; PCLK input signal is missing or
is disabled to conserve power); All outputs are high-
impedance
inactive(2)
Acquire Mode
Transmit Mode
PLL tries to achieve lock; All outputs are high-impedance
TXEN is high; PCLK input monitor detected input
activity
Data transfer (normal operation); Transmitter serializes data
and transmits data on serial output; unused outputs remain
high-impedance
TXEN is high and PLL is locked to incoming clock
(1) In Shutdown Mode, all SN65LVDS311 internal switching circuits (e.g., PLL, serializer, etc.) are turned off to minimize power
consumption. The input stage of any input pin remains active.
(2) Leaving inputs unconnected can cause random noise to toggle the input stage and potentially harm the device. All inputs must be tied to
a valid logic level VIL or VIH during Shutdown or Standmby Mode.
Table 5. Operating Mode Transitions
MODE TRANSITION
USE CASE
TRANSITION SPECIFICS
Shutdown → Standby
Drive TXEN high to enable
transmitter
1. TXEN high > 10 μs
2. Transmitter enters standby mode
a. All outputs are high-impedance
b. Transmitter turns on clock input monitor
1. PCLK input monitor detects clock input activity;
2. Outputs remain high-impedance;
Standby → Acquire
Acquire → Transmit
Transmitter activity detected
Link is ready to transfer data
3. PLL circuit is enabled
1. PLL is active and approaches lock
2. PLL achieved lock within 2 ms
3. Parallel Data input latches into shift register
4. CLK output turns on
5. selected Data outputs turn on and send out first serial data bit
1. PCLK Input monitor detects missing PCLK
2. Transmitter indicates standby, putting all outputs into high-impedance;
3. PLL shuts down;
Transmit → Standby
Request Transmitter to enter
Standby mode by stopping
PCLK
4. PCLK activity input monitor remains active
1. TXEN pulled low for longer than 10us
Transmit/Standby →
Turn off Transmitter
Shutdown
2. Transmitter indicates standby, putting output CLK+ and CLK– into high-
impedance state;
3. Transmitter puts all other outputs into high-impedance state
4. Most IC circuitry is shut down for least power consumption
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SLLSE31B –MAY 2010–REVISED MARCH 2013
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ORDERING INFORMATION(1)
PART NUMBER
SN65LVDS311YFF
SN65LVDS311YFFR
PACKAGE
SHIPPING METHOD
Tray
Reel
YFF
(1) Updated odering information is found in the orderable addendum at the end of this document.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
-0.3 to 2.175
-0.5 to 2.175
-0.5 to VDD + 2.175
±3
UNIT
V
Supply voltage range, VDD (2), VDDPLLA, VDDPLLD, VDDLVDS
Voltage range at any input When VDDx > 0 V
V
or output terminal
When VDDx ≤ 0 V
V
Human Body Model(3) (all Pins)
kV
V
Electrostatic discharge
Charged-Device Mode(4)l (all Pins)
Machine Model(5) (all pins)
±500
±200
Continuous power dissipation
See Dissipation Rating Table
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the GND terminals.
(3) In accordance with JEDEC Standard 22, Test Method A114-A.
(4) In accordance with JEDEC Standard 22, Test Method C101.
(5) In accordance with JEDEC Standard 22, Test Method A115-A
DISSIPATION RATINGS
CIRCUIT
DERATING FACTOR(1)
ABOVE TA = 25°C
TA = 85°C
POWER RATING
PACKAGE
θJA < 25°C
BOARD MODEL
YFF
Low-K(2)
692mW
7.69 mW/°C
148 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
(2) In accordance with the Low-K thermal metric definitions of EIA/JESD51-2.
THERMAL CHARACTERISTICS
PARAMETER
TEST CONDITIONS
VALUE
14.4
UNIT
PCLK at 4MHz
PCLK at 65MHz
PCLK at 4MHz
PCLK=65MHz
Typical
VDDx = 1.8 V, TA = 25°C
mW
mW
44.5
PD Device Power Dissipation
22.3
Maximum
VDDx = 1.95 V, TA = –40°C
71.8
8
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RECOMMENDED OPERATING CONDITIONS(1)
MIN
NOM
MAX UNIT
VDD
Supply voltages
1.65
1.8
1.95
V
VDDPLLA
VDDPLLD
VDDLVDS
VDDn(PP)
Test set-up see Figure 10
f(PCLK) ≤ 50MHz; f(noise) = 1 Hz to 2 GHz
f(PCLK) > 50MHz; f(noise) = 1 Hz to 1MHz
f(PCLK) > 50MHz; f(noise) > 1MHz
1-Channel transmit mode, see Figure 1
2-Channel transmit mode, see Figure 2
3-Channel transmit mode, see Figure 3
100
100
40
15
30
65
3
Supply voltage noise
magnitude (all supplies)
mV
4
8
fPCLK
Pixel clock frequency
PCLK input duty cycle
MHz
°C
20
0.5
Frequency threshold Standby mode to active
mode(2), see Figure 14
tH x fPCLK
TA
0.33
–40
0.67
85
Operating free-air
temperature
tjit(per)PCLK
tjit(TJ)PCLK
tjit(CC)PCLK
PCLK RMS period jitter(3)
5
0.05/fPCLK
0.02/fPCLK
ps-rms
PCLK total jitter
s
s
Measured on PCLK input
PCLK peak
cycle-to-cycle jitter(4)
PCLK, R[0:7], G[0:7], B[0:7], VS, HS, DE, PCLK, LS[1:0], TXEN, SWAP
VIH
VIL
tDS
High-level input voltage
Low-level input voltage
0.7×VDD
VDD
V
V
0.3×VDD
Data set up time prior to
PCLK transition
2.0
2.0
ns
f (PCLK) = 65MHz; see Figure 6
tDH
Data hold time after PCLK
transition
ns
(1) Unused single-ended inputs must be held high or low to prevent them from floating.
(2) PCLK input frequencies lower than 500kHz force the SN65LVDS311into standby mode. Input frequencies between 500kHz and 3MHz
may or may not activate the SN65LVDS311. Input frequencies beyond 3MHz activate the SN65LVDS311.
(3) Period jitter is the deviation in cycle time of a signal with respect to the ideal period over a random sample of 100,000 cycles.
(4) Cycle-to-cycle jitter is the variation in cycle time of a signal between adjacent cycles; over a random sample of 1,000 adjacent cycle
pairs.
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DEVICE ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAM
ETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
VDD =VDDPLLA=VDDPLLD=VDDLVDS
RL(PCLK)=RL(D0)=100 Ω, VIH=VDD, VIL=0 V,
,
fPCLK = 4MHz
fPCLK = 6MHz
fPCLK = 15MHz
fPCLK = 4MHz
fPCLK = 6MHz
fPCLK = 15MHz
fPCLK = 8MHz
fPCLK = 22MHz
fPCLK = 30MHz
fPCLK = 8MHz
fPCLK = 22MHz
fPCLK = 30MHz
fPCLK = 20MHz
fPCLK = 65MHz
9.0
10.6
16
11.4
12.6
18.8
mA
TXEN at VDD
,
alternating 1010 serial bit pattern
1ChM
2ChM
3ChM
VDD =VDDPLLA=VDDPLLD=VDDLVDS
,
8.0
RL(PCLK)=RL(D0)=100 Ω, VIH=VDD, VIL=0 V,
TXEN at VDD
typical power test pattern (see Table 7)
8.9
mA
mA
mA
mA
,
14.0
13.7
18.4
21.4
11.5
16.0
19.1
20.0
VDD =VDDPLLA=VDDPLLD=VDDLVDS
RL(PCLK)=RL(Dx)=100 Ω, VIH=VDD, VIL=0 V,
TXEN at VDD
alternating 1010 serial bit pattern;
,
15.9
22.0
25.8
,
VDD =VDDPLLA=VDDPLLD=VDDLVDS
RL(PCLK)=RL(D0)=100 Ω, VIH=VDD, VIL=0 V,
TXEN at VDD
typical power test pattern (see Table 8)
,
,
IDD
VDD =VDDPLLA=VDDPLLD=VDDLVDS
RL(PCLK)=RL(D0)=100 Ω, VIH=VDD, VIL=0 V,
TXEN at VDD
,
22.5
36.8
,
29.1
15.9
24.7
0.61
alternating 1010 serial bit pattern
VDD =VDDPLLA=VDDPLLD=VDDLVDS
,
fPCLK = 20MHz
fPCLK = 65MHz
RL(PCLK)=RL(D0)=100 Ω, VIH=VDD, VIL=0 V,
TXEN at VDD
typical power test pattern (see Table 9)
mA
,
Standby Mode
VDD = VDDPLLA = VDDPLLD
10
10
μA
= VDDLVDS
,
RL(PCLK)=RL(D0)=100 Ω,
VIH=VDD, VIL=0 V, all
inputs held static high or
static low
Shutdown Mode
0.55
μA
(1) All typical values are at 25°C and with 1.8 V supply unless otherwise noted.
OUTPUT ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
subLVDS output (D0+, D0–, D1+, D1–, D2+, D1–, CLK+, and CLK–)
VOCM(SS) Steady-state common-mode output voltage
VOCM(SS) Change in steady-state common-mode output voltage
VOCM(PP) Peak-to-peak common mode output voltage
Output load see Figure 8
0.8
0.9
1.0
10
V
–10
mV
mV
75
|VOD
|
Differential output voltage magnitude
|VDx+ – VDx– |, |VCLK+ – VCLK–
100
–10
150
200
mV
|
Δ|VOD
|
Change in differential output voltage between logic states
10
10
3
mV
ZOD(CLK) Differential small-signal output impedance
TXEN at VDD
210
5
Ω
IOSD
IOS
Differential short-circuit output current
Short circuit output current(2)
VOD = 0 V, fPCLK = 28MHz
VO = 0 V or VDD
mA
IOZ
High-impedance state output current
VO = 0 V or VDD(max),
TXEN at GND
–3
μA
(1) All typical values are at 25°C and with 1.8 V supply unless otherwise noted.
(2) All SN65LVDS311 outputs tolerate shorts to GND or VDD without permanent device damage.
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INPUT ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1) MAX UNIT
PCLK, R[0:7], G[0:7], B[0:7], VS, HS, DE, PCLK, LS[1:0], TXEN, SWAP
IIH
High-level input current
Low-level input current
Input capacitance
VIN = 0.7 × VDD
VIN = 0.3 × VDD
–200
–200
200
nA
IIL
200
CIN
1.5
pF
(1) All typical values are at 25°C and with 1.8 V supply unless otherwise noted.
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX UNIT
tr
tf
20%-to-80% differential
output signal rise time
See Figure 7 and Figure 8
250
500
ps
20%-to-80% differential
output signal fall time
See Figure 7 and Figure 8
Tested from PCLK input to
250
500
fPCLK = 22MHz
fPCLK = 65MHz
1-channel mode
2-channel mode
3-channel mode
0.082 × fPCLK
0.07 × fPCLK
1.2/fPCLK
1.5/fPCLK
1.6/fPCLK
0.55
PLL bandwidth (3dB cutoff
frequency)
(2)
fBW
MHz
s
CLK output, See Figure 5
tpd(L)
Propagation delay time,
input to serial output (data
latency Figure 9)
TXEN at VDD, VIH=VDD
,
0.8/fPCLK
1.0/fPCLK
1.1/fPCLK
0.45
1/fPCLK
1.21/fPCLK
1.31/fPCLK
0.50
VIL=GND, RL=100 Ω
tH × fCLK0
Output CLK duty cycle
1-channel and 3-channel
mode
2-channel mode
0.49
3.8
0.53
0.58
10
tGS
TXEN Glitch suppression
pulse width(3)
VIH=VDD, VIL=GND, TXEN toggles between VIL and VIH,
μs
see Figure 12 and Figure 13
tpwrup
tpwrdn
Enable time from power
down (↑TXEN)
Time from TXEN pulled high to CLK and Dx outputs
enabled and transmit valid data; see Figure 13
0.24
0.5
2
ms
Disable time from active
TXEN is pulled low during transmit mode; time
11
mode (↓TXEN)
measurement until output is disabled and PLL is Shutdown;
see Figure 13
μs
ms
μs
twakup
Enable time from Standby
(↕PCLK)
TXEN at VDD; device in standby; time measurement from
PCLK starts switching to CLK and Dx outputs enabled and
transmit valid data; see Figure 13
0.23
0.4
2
tsleep
Disable time from Active
mode (PCLK stopping)
TXEN at VDD; device is transmitting; time measurement
from PCLK input signal stops until CLK + Dx outputs are
disabled and PLL is disabled; see Figure 13
100
(1) All typical values are at 25°C and with 1.8 V supply unless otherwise noted.
(2) The Maximum Limit is based on statistical analysis of the device performance over process, voltage, and temp ranges. This parameter
is functionality tested only on Automatic Test Equipment (ATE).
(3) The TXEN input incorporates glitch-suppression circuitry to disregard short input pulses. tGS is the duration of either a high-to-low or low-
to-high transition that is suppressed.
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12.0%
11.0%
9.0
8.5
8.0
7.5
7.0
6.5
6.0
4 MHz:
8.5%
8 MHz:
8.5%
20 MHz:
8.3%
RX PLL BW
10.0%
9.0%
8.0%
7.0%
6.0%
5.0%
4.0%
Spec Limit
1ChM
Spec
Limit
2ChM
9%
8.5%
Spec Limit 3ChM
30 MHz:
7.6%
15 MHz:
7.6%
7.5%
7%
65 MHz:
7.0%
TX PLL BW
0
100
200
300
400
500
600
700
0
10
20
30
40
50
60
70
PLL frequency − MHz
PCLK FREQUENCY - MHz
Figure 5. LVDS311 PLL Bandwidth (also showing the LVDS302 PLL bandwidth)
TIMING CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1ChM: x=0..29, fPCLK=15MHz; TXEN at
x
x
- 330 ps
+ 330 ps
VDD, VIH=VDD, VIL=GND, RL=100 Ω, test
30 × fPCLK
30 × fPCLK
(3)
pattern as in Table 12
1ChM: x=0..29,
fPCLK=4MHz to 15MHz
x – 0.1845
30 × fPCLK
x + 0.1845
30 × fPCLK
(4)
2ChM: x = 0..14, fPCLK = 30MHz
TXEN at VDD, VIH=VDD, VIL=GND,
RL=100 Ω, test pattern as in Table 13
x
x
- 330 ps
+ 330 ps
15 × fPCLK
15 × fPCLK
x + 0.1845
15 × fPCLK
(3)
Output Pulse Position,
tPPOSX ⇅serial data to ↑CLK; see
ps
(1)
(2)and Figure 11
2ChM: x=0..14,
fPCLK= 8MHz to 30MHz
x – 0.1845
15 × fPCLK
(4)
3ChM: x=0..9, fPCLK=65MHz,
TXEN at VDD, VIH=VDD, VIL=GND,
RL=100 Ω, test pattern as in Table 14
x
x
- 210 ps
+ 210 ps
10 × fPCLK
10 × fPCLK
x + 0.153
10 × fPCLK
(3)
3ChM: x=0..9,
fPCLK=20MHz to 65MHz
x - 0.153
10 × fPCLK
(4)
(1) This number also includes the high-frequency random and deterministic PLL clock jitter that is not traceable by the SN65LVDS302
receiver PLL; tPPosx represents the total timing uncertainty of the transmitter necessary to calculate the jitter budget when combined
with the SN65LVDS302 receiver;
(2) The pulse position min/max variation is given with a bit error rate target of 10–12; The measurement estimates the random jitter
contribution to the total jitter contribution by multiplying the random RMS jitter by the factor 14; Measurements of the total jitter are taken
over a sample amount of > 10–12 samples.
(3) The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temp ranges.
This parameter is functionality tested only on Automatic Test Equipment (ATE).
(4) These Minimum and Maximum Limits are simulated only.
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PARAMETER MEASUREMENT INFORMATION
t
DS
VIH
VIL
R[7:0], G[7:0], B[7:0];
VS, HS, DE, LS0, LS1,
TXEN, SWAP
t
DH
VIH
VIL
PCLK
t
R
Figure 6. Setup/Hold Time
150mV (nom)
V
OD
t
f
t
r
80%
0 V
20%
−150mV (nom)
Figure 7. Rise and Fall Time Definitions
975mV (nom)
825mV (nom)
V
or V
CLK+
Dx+
V
or V
CLK−
Dx−
R1 = 49.9
R2 = 49.9
CLK+, Dx+
V
OD
V
V
OCM
OCM
CLK−, Dx−
SN65LVDS311
V
OCM
(pp)
V
OCM
(ss)
C1 = 1 pF
C2 = 1 pF
NOTES:
A. 20 MHz output test pattern on all differental outputs (CLK, D0, D1, and D2):
this is achieved by: 1. Device is set to 3-channel-mode;
2. f
= 20 MHz
PCLK
3. Inputs R[7:3] = B[7:3] connected to VDD, all other data inputs set to GND.
B. C1, C2 and C3 includes instrumentation and fixture capacitance; tolerance± 20%; C, R1 and R2 tolerance± 1%.
C. The measurement of V (pp) and V (ss) are taken with test equipment bandwidth >1 GHz.
OCM
OC
Figure 8. Driver Output Voltage Test Circuit and Definitions
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CMOS
Data In
pixel
R7
pixel
(n)
(n+1)
R7
R7
R6
(n−1)
(n)
(n+1)
R6
R6
(n)
(n−1)
(n+1)
V
DD
/2
PCLK
t
PROP
CLK−
CLK+
R7 R6
CP
CP R7 R6
D0+
pixel
(n−1)
pixel
(n−2)
R6
(n)
R6
R7
(n−1)
(n−1)
R7
(n)
Figure 9. tpd(L) Propagation Delay Input to Output (LS0 = LS1 = 0)
SN65LVDS311
V
DDPLLD
V
1
2
DDPLLA
1
V
DD
Noise
Generator
100mV
10mF
V
DDLVDS
GND
1.8V
supply
Note: The generator regulates the
noise amplitude at point to the
target amplitude given under the table
1.6mH
1
Recommended Operating Conditions
Figure 10. Power Supply Noise Test Set-Up
t
CLK+
CLK−
CLK+
Next Cycle
Bit0
Current Cycle
Bit 0
Bit1
Bit2
Bitx
Bit1
D[0:m]+
t
PPOS0
Note:
t
PPOS1
1−channel mode: x=0..29; m=0
2−channel mode: x=0..14; m=1
3−channel mode: x=0....9; m=2
t
PPOS2
t
PPOSx
Figure 11. tSK(0) SubLVDS Output Pulse Position Measurement
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V /2
DD
TXEN
t
GS
PCLK
PLL Approaches Lock
VCO Internal Signal
t
pwrup
CLK
D0, D1, D2
Figure 12. Transmitter Behavior While Approaching Sync
<20 ns
2 s
3
s
Glitch Shorter
Will Be
Ignored
Less Than 20 ns
Spike Will be
Rejected
Than t
GS
Glitch Shorter
Than t Will Be
Ignored
GS
TXEN
CLK+
t
pwrup
t
pwrdn
t
GS
I
CC
t
GS
PCLK
Transmitter Disabled
(OFF)
Transmitter Aquires Lock
Transmitter Enabled
(ON)
Transmitter
Disabled
(OFF)
Transmitter
Turns OFF
Figure 13. Transmitter Enable Glitch Suppression Time
PCLK
twakeup
tsleep
CLK+
Transmitter Disabled
(OFF)
Transmitter Aquires Lock,
Outputs Still Disabled
Transmitter Enabled,
Output Data Valid
Transmitter
Enabled,
Output Data
Valid
Transmitter
Disabled
(OFF)
Figure 14. Standby Detection
Power Consumption Tests
Table 6 shows an example test pattern word.
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Table 6. Example Test Pattern Word
Word
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
0x7C3E1E7
7
C
3
E
1
E
7
R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0
0
0
VS HS DE
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
1
Typical IC Power Consumption Test Pattern
The typical power consumption test patterns consists of sixteen 30-bit transmit words in 1-channel mode, eight
30-bit transmit words in 2-channel mode and five 30-bit transmit words in 3-channel mode. The pattern repeats
itself throughout the entire measurement. It is assumed that every possible transmit code on RGB inputs has the
same probability to occur during typical device operation.
Table 7. Typical IC Power Consumption Test Pattern,
1-Channel Mode
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
2
0x0000007
0xFFF0007
0x01FFF47
0xF0E07F7
0x7C3E1E7
0xE707C37
0xE1CE6C7
0xF1B9237
0x91BB347
0xD4CCC67
0xAD53377
0xACB2207
0xAAB2697
0x5556957
0xAAAAAB3
0xAAAAAA5
3
4
5
6
7
8
9
10
11
12
13
14
15
16
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Table 8. Typical IC Power Consumption Test Pattern,
2-Channel Mode
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
2
3
4
5
6
7
8
0x0000001
0x03F03F1
0xBFFBFF1
0x1D71D71
0x4C74C71
0xC45C451
0xA3aA3A5
0x5555553
Table 9. Typical IC Power Consumption Test Pattern,
3-Channel Mode
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
2
3
4
5
0xFFFFFF1
0x0000001
0xF0F0F01
0xCCCCCC1
0xAAAAAA7
Maximum Power Consumption Test Pattern
The maximum (or worst-case) power consumption of the SN65LVDS311 is tested using the two different test
patterns shown in Table 10 and Table 11. The test patterns consist of sixteen 30-bit transmit words in 1-channel
mode, eight 30-bit transmit words in 2-channel mode and five 30-bit transmit words in 3-channel mode. The
pattern repeats itself throughout the entire measurement. It is assumed that every possible transmit code on
RGB inputs has the same probability to occur during typical device operation.
Table 10. Worst-Case Power Consumption Test Pattern
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
2
0xAAAAAA5
0x5555555
Table 11. Worst-Case Power Consumption Test Pattern
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
2
0x0000000
0xFFFFFF7
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Output Skew Pulse Position & Jitter Performance
The following test patterns are used to measure the output-skew pulse position and the jitter performance of the
SN65LVDS311. The jitter test pattern stresses the interconnect, particularly to test for ISI. Very long run-lengths
of consecutive bits incorporate very high and low data rates, maximinges switching noise. Each pattern is self-
repeating for the duration of the test.
Table 12. Transmit Jitter Test Pattern, 1-Channel Mode
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
0x0000001
0x0000031
0x00000F1
0x00003F1
0x0000FF1
0x0003FF1
0x000FFF1
0x0F0F0F1
0x0C30C31
0x0842111
0x1C71C71
0x18C6311
0x1111111
0x3333331
0x2452413
0x22A2A25
0x5555553
0xDB6DB65
0xCCCCCC1
0xEEEEEE1
0xE739CE1
0xE38E381
0xF7BDEE1
0xF3CF3C1
0xF0F0F01
0xFFF0001
0xFFFC001
0xFFFF001
0xFFFFC01
0xFFFFF01
0xFFFFFC1
0xFFFFFF1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
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Table 13. Transmit Jitter Test Pattern, 2-Channel Mode
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
0x0000001
2
0x000FFF3
3
0x8008001
4
0x0030037
5
0xE00E001
6
0x00FF001
7
0x007E001
8
0x003C001
9
0x0018001
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
0x1C7E381
0x3333331
0x555AAA5
0x6DBDB61
0x7777771
0x555AAA3
0xAAAAAA5
0x5555553
0xAAA5555
0x8888881
0x9242491
0xAAA5571
0xCCCCCC1
0xE3E1C71
0xFFE7FF1
0xFFC3FF1
0xFF81FF1
0xFE00FF1
0x1FF1FF1
0xFFCFFC3
0x7FF7FF1
0xFFF0007
0xFFFFFF1
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Table 14. Transmit Jitter Test Pattern, 3-Channel Mode
Word
Test Pattern:
R[7:4], R[3:0], G[7:4], G[3:0], B[7-4], B[3-0], 0,VS,HS,DE
1
0x0000001
0x0000001
0x0000003
0x0101013
0x0303033
0x0707073
0x1818183
0xE7E7E71
0x3535351
0x0202021
0x5454543
0xA5A5A51
0xADADAD1
0x5555551
0xA6A2AA3
0xA6A2AA5
0x5555553
0x5555555
0xAAAAAA1
0x5252521
0x5A5A5A1
0xABABAB1
0xFDFCFD1
0xCAAACA1
0x1818181
0xE7E7E71
0xF8F8F81
0xFCFCFC1
0xFEFEFE1
0xFFFFFF1
0xFFFFFF5
0xFFFFFF5
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
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TYPICAL CHARACTERISTICS
POWERDOWN, STANDBY SUPPLY CURRENT
vs
TEMPERATURE
SUPPLY CURRENT IDD
vs
TEMPERATURE
1.0
20
15
10
5
2-Channel Mode, 22 MHz (VGA)
2-Channel Mode, 11 MHz (HVGA)
Standby Current
Power-Down Current
0.1
0
-50
-30
-10
10
30
50
70
90
-50
-30
-10
10
30
50
70
90
Temperature - °C
Temperature - °C
Figure 15.
Figure 16.
SUPPLY CURRENT
vs
PCLK FREQUENCY
DIFFERENTIAL OUTPUT SWING
vs
PCLK FREQUENCY
200
190
180
170
160
150
140
130
120
110
100
30
25
20
15
10
5
85°C
25°C
3-Channel Mode
–40°C
2-Channel Mode
1-Channel Mode
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
FREQUENCY - MHz
FREQUENCY - MHz
Figure 17.
Figure 18.
CYCLE-TO-CYCLE OUTPUT JITTER
vs
PLL BANDWIDTH
PCLK FREQUENCY
500
400
300
200
100
0
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
Spec Limit 1ChM, 4 MHz: 8.5%
Spec Limit 2ChM8 MHz: 8.5%
Spec Limit 3ChM 20 MHz: 8.3%
Spec Limit 2ChM
30 MHz: 7.6%
Spec Limit 1ChM,
15 MHz: 7.6%
Spec Limit 3ChM
65 MHz: 7.0%
3-ChM
2-ChM
3-Channel Mode
2-Channel Mode
1-Channel Mode
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
FREQUENCY - MHz
FREQUENCY - MHz
Figure 19.
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
CYCLE-TO-CYCLE OUTPUT JITTER
vs
TEMPERATURE
OUTPUT PULSE POSITION
vs
TEMPERATURE
200
150
100
50
120
100
80
60
40
20
0
2-Channel Mode,
11 MHz (VGA)
2-Channel Mode,
f(PCLK) = 11 MHz
2-Channel Mode,
22 MHz (HVGA)
2-Channel Mode,
f(PCLK) = 22 MHz
0
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
TEMPERATURE - °C
Temperature - °C
Figure 21.
Figure 22.
DATA EYE PATTERN, 2-CHANNEL MODE
DATA EYE PATTERN, 3-CHANNEL MODE
250
175
250
190
2-Channel Mode,
f(PCLK) = 22 MHz
3-Channel Mode,
f(PCLK) = 65 MHz
0
0
–175
–250
–190
–250
500 ps/div
200 ps/div
Figure 23.
Figure 24.
QVGA OUTPUT WAVEFORM
VGA 2-CHANNEL OUTPUT WAVEFORM
249
190
250
190
1-Channel Mode,
f(PCLK) = 5.5 MHz
2-Channel Mode,
f(PCLK) = 22 MHz
0
0
–190
–251
–190
–250
1 ns/div
500 ps/div
Response Over 80-inch of FR-4 + 1m Coax Cable
Response Over 8-inch FR-4 + 1m Coax Cable
Figure 25.
Figure 26.
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TYPICAL CHARACTERISTICS (continued)
VGA 2-CHANNEL OUTPUT WAVEFORM
VGA3-CHANNEL OUTPUT WAVEFORM
249
249
190
190
2-Channel Mode,
f(PCLK) = 22 MHz
3-Channel Mode,
f(PCLK) = 22 MHz
0
0
–190
–251
–190
–251
500 ps/div
1 ns/div
Response Over 80-inch FR-4 + 1m Coax Cable
Response Over 80-inch FR-4 + 1m Coax Cable
Figure 27.
Figure 28.
XGA 3-CHANNEL OUTPUT WAVEFORM ON THE
SN65LVDS302 WHEN DRIVEN BY THE SN65LVDS311
XGA 3-CHANNEL OUTPUT WAVEFORM
249
190
0
3-Channel Mode,
f(PCLK) = 56 MHz
–190
–251
3-Channel Mode,
f(PCLK) = 56 MHz
300 ps/div
3.5 ns/div
Response Over 80-inch FR-4 + 1m Coax Cable
Response With 10-pF Load
Figure 29.
Figure 30.
PLL PHASE NOISE
OUTPUT RETURN LOSS
-50
-60
0
-70
-80
-90
–5
-100
-110
-120
-130
-140
-150
-160
-170
-180
f(PCLK) = 65 MHz
CLK
D0
–10
D2
D1
–15
0
500
1000
1500
2000
1
10
100
1k
10k
100k
1M
10M
FREQUENCY - Hz
FREQUENCY - Hz
Figure 31.
Figure 32.
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TYPICAL CHARACTERISTICS (continued)
OUTPUT COMMON MODE NOISE REJECTION
CROSSTALK
0
0
-20
–5
D0
CLK
-40
–10
–15
–20
D0 to D1
D1
D2
-60
D0 to D2
-80
-100
0
500
1000
1500
2000
0
500
1000
1500
2000
FREQUENCY - MHz
FREQUENCY - MHz
Figure 33.
Figure 34.
GTEM SAE J1752/3 EMI TEST
20
15
10
5
f(PCLK)=65MHz
2-ChM, f(PCLK)=22MHz
320MHz; 16dBuV
3-ChM, f(PCLK)=65MHz,
988MHz, 12dBuV
2-ChM, f(PCLK)=22MHz
683MHz; 12dBuV
3-ChM, f(PCLK)=65MHz,
282MHz
3-ChM, f(PCLK)=65MHz
777MHz; 11dBuV
1-ChM f(PCLK)=5MHz,
960MHz; 8dBuV
3-ChM, f(PCLK)=65MHz
113MHz; 6dBuV
0
0
200
400
600
800
1000
FREQUENCY - MHz
Figure 35.
A. Figure 35 shows a superimposed image of three EMI measurements with the device operating at f(PCLK) = 5MHz,
f(PCLK) = 22MHz, and f(PCLK) = 65MHz. This excellent EMI performance meets the system requirements of dense,
mobile designs with a noise floor of ~2 dBµV (-105 dBm) and all spurs being smaller than 16 dBµV (-101 dBm). The
test was performed in compliance with the SAE J1752/3 EMI test guidelines.
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APPLICATION INFORMATION
Preventing Increased Leakage Currents in Control Inputs
A floating (left open) CMOS input allows leakage currents to flow from VDD to GND. Do not leave any CMOS
Input unconnected or floating. Every input must be connected to a valid logic level VIH or VOL while power is
supplied to VDD. This also minimizes the power consumption of standby and power down mode.
Power Supply Design Recommendation
For a multilayer pcb, it is recommended to keep one common GND layer underneath the device and connect all
ground terminals directly to this plane.
Decoupling Recommendation
The SN65LVDS311 was designed to operate reliably in a constricted environment with other digital switching
ICs. In many designs, the SN65LVDS311 often shares a power supply with the application processor. The
SN65LVDS311 can operate with power supply noise as specified in Recommend Device Operating Conditions.
To minimize the power supply noise floor, provide good decoupling near the SN65LVDS311 power pins. The use
of four ceramic capacitors (2×0.01 μF and 2×0.1 μF) provides good performance. At the very least, it is
recommended to install one 0.1 μF and one 0.01 μF capacitor near the SN65LVDS311. To avoid large current
loops and trace inductance, the trace length between decoupling capacitor and IC power inputs pins must be
minimized. Placing the capacitor underneath the SN65LVDS311 on the bottom of the pcb is often a good choice.
VGA Application
Figure 36 shows a possible implementation of a VGA display.
The LVDS311 interfaces directly to a LCD driver with integrated FlatLink3G receiver. The SPI interface is used to
configure the display. The pixel clock rate of 22MHz assumes ≈10% blanking overhead and 60Hz display refresh
rate. The application assumes 24-bit color resolution.
2x0.1uF
FPC
GND
2.7V
1.8V
GND
GND
2.7V
1.8V
GND
2x0.01uF
OMAP3630
Application
Processor
Display with
Integrated
FL3G RX
CLK+
CLK-
22MHz
D0+
D0-
330Mbps
330Mbps
Pixel CLK
PCLK
22MHz
D1+
D1-
D[7:0]
D[15:8]
R[7:0]
G[7:0]
B[7:0]
D[23:16]
HS,VS,DE
27
HS,VS,DE
SN65LVDS311
1.8V
Serial port interface
(3-wire IF)
3
Figure 36. Typical VGA Display Application
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Dual LCD-Display Application
The example in Figure 37 shows a possible application setup driving two video mode displays from one
application processor. The data rate of 330 Mbps at a pixel clock rate of 5.5 MHz corresponds to QVGA
resolution at 60 Hz refresh rate and 10% blanking overhead.
2x0.1uF
2x0.1uF
FPC
GND
2.7V
1.8V
GND
GND
2.7V
1.8V
GND
2x0.01uF
2x0.01uF
Display Driver1
Application
Processor
(e.g. OMAP)
21
CLK+
CLK-
CLK+
CLK-
D0+
5.5MHz
PCLK
PCLK
Pixel CLK
PCLK
5.5MHz
18+3
R[5:0]
G[5:0]
B[5:0]
D0+
D0-
EN
330Mbps
SIN
SOUT
SCLK
D0-
D[5:0]
D[11:6]
D[17:12]
HS,VS,DE
R[5:0]
G[5:0]
B[5:0]
HS,VS,DE
HS,VS,DE
SN65LVDS311
SN65LVDS302
Display Driver2
PCLK
EN
1.8V
1.8V
SIN
SOUT
SCLK
Figure 37. Example Dual-QVGA Display Application
Typical Application Frequencies
The SN65LVDS311 supports pixel clock frequencies from 4MHz to 65MHz over 1, 2, or 3 data lanes. Table 15
provides a few typical display resolution examples and shows the number of data lanes necessary to connect the
LVDS311 with the display. The blanking overhead is assumed to be 20%. Often, blanking overhead is smaller,
resulting in a lower data rate. Furthermore, the examples in the table assumes a display frame refresh rate of 60
Hz or 90 Hz. The actual refresh rate may differ depending on the application-processor clock implementation.
Table 15. Typical Application Data Rates & Serial Lane Usage
Display Screen
Resolution
Visible
Pixel Count Overhead
Blanking
Display
Refresh
Rate
Pixel Clock Frequency
[MHz]
Serial Data Rate Per Lane
1-ChM
2-ChM
3-ChM
176x220 (QCIF+)
240x320 (QVGA)
640x200
38,720
76,800
20%
90 Hz
60 Hz
4.2MHz
5.5MHz
125 Mbps
166 Mbps
276 Mbps
316 Mbps
335 Mbps
332 Mbps
432 Mbps
442 Mbps
128,000
146,432
154,880
153,600
200,000
204,800
307,200
327,680
409,920
480,000
786,432
9.2MHz
138 Mbps
158 Mbps
167 Mbps
166 Mbps
216 Mbps
221 Mbps
332 Mbps
354 Mbps
443 Mbps
352x416 (CIF+)
352x440
10.5MHz
11.2MHz
11.1MHz
14.4MHz
14.7MHz
22.1MHz
23.6MHz
29.5MHz
34.6MHz
56.6MHz
320x480 (HVGA)
800x250
640x320
640x480 (VGA)
1024x320
221 Mbps
236 Mbps
295 Mbps
346 Mbps
566 Mbps
854x480 (WVGA)
800x600 (SVGA)
1024x768 (XGA)
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Calculation Example: HVGA Display
This example calculation shows a typical Half-VGA display with these parameters:
Display Resolution:
Frame Refresh Rate:
480 x 320
58.4 Hz
Hsync = 5
Visible area = 480 column
HFP = 20
Horizontal Visible Pixel:
Horizontal Front Porch:
Horizontal Sync:
480 columns
20 columns
5 columns
3 columns
Vsync = 5
VBP = 3
Horizontal Back Porch:
Visible area
= 320 lines
Visible area
Vertical Visible Pixel:
Vertical Front Porch:
Vertical Sync:
320 lines
10 lines
5 lines
Vertical Back Porch:
3 lines
VFP = 10
Entire display
Figure 38. HVGA Display Parameters
Calculation of the total number of pixel and Blanking overhead:
Visible Area Pixel Count:
Total Frame Pixel Count: (480+20+5+3) × (320+10+5+3) = 171704 pixel
Blanking Overhead: (171704-153600) ÷ 153600 = 11.8 %
The application requires following serial-link parameters:
480 × 320 = 153600 pixel
Pixel Clk Frequency:
Serial Data Rate:
171704 × 58.4 Hz = 10.0MHz
1-channel mode: 10.0MHz × 30 bit/channel = 300 Mbps
2-channel mode: 10.0MHz × 15 bit/channel = 150 Mbps
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN65LVDS311YFFR
SN65LVDS311YFFT
ACTIVE
ACTIVE
DSBGA
DSBGA
YFF
YFF
49
49
3000 RoHS & Green
250 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
LVDS311
LVDS311
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jun-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65LVDS311YFFR
SN65LVDS311YFFT
DSBGA
DSBGA
YFF
YFF
49
49
3000
250
180.0
180.0
8.4
8.4
2.93
2.93
2.93
2.93
0.81
0.81
4.0
4.0
8.0
8.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jun-2015
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN65LVDS311YFFR
SN65LVDS311YFFT
DSBGA
DSBGA
YFF
YFF
49
49
3000
250
182.0
182.0
182.0
182.0
20.0
20.0
Pack Materials-Page 2
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